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1D 2D 3D 4D 5D 6D 7D 8D Team Problem Containment Root Cause Corrective Corrective Action Preventive Congratulate Members Description Definition Action Implementation Action the Team Definition & Validation Definition

Preliminary 8D Report:

REF50xx Output Voltage Temperature Drift Issue

Prepared by: Beth Cleveland / Olu Aderibigbe

November 4, 2014

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1D Team Members

• Beth Cleveland (PA CQE) • Olu Aderibigbe (PA CQE Mgr.) • Rod Madsen (HPA Reliability) • Joe Roybal (HPA Quality Director) • Marco Gardner (Op Amp Product Line Mgr.) • Vaibhav Kumar (Op Amp Design Mgr.) • Jerry Doorenbos (PA CTO) • Amy Warner (PA Business Unit Mgr., VP) • Sandra Alvarez (Op Amp Planning) • Ted Hess (PA F&O) • Gene Huang (PA Planning Mgr.) • Mack Good (PA F&O Mgr.) • Ray Ochotorena Jr. (AEO/Product Engr. Mgr.) • Pooja Singh (AEO/Product Engineer)

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• Marek Lis (PA Apps Engineer) • Mark Irwin (Characterization Engr. Mgr.) • Kevin Huckins (PA Design Engineer) • Srinivas Pulijala (PA Design Engineer) • Amit Nangia (SC Packaging DFM) • Luis Rivera (SC Packaging DFM) • Josh Roberge (DMOS5 Product Engineering) • Al Griffin (TI Fellow)

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2D Problem Description • Electrical Failure Analysis (EFA) following a customer return revealed that the Output

Voltage Temperature Drift on the REF50xx family of devices may not meet the current datasheet maximum limit of 3 ppm/˚C across the temperature range of -40˚C to 125˚C (see Figure 1). The devices will however meet a maximum drift limit of 8 ppm/˚C

• In addition, Output Voltage Initial Accuracy will exhibit a shift of up to 0.05% after Printed Circuit Board (PCB) reflow, resulting in a total Output Voltage Initial Accuracy of ~0.1%. See Figure 2 for TI test results provided for informational purposes only. All other parameters are within datasheet limits

• This test / packaging issue only affects the high-grade versions of this device family. See Figure 3 for the full list of affected devices

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2D Problem Description

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Figure 1: Output Voltage Temperature Drift performance over temperature

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2D Problem Description

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Figure 2: Initial Accuracy Performance

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2D Problem Description

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Figure 3: Full list of affected devices

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3D Corrective & Containment Plan / Actions • Stop-ship placed on all REF50xx high-grade devices (Complete, 9/4/14)

• Stop-build placed on all REF50xx high-grade devices (Complete, 9/12/14) • Publish customer waiver (Complete, 10/29/14)

• Provides summary of device datasheet non-conformance • If signed, allows shipment of affected devices to customers

• Affected Material: Based on currently available information, all REF50xx lots are

affected by this issue; it is not possible to provide a list of affected lots or Date Codes (DCs) or Lot Trace Codes (LTCs)

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4D Root Cause Definition / Verification

• Customer return as well as Product Distribution Center (PDC) units from multiple LTCs were used for subsequent and extensive EFA; it was confirmed that both device package offerings (MSOP, SOIC) were affected by this issue

• Extensive drift testing was conducted across multiple temperature readpoints to determine actual device performance:

– Pre-PCB Reflow: Device family will exhibit a maximum Output Voltage Temperature Drift of 3 ppm/˚C across the temperature range of -10˚C to 125˚C

– Post-PCB Reflow: Device family will exhibit a maximum Output Voltage Temperature Drift of 5 ppm/˚C across the temperature range of -10˚C to 125˚C

– Pre-/Post-PCB Reflow: Device family will exhibit a maximum Output Voltage Temperature Drift of 8 ppm/˚C from -40˚C to 125˚C

• Output Voltage Temperature Drift Recovery (Post-PCB Reflow) – EFA revealed that baking devices at 125˚C for 30 minutes will recover them to

aforementioned pre-PCB reflow maximum drift of 3 ppm/˚C across the temperature range of -10˚C to 125˚C

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4D Root Cause Definition / Verification

Fault Tree Analysis / Fishbone Diagram

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4D Root Cause Definition / Verification

• Drift Oven: Temperature tolerance specification was set at ±5˚C; this is believed to be too wide of a temperature range for screening high-grade devices

• Test Correlation: Ensure correlation between drift ovens and Automated Test Equipment (ATE) data

• Test Capability: Ensure that appropriate drift guardbands are in place

• Changes: Review all applicable process / product changes for possible effects on device performance

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5D Corrective Action Definition / Implementation • Drift Oven Accuracy / Capability Study (AEO, TIM)

– Tighten temperature tolerance specifications for improved oven temperature accuracy – Conduct correlation study between drift ovens and Automated Test Equipment (ATE) device

data – Conduct capability study between ovens, drift boards, and readout boards to ensure that

appropriate guardbands are in place

• Implement additional readpoint at -10C for drift testing (AEO) – Previous readpoints were -40C, 25C, and 125C

• Additional C/As to be determined

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6D Corrective Action Validation / Risk Assessment • Drift Oven Accuracy / Capability Study

– Tightened temperature tolerance specifications for improved oven temperature accuracy (Completed, 10/27/14)

– Completed correlation study between drift ovens and Automated Test Equipment (ATE) device data (Complete, 10/28/14)

– Completed capability study between ovens, drift boards, and readout boards to ensure that appropriate guardbands are in place (Complete, 10/28/14)

• Implement additional readpoint at -10C for drift testing, product process flow document updated accordingly (Complete, 10/31/14)

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6D Corrective Action Validation / Risk Assessment Risk Assessment • Temperature drift varies across the REF50xx device family and from lot-to-lot • For systems that pass initial testing at -10C or lower, no reliability concerns are

expected

• For systems with frequent startups, if calibration is conducted each time, Initial Accuracy will remain stable

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7D Preventive Action Definition / Implementation • Die Redesign to optimize drift curvature (PA Design, 1Q15)

– FIB experiments (11/21/14) – Photomask Generation (PG) (12/31/14)

• Fan-Out die redesign to all REF50xx family of devices (PA Design, TBD)

8D Close with Customer / Thank the Team • Preliminary 8D published (11/5/14)