INTERNAL ARCHITECTURE OF 89C52.

The 8052 has the following on-chip facilities:

4k ROM (EPROM on 8751)

128 byte RAM

USRT

32 Input-output port lines

TWO 16-bit timer/ count

Six interrupt sources and

On-chip clock oscillator and power –on- reset circuitry.

The other members of this family, such as 8053, have one extra timer/counter, 8k

ROM/EPROM and 256 byte RAM, while 8031and 8032 are corresponding ROM-less versions

of 8052,respectivily. All these are also available in CMOS versions. The 8051 family includes a

large numbers of members from many manufacturers.

SALIENT FEATURES

The 8051 can be configured to bypass the internal 4k RAM and run solely with external

program memory. For this its external access ( ) pin 31 has to be grounded, which makes it

equivalent to 8031. The program store enable (PSEN) signal acts as read pulse for program

memory. The data memory is external only and a separate RD* signal is available for reading its

contents.

Use of external memory requires that three of its 8-bit ports (out of four) are configured

to provide data/address multiplexed bus, Hi address bus and control signals related to external

memory use. The RXD and TXD ports of UART also appear on pins 10 and 11 of 8051 and

8031, respectively. One 8-bit port, which is bit addressable and extremely useful for control

applications, still remains free for use.

The UART utilizes one of the internal timers for generation of baud rate. The crystal used

for generation of CPU clock has therefore to be chosen carefully. The 3.579MHz crystal;

available abundantly, can provide a baud rate of 1200.

The 256-byte address space is utilized by the internal RAM and special function registers

(SFRs)array which is separate from external RAM space of 64k. the 00-7f space is occupied by

the RAM and the 80-FF space by the SFRs. The 128-byte internal RAM has been utilized in the

following fashion:

00-1F: Used for four banks of eight registers of 8-bit each. The four banks may be selected by

soft ware any time during the program.

20-2F: The 16 bytes may be used as 128 bits oriented programs.

30-7F This area is used for temporary storage, pointers and stack. On reset, the stack starts at 08

and gets incremented during use.

PIN DIAGRAM OF 89C52

PIN DETAILS OF 8951

VSS - Cir unit ground potential.

VCC - 5-volt power supply input for normal operation and program verification.

PORT 0

Port o is an 8-bit open drain BI directional input output port. It is also the multiplexed

low ordered address and data bus when using external memory. it is used for data output during

program verification Port 0 can sink (and in bus operations can source) 8 LSTTL loads.

PORT 1

Port 1 is an 8 bit quasi bi-directional I/o port. It is also used for low order address byte

during program verification. Port 1 can sink / source 4 LSTTL loads.

PORT 2

Port 2 is an 8 bit quasi bi-directional i/o port. It also emits the high order address byte

when according external memory. It is used for the high order address and the control signals

during program verification. Port 2 can sink / source 4 LSTTL loads.

PORT 3

Port 3 is an 8 bit quasi bi-directional i/o port with internal pull ups. It also serves the

function of various special features of the MCS-51th. Family as listed below:

Port pin Alternate function

P3.0 RXD (serial input port)

P3.1 TXD (serial input port)

P3.2 INTO (external interrupt)

P3.3 INT1 (external interrupt)

P3.4 TO (timer /counter 1 external input)

P3.5 T1 (timer/ counter 1 external input)

P3.6 WR (external data memory write strobe)

P3.7 RD (external data memory read strobe)

The output latch corresponding to a secondary function must be programmed to a one (1)

for that function to operate. Port 3 can sink /source 4 LSTTL loads.

RST

A high on this pin for two-machine cycle while the oscillator is running rests the devices.

A small external pull down resistor (=8.2 kilo ohms) from RST to VSS permits power on reset

when a capacitor (=10 microfarad) is also connected from this pin to VCC.

ALE

Address latch enable output for latching the low byte of the during access to external

memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during an

external data memory access at which time one ALE pulse is skipped. ALE can sink / source 8

LSTTL inputs.

PSEN

The program store enable output for latching the low byte of the during access to external

memory six oscillator periods except during external data memory access PSEN remains high

during internal program memory. Do not float EA during normal operation.

XTAL 1

Input to the inverting amplifier that forms the part of the oscillator and input to the

internal clock generator. XTAL2 receives the oscillator signal when an external oscillator used.

XTAL 2

Output of the inverting amplifier that forms the part of the oscillator and input to the

interval clock generator. XTAL2 receives the oscillator signal when an external oscillator

HARDWARE AND SOFTWARE REQUIREMENTS:-

SOFTWARE REQUIREMENTS :-

1)    EMBEDDED C PROGRAMMING.   

               

HARDWARE REQUIREMENTS:-

1)    8051 MICROCONTROLLER.

2)    DC MOTORS.

3)    RF TRANSMITTERS AND RECIEVERS. Etc.

4) LEAD ACID BATTERY 12V 5) BUZZER 6) SENSOR 7) LCD DISPLAY

INTRODUCTION TO MICROCONTROLLER

A micro-controller can be compared to a small stand alone computer, it is a very powerful

device, which is capable of executing a series of pre-programmed tasks and interacting with

other hardware devices. Being packed in a tiny integrated circuit (IC) whose size and weight is

usually negligible, it is becoming the perfect controller for robots or any machines requiring

some kind of intelligent automation. A single microcontroller can be sufficient to control a small

mobile robot, an automatic washer machine or a security system. Any microcontroller contains a

memory to store the program to be executed, and a number of input/output lines that can be used

to interact with other devices, like reading the state of a sensor or controlling a motor.

Nowadays, microcontrollers are so cheap and easily available that it is common to use them

instead of simple logic circuits like counters for the sole purpose of gaining some design

flexibility and saving some space. Some machines and robots will even rely on a multitude of

microcontrollers, each one dedicated to a certain task. Most recent microcontrollers are 'In

System Programmable', meaning that you can modify the program being executed, without

removing the microcontroller from its place.

Today, microcontrollers are an indispensable tool for the robotics hobbyist as well as for the

engineer. Starting in this field can be a little difficult, because you usually can't understand how

everything works inside that integrated circuit, so you have to study the system gradually, a

small part at a time, until you can figure out the whole image and understand how the system

works.

The 89C51 is a single chip microcomputer with I/O port, timer, clock generator, Data

memory, program memory stack, ADC and serial ports etc.

8 bit CPU with registers A and B.

16 bit Program Counter and Data Pointer.

8 bit Program Status Word.

8 bit stack pointer.

Internal ROM of 8K bytes.

Internal RAM of 256 bytes, 4 register banks each containing 8registers.

Two 16 bit timer / counter.

Full duplex serial data receiver/transmitter.

Special function registers like TCON, TMOD and SCON etc.

Two external and three internal interrupt sources.

Microcontrollers are used in automatically controlled products and devices such as

automobile engine control systems, home security systems, hotel security and monitoring

systems, remote controls, office machines, appliances, power tools, and toys. By reducing the

size and cost compared to a design that uses a separate microprocessor, memory, and

input/output devices, microcontrollers make it economical to digitally control even more devices

and processes.

THE 8051 MICROCONTROLLER ARCHITECTURE

The 8051 is the name of a big family of microcontrollers. The device which we are going to use

along this tutorial is the 'AT89S52' which is a typical 8051 microcontroller manufactured by

Atmel™. Note that this part doesn't aim to explain the functioning of the different components of

a 89S52 microcontroller, but rather to give you a general idea of the organization of the chip and

the available features, which shall be explained in detail along this tutorial.

This figures shows the main features and components that the designer can interact with. You

can notice that the 89S52 has 4 different ports, each one having 8 Input/output lines providing a

total of 32 I/O lines. Those ports can be used to output DATA and orders do other devices, or to

read the state of a sensor, or a switch. Most of the ports of the 89S52 have 'dual function'

meaning that they can be used for two different functions: the fist one is to perform input/output

operations and the second one is used to implement special features of the microcontroller like

counting external pulses, interrupting the execution of the program according to external events,

performing serial data transfer or connecting the chip to a computer to update the software.

Each port has 8 pins, and will be treated from the software point of view as an 8-bit variable

called 'register', each bit being connected to a different Input/Output pin.

You can also notice two different memory types: RAM and EEPROM. Shortly, RAM is used to

store variable during program execution, while the EEPROM memory is used to store the

program itself, that's why it is often referred to as the 'program memory'. The memory

organization will be discussed in detail later

It is clear that the CPU (Central Processing Unit) is the heart of the microcontrollers, It is the

CPU that will Read the program from the FLASH memory and execute it by interacting with the

different peripherals discussed above.

the pin configuration of the 89S52, where the function of each pin is written next to it, and, if it

exists, the dual function is written between brackets. The pins are written in the same order as in

the block diagram of figure 1.2.A, except for the VCC and GND pins which I usually note at the

top and the bottom of any device. Note that the pin that have dual functions, can still be used

normally as an input/output pin. Unless you program uses their dual functions, All the 32 I/O

pins of the microcontroller are configured as input/output pins.

Most of the function of the pins of the 89S52 microcontroller will be discussed in detail, except

for the pins required to control an external memory, which are the pins number 29, 30 and 31.

Since we are not going to use any external memory, pins 29 and 30 will be ignored through all

the tutorial, and pin 31 (EA) always connected to VCC (5 Volts) to enable the micro-controller

to use the internal on chip memory rather than an external one .

PIN DIAGRAM OF MICROCONTROLLER (8051)

PIN DETAILS OF 8051

The on-chip oscillator of 8031 can be used to generator system clock. Depending upon

version of the device, crystals from 3.5 to 12 MHz may be used for this purpose. The system

clock is internally divided by 6 and the resultant time period becomes one processor cycle. The

instructions take mostly one or two processor cycles. The ALE (address latch enable) pulse rate

is 1/6th of the system clock, except during access of internal program memory, and thus can be

used for timing purposes.

The two internal timers are wired to the system clock and persecuting factor is decided by

the software apart from the count stored in the two bytes of the timer control registers. One of the

counters, as mentioned earlier, is used for generation of baud rate clock for the UART. It would

be of interest to point out that the 8052 has a third timer which is usually used for generation of

baud rate.

VSS

Circuit ground potential.

VCC

5-volt power supply input for normal operation and program verification.

PORT 0

Port o is an 8-bit open drain BI directional input output port. It is also the multiplexed

low ordered address and data bus when using external memory. it is used for data output during

program verification Port 0 can sink (and in bus operations can source) 8 LSTTL loads.

PORT 1

Port 1 is an 8 bit quasi bi-directional I/O port. It is also used for low order address byte

during program verification. Port 1 can sink / source 4 LSTTL loads.

PORT 2

Port 2 is an 8 bit quasi bi-directional I/O port. It also emits the high order address byte

when according external memory. It is used for the high order address and the control signals

during program verification. Port 2 can sink / source 4 LSTTL loads.

PORT 3

Port 3 is an 8 bit quasi bi-directional I/O port with internal pull ups. It also serves the

function of various special features of the MCS-51th.

Family of alternate functions are listed below

P3.0 RXD (serial input port)

P3.1 TXD (serial input port)

P3.2 INTO (external interrupt)

P3.3 INT1 (external interrupt)

P3.4 TO (timer /counter 1 external input)

P3.5 T1 (timer/ counter 1 external input)

P3.6 WR (external data memory-write strobe)

P3.7 RD (external data memory read strobe)

The output latch corresponding to a secondary function must be programmed to a one (1)

for that function to operate. Port 3 can sink /source 4 LSTTL loads.

RST

A high on this pin for two-machine cycle while the oscillator is running rests the devices.

A small external pull down resistor (=8.2 kilo ohms) from RST to VSS permits power on reset

when a capacitor (=10 microfarad) is also connected from this pin to VCC.

ALE

Address latch enable output for latching the low byte during access to external memory.

ALE is activated at a constant rate of 1/6 the oscillator frequency except during an external data

memory access at which time one ALE pulse is skipped.

PSEN

The program store enable output for latching the low byte of the during access to external

memory six oscillator periods except during external data memory access PSEN remains high

during internal program memory. Do not float EA during normal operation.

XTAL 1

Input to the inverting amplifier that forms the part of the oscillator and input to the

internal clock generator. XTAL2 receives the oscillator signal when an external oscillator used.

XTAL 2

Output of the inverting amplifier that forms the part of the oscillator and input to the

interval clock generator. XTAL2 receives the oscillator signal when an external oscillator used.

Power Supply

The AT89C52 operates with a single +5V power supply. It consists of two power supply

pins Vcc and Vss. Power supply is given to Vcc with respect to Vss, which is power supply ground.

Reset Circuit

In AT89C52 the reset input is RST pin. A reset is accomplished by holding the RST pin

high for atleast two machine cycles( 24 oscillator periods), while the oscillator is running. The

CPU responds by generating an internal reset with the timing.

The reset in AT89C52 is positive active, which means that the processor runs when the

reset pin is held low. This is in contrast to the other devices that all have a negatively active

reset. The AT89C51 has an internal pull down and RC delay circuit built in to delay the

processor setup until the built in oscillator operation has stabilized.

Program Memory

Up to 8 Kbytes of the program memory can reside on the chip. In addition the device

addresses up to 64 Kbytes of program memory external to the chip.

Data Memory

This microcontroller has a 256 on-chip RAM. In addition it can address up to 64K bytes

of external data memory.

INSTRUCTION SET

Moving Data

Mnemonic OperationMOV A, #n Copy the immediate data byte n to the A register

MOV A, Rr Copy data from register Rr to register AMOV Rr, A Copy data from register A to register RrMOV Rr, #n Copy the immediate data byte n to register RrMOV DPTR, #nn Copy the immediate 16-bit number nn to the DPTR register

LOGICAL OPERATIONS

Mnemonic Operation

MOV A, #OF1h Move the immediate data byte F1h to the A registerMOV A, RO Copy the data in register RO to register AMOV DPTR, #0ABCDh Move the immediate data bytes ABCDh to the DPTRMOV R5, A Copy the data in register A to register R5MOV R3, # 1 Ch Move the immediate data byte 1Ch to register R3

CAUTION

It is impossible to have immediate data as a destination.

All number must star with a decimal number (0-9), or the assumes the number is a

label.

Register-to-register moves using the register addressing mode occur between register

A and RO to R7.

Mnemonic OperationRL Rotate a byte to the left; the Most Significant Bit (MSB) becomes the Least Significant Bit (LSB)RLC Rotate a byte and the carry bit left; the carry becomes the LSB, the MSB becomes the carryRR Rotate a byte to the right; the LSB becomes the MSBRRC Rotate a byte carry to the right; the LSB becomes the carry, and the carry the MSB SWAP Exchange the low and high nibbles in a byte

CAUTION

If the direct address destination is one of the port SFRs, the data latched in the SFR,

not the pin data is used.

No flags are affected unless the the direct address is the PSW.

Only internal RAM or SFRs may be logically manipulated.

CAUTION

Remember: No match flags are affected.

All 8-bit address contents overflow from FFh to 00h.

DPTR is 16 bits; DPTR overflows from FFFFh to 0000h.

The 8-bit address contents underflow from 00h to FFh.

There is no DEC DPTR to match the INC DPTR.

JUMP AND CALL INSTRUCTIONS

Conditional Jumps

Mnemonic Operation

JC radd Jump relative if the Carry flag is set to 1

JNC radd JUMP relative if the Carry flag is reset to 0

JB b, radd JUMP relative if addressable bit set to 1

JNB b, radd JUMP relative if addressable bit is set, and clear the

addressable bit to 0

Unconditional Jumps

Mnemonic Operation

JMP @A+DPTR Jump to the address formed by adding A to the DPTR; this

is an unconditional

Jump and will always be done; the address can be anywhere

Mnemonic Operation

INC destination Increment destination by 1

DEC destination Decrement destination by 1

ADD/ADDC destination, source Add source to destination with/with carry © flag

SUBB destination, source Multiply the contents of register A and B

MUL AB Divide the contents of register A by the contents

of register B

DA A Decimal Adjust the A register

in program

memory; A, the DPTR, and the flags are unchanged

AJMP sadd Jump to absolute short range address sadd; this an unconditional jump

and is always taken;no flags are affected

LJMP sadd Jump to absolute long range address ladd; this is an unconditional

jump and is always taken; no flags are affected

SJMP radd Jump to relative address radd; this is an unconditional jump and is

always taken; no flags are affected

NOP Do nothing and go to the next is instruction; NOP (no operational) is

used to waste time in a software timing loop, or to leave room in a program for later

additions; no flags are affected

DJNZ decrements first, then check for 0. A location set to 00h and then decremented

goes to FFh, then Feh, and so on, down to 00h.

CJNE does nor change the contents of any register or RAM location. It can change

the Carry flag to 1 if the destination byte is less than the source byte.

There is no zero flag; the JZ and JNZ instructions check the contents of the A

register for 0.

JMP @A+DPTR does not change A, DPTR, or any flags,

The student version of A51 will not assemble more than 400h bytes of code (0000to

03FFh). Addresses greater than 03FFh are not assembled.