88F6281, 88F6192, and 88F6180 Functional SpecificationsDocument Conventions Note: Provides related...

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Doc. No. MV-S104860-U0, Rev. C

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88F6180, 88F6190, 88F6192, and 88F6281Integrated ControllerFunctional Specifications

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88F6180/88F619x/88F6281 Functional Specifications

Doc. No. MV-S104860-U0 Rev. C Copyright © 2008 MarvellPage 2 Document Classification: Proprietary Information December 2, 2008, Preliminary

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Table of Contents

Copyright © 2008 Marvell Doc. No. MV-S104860-U0 Rev. CDecember 2, 2008, Preliminary Document Classification: Proprietary Information Page 3

Table of ContentsPreface.......................................................................................................................................................17

About this Document.......................................................................................................................................17

Relevant Devices ............................................................................................................................................17

Related Documentation...................................................................................................................................17

Document Conventions...................................................................................................................................19

1 Overview.......................................................................................................................................201.1 Block Diagrams ...............................................................................................................................................21

1.2 Overview of Functions and Interfaces.............................................................................................................25

1.3 Differences Between the 88F6180, 88F6190, 88F6192, and 88F6281 Devices.............................................31

2 Address Map ................................................................................................................................342.1 Sheeva™ CPU Core Address Decoding.........................................................................................................34

2.2 TDM (SLIC/Codec) Address Map (88F6192/88F6281 Only) ..........................................................................37

2.3 PCI Express Address Decoding......................................................................................................................37

2.4 SATA Address Decoding (88F619x/88F6281)................................................................................................39

2.5 Gigabit Ethernet Address Decoding................................................................................................................39

2.6 USB Address Decoding ..................................................................................................................................39

2.7 Security Accelerator Address Decoding..........................................................................................................39

2.8 XOR Engine Address Decoding......................................................................................................................40

2.9 TWSI Address Decoding.................................................................................................................................40

2.10 Audio Interface Address Map (88F6180/88F6192/88F6281 Only)..................................................................40

2.11 SDIO Address Map .........................................................................................................................................40

2.12 Transport Stream (TS) Address Map (88F6192/88F6281 Only) .....................................................................41

2.13 Default Address Map.......................................................................................................................................41

3 Sheeva™ CPU Core.....................................................................................................................43

4 DDR SDRAM Controller ..............................................................................................................444.1 SDRAM Controller Implementation .................................................................................................................44

4.2 DDR SDRAM Addressing................................................................................................................................45

4.3 SDRAM Timing Parameters............................................................................................................................47

4.4 DRAM Burst ....................................................................................................................................................48

4.5 SDRAM Bank Interleaving ..............................................................................................................................48

4.6 SDRAM Open Pages ......................................................................................................................................49

4.7 SDRAM Refresh..............................................................................................................................................49

4.8 SDRAM Initialization .......................................................................................................................................49

4.9 SDRAM Operation Register ............................................................................................................................50



4.10 SDRAM Self Refresh Mode ............................................................................................................................50

4.11 Heavy Load Support .......................................................................................................................................52

4.12 SDRAM Clocking ............................................................................................................................................52

4.13 SDRAM Address/Data Drive ...........................................................................................................................52

4.14 SDRAM Read Data Sample............................................................................................................................53

4.15 DDR2 On Die Termination (ODT) ...................................................................................................................53

5 Time Division Multiplexing (TDM) Unit (88F6192 and 88F6281 Only) .....................................565.1 Functional Description.....................................................................................................................................56

5.2 TDM Protocol Specification.............................................................................................................................59

5.3 TDM (SLIC/Codec) Registers Access via SPI.................................................................................................71

6 PCI Express Interface..................................................................................................................746.1 Functional Description.....................................................................................................................................74

6.2 Link Initialization..............................................................................................................................................76

6.3 Master Memory Transactions..........................................................................................................................76

6.4 Master I/O Transactions..................................................................................................................................77

6.5 Master Configuration Transactions .................................................................................................................77

6.6 Target Memory Transactions ..........................................................................................................................78

6.7 Target I/O Transactions ..................................................................................................................................78

6.8 Target Configuration Transactions..................................................................................................................78

6.9 Target Special Cases......................................................................................................................................79

6.10 Messages........................................................................................................................................................79

6.11 Message Signaled Interrupts (MSI).................................................................................................................81

6.12 Locked Transactions .......................................................................................................................................81

6.13 Arbitration and Ordering..................................................................................................................................81

6.14 PCI Express Register Access .........................................................................................................................82

6.15 Hot Reset ........................................................................................................................................................83

6.16 Link Disable.....................................................................................................................................................83

6.17 Power Management ........................................................................................................................................83

6.18 Error Handling .................................................................................................................................................84

6.19 Loopback Modes.............................................................................................................................................86

6.20 Peer-to-Peer Traffic.........................................................................................................................................88

7 Serial-ATA (SATA) II Interface (88F619x and 88F6281 Only) ...................................................897.1 Serial ATA II Host Controller (SATAHC) .........................................................................................................89

7.2 SATAHC Block Diagram .................................................................................................................................90

7.3 SATAHC Initialization......................................................................................................................................90

7.4 Host Direct Control Over the Hard Disk Drive .................................................................................................90

7.5 LED Indications ...............................................................................................................................................91

7.6 EDMA Operation .............................................................................................................................................91

7.7 BIST ..............................................................................................................................................................111

Table of Contents


7.8 Vendor Unique ..............................................................................................................................................112

7.9 Protocol Based Port Select ...........................................................................................................................112

8 Gigabit Ethernet Controller ......................................................................................................1138.1 Port Features ................................................................................................................................................113

8.2 Functional Overview......................................................................................................................................114

8.3 DMA Functionality .........................................................................................................................................116

8.4 Receive Frame Processing ...........................................................................................................................134

8.5 Marvell® Header Support..............................................................................................................................136

8.6 Distributed Switching Architecture (DSA) Tag Support .................................................................................139

8.7 Ethernet Interrupts ........................................................................................................................................143

8.8 Transmit Weighted Round-Robin Arbitration.................................................................................................144

8.9 Token Rate Configuration .............................................................................................................................146

8.10 Transmit Queues Egress Jitter Pacing (EJP) Arbitration ..............................................................................147

8.11 Network Interface (10/100/1000 Mbps).........................................................................................................150

8.12 Auto-Negotiation ...........................................................................................................................................153

8.13 Data Blinder ..................................................................................................................................................154

8.14 Inter-packet Gap ...........................................................................................................................................154

8.15 Illegal Frames................................................................................................................................................154

8.16 Backpressure Mode ......................................................................................................................................155

8.17 Flow Control ..................................................................................................................................................155

8.18 Serial Management Interface (SMI) ..............................................................................................................157

8.19 Link Detection and Link Detection Bypass (ForceLinkPass*) .......................................................................158

8.20 Precise Time Protocol (PTP).........................................................................................................................158

8.21 Network Management Interface Counters.....................................................................................................168

8.22 Port MIB Counters.........................................................................................................................................168

9 Universal Serial Bus (USB 2.0) Interface.................................................................................173

10 Cryptographic Engines and Security Accelerator (CESA) ....................................................17410.1 Cryptographic Engine Features ....................................................................................................................175

10.2 Security Accelerator Features.......................................................................................................................175

10.3 Cryptographic Engines Operational Description ...........................................................................................175

10.4 Security Accelerator Operational Description................................................................................................189

10.5 TDMA Controller ...........................................................................................................................................200

11 XOR Engine................................................................................................................................20511.1 Theory of Operation ......................................................................................................................................205

11.2 Descriptor Chain ...........................................................................................................................................209

11.3 Address Decoding.........................................................................................................................................213

11.4 Arbitration......................................................................................................................................................214

11.5 XOR Engine Programming............................................................................................................................215



11.6 Burst Limit .....................................................................................................................................................219

11.7 Errors and Interrupts .....................................................................................................................................220

12 Two-Wire Serial Interface (TWSI) .............................................................................................22112.1 TWSI Bus Operation .....................................................................................................................................221

12.2 TWSI Port Operation.....................................................................................................................................222

12.3 TWSI Serial ROM Initialization......................................................................................................................227

13 UART Interface...........................................................................................................................22813.1 Features ........................................................................................................................................................228

13.2 UART Interface Pin Assignment ...................................................................................................................228

13.3 Operation ......................................................................................................................................................228

13.4 Programmable Baud-Rate Generator ...........................................................................................................229

14 8-bit NAND Flash Interface .......................................................................................................23114.1 NAND Flash Interface Pin Assignment .........................................................................................................231

14.2 NAND Flash Types .......................................................................................................................................231

14.3 Software Responsibilities ..............................................................................................................................231

14.4 NAND Flash Interface Read Timing Parameters ..........................................................................................232

14.5 NAND Flash Interface Write Timing Parameters...........................................................................................234

14.6 Boot from NAND Flash..................................................................................................................................234

15 Serial Peripheral Interface (SPI) ...............................................................................................23615.1 SPI Interface Signals.....................................................................................................................................236

15.2 Indirect Mode ................................................................................................................................................237

15.3 Direct Mode...................................................................................................................................................237

16 Audio (I2S / S/PDIF) Interface (88F6180, 88F6192, and 88F6281 Only) .................................24016.1 Recording Data Flow.....................................................................................................................................242

16.2 Playback Flow ...............................................................................................................................................246

16.3 Error Handling ...............................................................................................................................................251

16.4 Audio Unit Memory Structure ........................................................................................................................252

17 Secure Digital Input/Output (SDIO) Interface..........................................................................25617.1 Features ........................................................................................................................................................257

17.2 SDMem, MMC, and SDIO Arbitration Scheme .............................................................................................257

17.3 Difference Between SD Cards and MMC Cards ...........................................................................................259

17.4 SDIO / SDMem / MMC Host Controller Initialization .....................................................................................259

17.5 SDIO / SDMem / MMC Command Execution................................................................................................259

17.6 SDIO / SDMem / MMC Interrupts..................................................................................................................261

18 Transport Stream (TS) Interface (88F6192 and 88F6281 Only) .............................................26218.1 TS Port Architecture......................................................................................................................................263

18.2 TS Interface...................................................................................................................................................263

Table of Contents


18.3 Clocks ...........................................................................................................................................................266

18.4 TS Input Data Flow .......................................................................................................................................267

18.5 TS Output Data Flow.....................................................................................................................................267

18.6 DMA Engine ..................................................................................................................................................267

18.7 TS Timestamp Mechanism............................................................................................................................272

18.8 TS Packet Aggregation .................................................................................................................................273

18.9 TS Port Interrupts..........................................................................................................................................275

18.10 Loopback Mode.............................................................................................................................................276

19 General-Purpose I/O (GPIO) Port Interface .............................................................................27719.1 GPIO Control Registers ................................................................................................................................277

19.2 GPIO Blink Enable Register ..........................................................................................................................277

19.3 GPIO Interrupts .............................................................................................................................................277

20 Real-Time Clock (RTC) Unit ......................................................................................................27820.1 Features ........................................................................................................................................................278

20.2 Functionality ..................................................................................................................................................278

21 Interrupt Controller....................................................................................................................28021.1 Local Interrupt Cause and Mask Registers ...................................................................................................280

21.2 Main Interrupt Cause and Mask Registers ....................................................................................................281

21.3 Doorbell Interrupt ..........................................................................................................................................281

21.4 Device Interrupt Controller Scheme ..............................................................................................................282

22 Timers and Counters.................................................................................................................28322.1 32-bit General-Purpose Timers.....................................................................................................................283

22.2 Watchdog Timer............................................................................................................................................283

22.3 RTC Alarm ....................................................................................................................................................283

22.4 SYSRSTn Duration Counter .........................................................................................................................285

23 eFuse ..........................................................................................................................................28623.1 Typical eFuse Applications ...........................................................................................................................286

23.2 eFuse Power Supply .....................................................................................................................................286

23.3 eFuse Program and Lock..............................................................................................................................286

23.4 eFuse Read...................................................................................................................................................287

24 System Considerations.............................................................................................................28824.1 Big and Little Endian Support........................................................................................................................288

24.2 BootROM Firmware ......................................................................................................................................290

24.3 Power Management ......................................................................................................................................303

24.4 Error Handling Functional Description...........................................................................................................309



25 Internal Architecture .................................................................................................................31225.1 Mbus-L—Sheeva™ CPU Core Local Bus.....................................................................................................312

25.2 Mbus—Device Internal Bus...........................................................................................................................315

25.3 Mbus-L to Mbus Bridge .................................................................................................................................317

25.4 Transaction Ordering ....................................................................................................................................317

A 88F6180/88F619x/88F6281 Register Set ..................................................................................352A.1 Registers Overview .......................................................................................................................................352

A.2 Internal Registers Address Map....................................................................................................................354

B Revision History ........................................................................................................................786

List of Tables


List of TablesPreface.......................................................................................................................................................17

1 Overview............................................................................................................................................20Table 1: 88F6180, 88F619x, and 88F6281 Device Differences and Similarities ............................................31

2 Address Map .....................................................................................................................................34Table 2: Units IDs and Attributes—CPU.........................................................................................................35Table 3: Unit IDs and Attributes—PCI Express ..............................................................................................38Table 4: Device Default Address Map ............................................................................................................41

3 Sheeva™ CPU Core..........................................................................................................................43

4 DDR SDRAM Controller....................................................................................................................44Table 5: DDR2 DRAM Addressing .................................................................................................................45Table 6: Address Multiplex for 16b Interface, AddrSel = 0 .............................................................................46Table 7: Address Multiplex for 16b Interface, AddrSel = 1 .............................................................................46Table 8: SDRAM Timing Parameters .............................................................................................................47Table 9: M_STARTBURST Output Assertion Point Configuration..................................................................53

5 Time Division Multiplexing (TDM) Unit (88F6192 and 88F6281 Only) ..........................................56Table 10: Time Division Multiplexing (TDM) Interface Signals .........................................................................58

6 PCI Express Interface.......................................................................................................................74Table 11: Supported Message Groups—Root Complex Mode ........................................................................79Table 12: Supported Message Groups—Endpoint Mode .................................................................................80Table 13: Physical Layer Error List ...................................................................................................................84Table 14: Data Link Layer Error List .................................................................................................................84Table 15: Transaction Layer Error List .............................................................................................................85

7 Serial-ATA (SATA) II Interface (88F619x and 88F6281 Only) ........................................................89Table 16: Disc Status LED State Settings ........................................................................................................91Table 17: EDMA CRQB Data Structure Map..................................................................................................104Table 18: CRQB DW0—cPRD Descriptor Table Base Low Address .............................................................105Table 19: CRQB DW1—cPRD Descriptor Table Base High Address ............................................................105Table 20: CRQB DW2—Control Flags ...........................................................................................................105Table 21: CRQB DW3—Data Region Byte Count ..........................................................................................106Table 22: CRQB DW4—ATA Command ........................................................................................................106Table 23: CRQB DW5—ATA Command ........................................................................................................106Table 24: CRQB DW6—ATA Command ........................................................................................................107Table 25: CRQB DW7—ATA Command ........................................................................................................107Table 26: ePRD Table Data Structure Map ....................................................................................................108Table 27: ePRD DWORD 0 ............................................................................................................................108Table 28: ePRD DWORD 1 ............................................................................................................................109



Table 29: ePRD DWORD 2 ............................................................................................................................109Table 30: ePRD DWORD 3 ............................................................................................................................109Table 31: EDMA CRPB Data Structure Map ..................................................................................................110Table 32: CRPB ID Register ...........................................................................................................................110Table 33: CRPB Response Flags Register ....................................................................................................110Table 34: CRPB Time Stamp Register ...........................................................................................................111

8 Gigabit Ethernet Controller............................................................................................................113Table 35: Transmit Descriptor Command/Status............................................................................................123Table 36: Transmit Descriptor Byte Count......................................................................................................125Table 37: Transmit Descriptor Buffer Pointer .................................................................................................125Table 38: Transmit Descriptor Next Descriptor Pointer ..................................................................................125Table 39: Receive Descriptor Command/Status.............................................................................................132Table 40: Receive Descriptor Byte Count.......................................................................................................134Table 41: Receive Descriptor Buffer Pointer ..................................................................................................134Table 42: Receive Descriptor Next Descriptor Pointer ...................................................................................134Table 43: Marvell Header Fields.....................................................................................................................137Table 44: DSA Tag Fields (TO_CPU Format) ................................................................................................140Table 45: DSA Tag Fields (FORWARD Format) ............................................................................................141Table 46: Token Rate Configuration Examples ..............................................................................................147Table 47: SMI Bit Stream Format ...................................................................................................................157Table 48: Definitions for MAC MIB Counters ..................................................................................................168

9 Universal Serial Bus (USB 2.0) Interface ......................................................................................173

10 Cryptographic Engines and Security Accelerator (CESA) .........................................................174Table 49: Acronyms, Abbreviations, and Definitions ......................................................................................174Table 50: Security Accelerator Data Structure Dword 0—Configuration ........................................................196Table 51: Security Accelerator Data Structure Dword 1—Encryption Pointers ..............................................197Table 52: Security Accelerator Data Structure Dword 2—Encryption Data Length........................................198Table 53: Security Accelerator Data Structure Dword 3—Encryption Keys Pointer .......................................198Table 54: Security Accelerator Data Structure Dword 4—Encryption Initial Values Pointer...........................198Table 55: Security Accelerator Data Structure Dword 5—MAC Source Pointer.............................................199Table 56: Security Accelerator Data Structure Dword 6—MAC Digest ..........................................................199Table 57: Security Accelerator Data Structure Dword 7—MAC Initial Values Pointers ..................................199Table 58: TDMA Descriptor Definitions ..........................................................................................................201

11 XOR Engine .....................................................................................................................................205Table 59: Descriptor Status Word Definition...................................................................................................211Table 60: Descriptor CRC-32 Result Word Definition.....................................................................................211Table 61: Descriptor Command Word Definition ............................................................................................211Table 62: Descriptor Next Descriptor Address Word......................................................................................212Table 63: Descriptor Byte Count Word ...........................................................................................................212Table 64: Descriptor Destination Address Word.............................................................................................212Table 65: Descriptor Source Address #N Words............................................................................................213Table 66: EOC/EOD interpretation .................................................................................................................220

List of Tables


12 Two-Wire Serial Interface (TWSI) ..................................................................................................221Table 67: TWSI Control Register Bits .............................................................................................................223Table 68: TWSI Status Codes ........................................................................................................................224

13 UART Interface................................................................................................................................228Table 69: Typical Baud Rates where TCLK = 166 MHz .................................................................................230

14 8-bit NAND Flash Interface ............................................................................................................231Table 70: Device Controller Pin Assignments ................................................................................................231

15 Serial Peripheral Interface (SPI) ....................................................................................................236Table 71: SPI Interface Signals ......................................................................................................................236

16 Audio (I2S / S/PDIF) Interface (88F6180, 88F6192, and 88F6281 Only) ......................................240Table 72: Audio Unit Memory Bit Description .................................................................................................255

17 Secure Digital Input/Output (SDIO) Interface ...............................................................................256Table 73: Software Flow .................................................................................................................................260

18 Transport Stream (TS) Interface (88F6192 and 88F6281 Only)...................................................262Table 74: Transport Stream (TS) Interface Signal Assignment ......................................................................264

19 General-Purpose I/O (GPIO) Port Interface ..................................................................................277

20 Real-Time Clock (RTC) Unit ...........................................................................................................278

21 Interrupt Controller.........................................................................................................................280

22 Timers and Counters......................................................................................................................283Table 75: Alarm Interrupt Valid Bit Usage ......................................................................................................284

23 eFuse ...............................................................................................................................................286

24 System Considerations..................................................................................................................288Table 76: MMU Virtual-to-Physical Address Translation Table ......................................................................291Table 77: Main Header Format.......................................................................................................................293Table 78: Header Extension Format...............................................................................................................294Table 79: Types of NAND Flash Read Commands Supported.......................................................................301Table 80: Types of ECC Protocols Supported per Flash Type.......................................................................302Table 81: Bad Block Indicators per NAND Flash Cell Type............................................................................302Table 82: 512 Mb—SDRAM IDD Values ........................................................................................................304Table 83: CPU Address Decoding Error Handling..........................................................................................310Table 84: PCI Express Error Handling............................................................................................................310Table 85: USB Error Handling ........................................................................................................................311

25 Internal Architecture.......................................................................................................................312Table 86: Mbus Units ......................................................................................................................................315



A 88F6180/88F619x/88F6281 Register Set .......................................................................................352Table 87: Register Field Type Codes .............................................................................................................352Table 88: Device Internal Registers Address Map .........................................................................................354Table 89: Register Map Table for the Mbus-L to Mbus Bridge Registers .......................................................355Table 159: Register Map Table for the DDR SDRAM Controller Registers......................................................389Table 194: Register Map Table for the Time Division Multiplexing (TDM) Unit Registers ................................413Table 242: Register Map Table for the PCI Express Interface Registers .........................................................437Table 326: Register Map Table for the Serial-ATA Host Controller (SATAHC) Registers................................491Table 399: Shadow Register Block Registers Map ..........................................................................................549Table 400: Register Map Table for the Gigabit Ethernet Controller Registers..................................................550Table 465: Register Map Table for the PTP Registers .....................................................................................597Table 500: Register Map Table for the USB 2.0 Registers...............................................................................625Table 515: USB Controller Register Map (Offsets: 0x50000–0x502FF)...........................................................632Table 516: Register Map Table for the Cryptographic Engine and Security Accelerator (CESA) Registers ....634Table 581: Register Map Table for the XOR Engine Registers ........................................................................657Table 601: Register Map Table for the TWSI Registers ...................................................................................671Table 610: Register Map Table for the NAND Flash Registers ........................................................................675Table 614: Register Map Table for the UART Registers ..................................................................................678Table 627: Register Map Table for the SPI Registers ......................................................................................685Table 636: Register Map Table for the Audio Interface Registers....................................................................689Table 677: Register Map Table for the SDIO Registers ...................................................................................714Table 729: Register Map Table for the Transport Stream (TS) Registers ........................................................744Table 740: Register Map for TSU Registers.....................................................................................................749Table 766: Register Map Table for the General Purpose Port Registers .........................................................762Table 783: Register Map Table for the RTC Registers.....................................................................................767Table 790: Register Map Table for the Boot ROM Registers ...........................................................................771Table 792: Register Map Table for the MPP Registers ....................................................................................773Table 801: Register Map Table for the eFuse Registers ..................................................................................779Table 808: Register Map Table for the Miscellaneous Registers .....................................................................782

B Revision History .............................................................................................................................786Table 816: Revision History..............................................................................................................................786

List of Figures


List of FiguresPreface.......................................................................................................................................................17

1 Overview........................................................................................................................................... 20Figure 1: 88F6180 Interface Block Diagram ....................................................................................................21Figure 2: 88F6190 Interface Block Diagram ....................................................................................................22Figure 3: 88F6192 Interface Block Diagram ....................................................................................................23Figure 4: 88F6281 Interface Block Diagram ....................................................................................................24

2 Address Map .................................................................................................................................... 34

3 Sheeva™ CPU Core......................................................................................................................... 43

4 DDR SDRAM Controller................................................................................................................... 44Figure 5: DDR2 I/O Buffer ...............................................................................................................................54

5 Time Division Multiplexing (TDM) Unit (88F6192 and 88F6281 Only) ......................................... 56Figure 6: SLIC/Codec Connection Example ....................................................................................................56Figure 7: TDM Unit Block Diagram ..................................................................................................................57Figure 8: TDM Operation Time Slot 0 ..............................................................................................................59Figure 9: TDM Wideband Mode Operation ......................................................................................................60Figure 10: TDM Transmit Path...........................................................................................................................63Figure 11: TDM Receive Path............................................................................................................................68Figure 12: Codec Register Write Operation.......................................................................................................72Figure 13: Codec Register Read Operation.......................................................................................................73

6 PCI Express Interface...................................................................................................................... 74Figure 14: High-level Block Diagram .................................................................................................................75Figure 15: Shallow Internal Loopback................................................................................................................87Figure 16: Deep Internal Loopback....................................................................................................................87

7 Serial-ATA (SATA) II Interface (88F619x and 88F6281 Only) ....................................................... 89Figure 17: SATAHC Block Diagram...................................................................................................................90Figure 18: Disc Status LED Indication Diagram.................................................................................................91Figure 19: Command Request Queue—32 Entries ...........................................................................................92Figure 20: Command Response Queue—32 Entries ........................................................................................93Figure 21: EDMA Interrupt Hierarchy...............................................................................................................100

8 Gigabit Ethernet Controller........................................................................................................... 113Figure 22: Ethernet Descriptors and Buffers....................................................................................................116Figure 23: Ethernet Packet Transmission Example.........................................................................................119Figure 24: Transmit Descriptor Description ....................................................................................................122Figure 25: Receive Descriptor Description ......................................................................................................131Figure 26: Rx Packet Marvell Header Example ...............................................................................................137



Figure 27: Tx Packet with Marvell Header Example ........................................................................................138Figure 28: Rx Packet with DSA Tag Example (4 bytes tag, TO_CPU Format)................................................139Figure 29: Tx Packet with a DSA Tag Example (FROM_CPU format, use_vidx = 0) .....................................143Figure 30: MII Connection................................................................................................................................150Figure 31: GMII Connection.............................................................................................................................152Figure 32: RGMII Pin Interconnection Between MAC and PHY ......................................................................152Figure 33: PTP Common Header Format ........................................................................................................160Figure 34: PTP over UDP Frame.....................................................................................................................161Figure 35: PTP 2.1 Pipe Block Diagram ..........................................................................................................162Figure 36: Time Stamping Pipeline Stages......................................................................................................164Figure 37: Ethernet Frame Classification.........................................................................................................170Figure 38: Bad Frame Procedure ....................................................................................................................171

9 Universal Serial Bus (USB 2.0) Interface ..................................................................................... 173

10 Cryptographic Engines and Security Accelerator (CESA) ........................................................ 174Figure 39: Authentication of a Data Chunk ......................................................................................................178Figure 40: Typical Authentication Flow for a Packet ........................................................................................179Figure 41: DES Engine Pipeline ......................................................................................................................181Figure 42: Typical DES/3DES Encryption Flow for Packet ..............................................................................184Figure 43: Typical AES Encryption Flow for a Data Block ...............................................................................187Figure 44: Typical AES Decryption Flow for a Data Block...............................................................................189Figure 45: Security Accelerator Main Decision Flow .......................................................................................190Figure 46: Security Acceleration Flow for Packet Processing..........................................................................191Figure 47: Security Acceleration Flow for Packet Processing—Enhanced Mode............................................192Figure 48: TDMA Descriptors Structure for Security Accelerator Packet Processing

in Enhanced Mode.........................................................................................................................193Figure 49: TDMA Descriptors ..........................................................................................................................201Figure 50: Chained Mode TDMA .....................................................................................................................203

11 XOR Engine .................................................................................................................................... 205Figure 51: Schematic Diagram of the Two XOR Engines................................................................................205Figure 52: XOR Operation with Multiple Incoming Data Blocks.......................................................................207Figure 53: XOR iSCSI CRC32C Operation......................................................................................................208Figure 54: XOR Descriptor Format ..................................................................................................................210Figure 55: Programmable Channel Pizza Arbiter ............................................................................................214Figure 56: Software and Hardware Synchronization .......................................................................................218

12 Two-Wire Serial Interface (TWSI) ................................................................................................. 221Figure 57: TWSI Examples .............................................................................................................................222

List of Figures


13 UART Interface............................................................................................................................... 228Figure 58: Example UART Data Frame (Two Stop Bits)..................................................................................229Figure 59: Example UART Data Frame (One Stop Bit) ...................................................................................229

14 8-bit NAND Flash Interface ........................................................................................................... 231Figure 60: 8-bit NAND Flash Read Parameters Example................................................................................233Figure 61: 8-bit NAND Flash Write Parameters Example................................................................................234

15 Serial Peripheral Interface (SPI) ................................................................................................... 236

16 Audio (I2S / S/PDIF) Interface (88F6180, 88F6192, and 88F6281 Only) ..................................... 240Figure 62: Audio Unit Block Diagram...............................................................................................................240Figure 63: Recording Flow ..............................................................................................................................244Figure 64: Playback Flow.................................................................................................................................249Figure 65: Memory Structure for Transmit and Receive ..................................................................................254

17 Secure Digital Input/Output (SDIO) Interface .............................................................................. 256Figure 66: SD_MMC Host Controller Hardware Block Diagram ......................................................................256Figure 67: Host Initialization Flow ...................................................................................................................258

18 Transport Stream (TS) Interface (88F6192 and 88F6281 Only).................................................. 262Figure 68: TSU Block Diagram ........................................................................................................................262Figure 69: TS Interface Block Diagram............................................................................................................263Figure 70: TS Parallel Protocol (Example).......................................................................................................266Figure 71: TS Continuous Serial Data Protocol (Example) .............................................................................266Figure 72: TS Input Descriptor Queue .............................................................................................................269Figure 73: TS Output Descriptor Structure—No Packet Aggregation..............................................................270Figure 74: TS Output Descriptor Queue—No Packet Aggregation..................................................................271Figure 75: Impact of Timestamp on the Average TS Data Output Data Rate..................................................273Figure 76: Aggregated TS Input Mode.............................................................................................................274Figure 77: Aggregated TS Output Mode..........................................................................................................275Figure 78: TS Loopback Modes.......................................................................................................................276

19 General-Purpose I/O (GPIO) Port Interface ................................................................................. 277

20 Real-Time Clock (RTC) Unit .......................................................................................................... 278

21 Interrupt Controller........................................................................................................................ 280Figure 79: Device Interrupt Controller Scheme................................................................................................282



22 Timers and Counters..................................................................................................................... 283

23 eFuse .............................................................................................................................................. 286

24 System Considerations................................................................................................................. 288Figure 80: Binary Image Layout in the Boot Device.........................................................................................292Figure 81: Initialization and Boot Method Selection Flow ................................................................................296Figure 82: Header Decoding, DDR Initialization, and Image Execution Flowchart ..........................................299Figure 83: Endpoint Power Supply Control ......................................................................................................307

25 Internal Architecture...................................................................................................................... 312Figure 84: 88F6180 and 88F619x Bus Interface Unit Mbus-L Block Diagram.................................................312Figure 85: 88F6281 Bus Interface Unit Mbus-L Block Diagram.......................................................................313Figure 86: CPU to DDR Mbus-L Timing Diagrams—CPU2MbusLTickDrv=0,

CPU2MbusLTickSample=0.............................................................................................................314Figure 87: CPU to DDR Mbus-L Timing Diagrams—CPU2MbusLTickDrv=2,

CPU2MbusLTickSample=2 ............................................................................................................314Figure 88: Masters Request Default Arbitration Cycle.....................................................................................316

A 88F6180/88F619x/88F6281 Register Set .......................................................................................352Figure 89: PTP Configuration Data Structure Registers ..................................................................................600Figure 90: PTP Global Status Data Structure Registers..................................................................................602Figure 91: PTP Port Configuration Data Structure Registers ..........................................................................603Figure 92: PTP Port Status Data Structure Registers......................................................................................607Figure 93: TAI Global Configuration Data Structure ........................................................................................615Figure 94: PTP Time Application Interface Global Status Data Structure........................................................620

B Revision History .............................................................................................................................786

PrefaceAbout this Document


Preface

About this DocumentThis document provides the functional specifications for the 88F6180, 88F6190, 88F6192, and 88F6281 integrated controllers. This datasheet also provides detailed definitions for the registers implemented in these devices.

This document is intended to be the basic source of information for designers of new systems.

All feature descriptions and specifications described in this document refer to all the devices, unless otherwise specified. In this document, the 88F6180, 88F6190, 88F6192, and 88F6281 are often referred to as “the device/s”. In addition, the 88F6190 and 88F6192 are often referred to as the 88F619x.

Relevant Devices 88F618088F619088F619288F6281

Related DocumentationThe following documents contain additional information related to the 88F6180,88F619x, and 88F6281:

88F6180 Hardware Specifications, Doc No. MV-S104988-U088F6190 and 88F6192 Hardware Specifications, Doc No. MV-S104987-U088F6281 Hardware Specifications, Doc No. MV-S104859-U088F6180, 88F6190, 88F6192, and 88F6281 Design Guide, Doc No. MV-S301398-001

Sheeva™ 88SV131 ARM v5TE Processor Core with MMU and L1/L2 Cache Datasheet, Doc No. MV-S104950-U0 Unified Layer 2 (L2) Cache for Sheeva™ CPU Cores Addendum, Doc No. MV-S104858-U0AN-179 TWSI Software Guidelines for Discovery™, Horizon™, and Feroceon® Devices, Doc No. MV-S300754-001

AN-183, 88F5181 and 88F5281 Big Endian and Little Endian Support, Doc No. MV-S300767-001

AN-249: Configuring the Marvell® SATA PHY to Transmit Predefined Test Patterns, Doc No. MV-S301342-001

AN-260 System Power-Saving Methods for 88F6180, 88F6190, 88F6192, and 88F6281, Doc No. MV-S301454-001

TB-227: Differences Between the 88F6192, and 88F6281 Stepping Z0 and A0, Doc No. MV-S105223-001

ARM Architecture Reference Manual, Second EditionPCI Express Base Specification, Revision 1.1Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips

1. This document is a Marvell proprietary, confidential document, requiring an NDA and can be downloaded from the Marvell Extranet.



Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95, November 2000, Intel CorporationARC USB-HS OTG High-Speed USB On-The-Go Controller Core V 4.0.1 Reference.Federal Information Processing Standards (FIPS) 46-2 (Data Encryption Standard)FIPS 81 (DES Modes of Operation)FIPS 180-1 (Secure Hash Standard)FIPS draft - Advanced Encryption Standard (Rijndeal)RFC 1321 (The MD5 Message-Digest Algorithm)RFC 1851 – The ESP Triple DES TransformRFC 2104 (HMAC: Keyed-Hashing for Message Authentication).RFC 2405 – The ESP DES-CBC Cipher Algorithm With Explicit IVIEEE standard, 802.3-2000 Clause 14ANSI standard X3.263-1995

See the Marvell Extranet website for the latest product documentation.

PrefaceDocument Conventions


Document ConventionsThe following conventions are used in this document: ns

Signal Range A signal name followed by a range enclosed in brackets represents a range of logically related signals. The first number in the range indicates the most significant bit (MSb) and the last number indicates the least significant bit (LSb).Example: DB_Addr[12:0]

Active Low Signals # An n letter at the end of a signal name indicates that the signal’s active state occurs when voltage is low.Example: INTn

State Names State names are indicated in italic font.Example: linkfail

Register Naming Conventions

Register field names are indicated by angle brackets. Example: Register field bits are enclosed in brackets. Example: Field [1:0] Register addresses are represented in hexadecimal format.Example: 0x0Reserved: The contents of the register are reserved for internal use only or for future use.A lowercase in angle brackets in a register indicates that there are multiple registers with this name.Example: Multicast Configuration Register

Reset Values Reset values have the following meanings:0 = Bit clear1 = Bit set

Abbreviations Gb: gigabitGB: gigabyteKb: kilobitKB: kilobyteMb: megabitMB: megabyte

Numbering Conventions Unless otherwise indicated, all numbers in this document are decimal (base 10).An 0x prefix indicates a hexadecimal number.An 0b prefix indicates a binary number.



1 OverviewThe Marvell® 88F6180, 88F6190, 88F6192, and 88F6281 devices are high-performance, highly integrated controllers. The devices are based on the ARMv5TE-compliant, high-speed Marvell® Sheeva™ 88SV131 CPU core with 256 KB L2 cache.

This section provides a brief description of the interfaces in each of these devices.

Note

The functions, interfaces, and registers/register bits described in this document do not necessarily apply to all of the devices.

OverviewBlock Diagrams


1.1 Block DiagramsFigure 1 is a block diagram of the 88F6180 interfaces.

Figure 1: 88F6180 Interface Block Diagram

Mbus-L Local bus

64-bit

up to 200 MHz

Mbus-L to Mbus Bridge

Mbus 64-bits

@ 166 MHz

Dual Channel 16-bit up to 400 MHz data rate DDR2 SDRAM Controller

Sheeva™88SV131 CPU core

600 MHz or

800 MHz

16 KB L1

D-cache

16 KB L1

I-cache

256 KB L2

cache

up to 400 MHz

SDIO interface

S/PDIF / I2S Audio

interface

PCI Express with integrated

SERDESx1 port

TWSI, SPI, UART x2, MPP,

NAND Flash, BootROM

XOR / DMAx4 channels

Security engine

USB 2.0 with integrated

PHY

Gigabit Ethernet x1 port



Figure 2 is a block diagram of the 88F6190 interfaces.


Mbus-LLocal bus

64-bit

up to 200 MHz


Mbus 64-bits

@166 MHz

Dual Channel 16-bit up to 400 MHz data rateDDR2 SDRAM Controller

Sheeva™

88SV131 CPU core

600 MHz

16 KB L1

D-cache

16 KB L1

I-cache

256 KB L2

cache

up to 300 MHz


SERDESx1 port

SDIO interface


NAND flash, BootROM


Security engine


PHY

Gb Ethernet x1 port,

Fast Ethernet x1 port

SATA II with integrated

PHYsx1 port

OverviewBlock Diagrams




Mbus-LLocal bus

64-bit

up to 200 MHz


Mbus 64-bits

@166 MHz

Dual Channel 16-bit up to 400 MHz data rateDDR2 SDRAM Controller

Sheeva™

88SV131 CPU core

800 MHz

16 KB L1

D-cache

16 KB L1

I-cache

256 KB L2

cache

up to 400 MHz

TDMSLIC/Codec

interface


SERDESx1 port

TS/Video interface

SDIO interface

S/PDIF / I2S Audio

interface


NAND flash, BootROM


Security engine


PHY

Gigabit Ethernet x2 ports


PHYsx2 ports





Mbus-LLocal bus

64-bit

up to 400 MHz


Mbus 64-bits

@200 MHz

Dual Channel 16-bit up to 800 MHz data rate DDR2 SDRAM Controller

Sheeva™

88SV131 CPU core

1.0 GHz, 1.2 GHz,

or 1.5 GHz

16 KB L1

D-cache

16 KB L1

I-cache

256 KB L2

cache

up to 500 MHz

TDMSLIC/Codec

interface


SERDESx1 port

TS/Video interface

SDIO interface

S/PDIF / I2S Audio

interface


NAND flash, BootROM


Security engine


PHY

Gigabit Ethernet x2 ports


PHYsx2 ports

OverviewOverview of Functions and Interfaces


1.2 Overview of Functions and InterfacesThe following is a list of the device functions and interfaces:

Sheeva™ 88SV131 CPU Core

The device integrates the Sheeva 88SV131 CPU core. This core is compliant with ARMv5TE architecture, as published in the ARM Architecture Reference Manual, Second Edition. The Sheeva 88SV131 CPU core provides integrated 16/16 KB, four-way, set-associative I/D L1 caches and a unified 256 KB four-way, set-associative L2 cache.

88F6180: Running at 600 MHz or 800 MHz88F6190: Running at 600 MHz88F6192: Running at 800 MHz88F6281: Running at 1.0 GHz, 1.2 GHz, or 1.5 GHz

The Sheeva 88SV131 CPU core also provides: 32-bit and 16-bit RISC architectureAn MMU to support virtual memory features 64-bit internal data busBranch Prediction UnitJTAG/ARM ICE support Big and Little Endian modes support

See Section 3, Sheeva™ CPU Core, on page 43.

DDR SDRAM Interface The device integrates a 16-bit DDR2 SDRAM interface.88F6180 and 88F619x

Up to 200 MHz clock frequency with an 400 MHz data rateSupports two DRAM chip selectsSupports all DDR2 devices with densities up to 1 GbSupports up to 16 open pages (page per bank)Up to 512 MB total address space

88F6281Up to 400 MHz clock frequency with an 800 MHz data rateSupports four DRAM chip selectsSupports all DDR2 devices with densities up to 2 Gb Supports up to 32 open pages (page per bank)Up to 2 GB total address space

All of the devices Provide the following DDR SDRAM interface features:

Support for on board DDR designs (no DIMM support)DDR SDRAM with a clock ratio of 1:N and 2:N between the DDR SDRAM and the CPU core, respectivelySSTL 1.8V I/Os Auto calibration of I/Os output impedanceSupport for 2T mode to enable high-frequency operation with a heavy load configurationSupports DRAM bank interleavingSupports up to a 128-byte burst per single memory access

See Section 4, DDR SDRAM Controller, on page 44.



Time Division Multiplexing (SLIC/SLAC/Codec) Interface

The 88F6192 and 88F6281 contain a Time Division Multiplexing (SLIC/SLAC/Codec) interface.The TDM is a generic interface to the standard SLIC/SLAC/codec devices. It provides:

Compatibility with standard PCM highway formatsTDM protocol support for two channels, up to 128 time slotsSPI interface for codec register read/write accessTwo integrated DMA engines to transfer voice data to/from memory buffer

See Section 5, Time Division Multiplexing (TDM) Unit (88F6192 and 88F6281 Only), on page 56.

PCI Express Interface The device integrates a PCI Express Base 1.1 compatible interface containing a single PCI Express lane (x1) host port with an integrated low power SERDES, based on Marvell® SERDES technology. This interface can serve as a Root Complex or an Endpoint port with:

x1 lane width2.5 Gbps data rateLane polarity reversal supportMaximum payload size of 128 bytesSingle Virtual Channel (VC-0)Replay buffer supportExtended PCI Express configuration spaceAdvanced Error Reporting (AER) supportPower management: L0s and software L1 supportInterrupt emulation message supportError message support

As a master, the PCI Express interface contains:Single outstanding read transactionMaximum read request of up to 128 bytesMaximum write request of up to 128 bytesUp to four outstanding read transactions in Endpoint mode

As a target, the PCI Express interface contains:Supports up to eight read request transactionsMaximum read request size of 4 KBMaximum write request of 128 bytesSupports PCI Express access to all of the device’s internal registers

See Section 6, PCI Express Interface, on page 74.

OverviewOverview of Functions and Interfaces


Serial ATA II (SATA II) Interface

The 88F6192 and 88F6281 contain two and the 88F6190 contains one SATA II compliant 3 Gbps (Gen2i) SATA PHY(s). The SATA interface supports:

SATA II Native command queuing, up to 128 outstanding commands per portFirst party DMA (FPDMA) full supportBackwards compatibility to SATA I 1.5-Gbps speed and devicesFully supports the SATA II Phase 1.0 specification, and the following advanced SATA II Phase 2.0 specification features:• 3 Gbps (Gen2i) SATA II speed• SATA II Port Multiplier performs FIS-Based Switching as defined in SATA working

group Port Multipl

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