88118505-120-2013-000-STM32-EM35x-NCP-Host-Module

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EM35x NCP Host (STM32)

Module Technical

SpecificationWhen combined with an EM35x NCP Breakout Board, the Ember

STM32 NCP Host

Module offers a complete ZigBee wireless solution for development and deployment of

a low-data-rate, low-power ZigBee application. The STM32 microprocessor is part of the

two-layer (FR4-based) host module that connects to the EM35x NCP Breakout Board

through the board-to-board connectors.

This document provides the technical specification for the STM32 EM35x NCP Host

Module. It describes the board-level interfaces as well as the key performance

parameters. In addition, it provides the necessary information for developer to validate

their application designs using the STM32 EM35x NCP Host Module.

Contents

STM32 Host Module Features ....................................................................... 2Components .......................................................................................... 3

STM32 Microcontroller ............................................................................ 4EM35x NCP Breakout Board interface connector (J1-J2).................................... 4JTAG Programming and Debug Connector (J3) ............................................... 7Unused STM32 GPIO (TP0-TP10) ................................................................ 7

STM32 NCP Host Module Schematic ............................................................... 7

8 October 2010

120-2013-000A

Ember Corporation

47 Farnsworth Street

Boston, MA 02210

+1 (617) 951-0200

www.ember.com
http://www.ember.com/http://www.ember.com/http://www.ember.com/


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Page 2

EM35x NCP Host (STM32) Module Technical Specification 120-2013-000A

The STM32 EM35x NCP Host Module offers:

Cortex-M3 based microprocessor (STM32F103RET6)

512Kbytes FLASH, 64Kbytes RAM

Host UART1 for use with STM32 serial bootloader and application serial UART

Host UART2 for EZSP UART interface to EM35x NCP

Host SPI1 for EZSP SPI interface to EM35x NCP

16 additional Host GPIO routed to mating connector for application use on EM35x

NCP Breakout Board

All unused Host GPIO routed to test points

14-pin, 0.1 pitch, dual-row, JTAG programming and debug header (could be used

with a JTAG programmer such as SEGGERs JLINK.)

16-pin, 0.1 pitch, single-row along with a 20-pin 0.1 pitch, single-row, board-to-

board connector for mating to the EM35x NCP Breakout Board

Spare Host IO routed to test points for application use

Table 1 lists the DC electrical characteristics of the STM32 EM35x NCP Host Module.

Table 1. DC electrical characteristics

Parameter Min. Typ. Max. Unit

VDD supply 2.0 3.6 V

Current Draw (active) 45 mA

Operating temperature 0 + 55 C

For more information on the STM32F103RET6, refer to the STM32 datasheet

(http://www.st.com/stonline/products/literature/ds/14611.pdf).

STM32 Host ModuleFeatures
http://www.st.com/stonline/products/literature/ds/14611.pdfhttp://www.st.com/stonline/products/literature/ds/14611.pdfhttp://www.st.com/stonline/products/literature/ds/14611.pdfhttp://www.st.com/stonline/products/literature/ds/14611.pdf


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Page 3


Figure 1 illustrates the components on layer 1 (top side), while Figure 2 illustrates the

components on layer 2 (bottom side).

Figure 1. Assembly print for layer 1

Spare GPIO

Routed to Test

Points (TP0-TP10)

STM32F103RET6Micro (U1)

14-pin 0.1" JTAGConnector (J3)

Pair of 0.1" Interface

Connectors (J1-J2)

Figure 2. Assembly print for layer 2

Serial Number

Label

Pair of 0.1" Interface

Connectors (J1-J2)

Components


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Page 4


STM32 Microcontroller

The STM32 NCP Host Module contains the STM32F103RET6 microcontroller from ST

Microelectronics. This microcontroller is based on the Cortex-M3 core from ARM. This

version of the STM32 contains 512Kbytes of FLASH and 64Kbytes of SRAM. 2 USARTs are

exposed to the board-to-board connector for STM32 system bootloading (STM32

USART1) and EZSP UART (STM32 USART2) to the EM35x NCP. 2 SPI ports are also routed

to the board-to-board connector for EZSP SPI interface to the EM35x NCP (STM32 SPI1)

and external DataFlash (STM32 SPI2). Various other IOs are exposed to the board-to-

board connector, including timers and interrupts. For more information on the

STM32F103RET6, refer to the STM32 datasheet


EM35x NCP Breakout Board interface connector (J1-J2)

Two single-row, 0.1 pitch, connectors make up the STM32 NCP host module interface

to the EM35x NCP Breakout Board. The board-to-board connector scheme allows access

to 16 Host GPIO for application purposes, along with 2 USART ports and 1 SPI port

dedicated to EZSP and debug use. These 16 Host GPIO are listed in Table 2; the

connector is illustrated in Figure 3. Interface connector dimensions are shown in Figure

4.

Table 2. Host GPIO Functions

Host GPIO STM32 I/O Primary GPIO Function

HGPIO0 PB8 Application LED (LED0)

HGPIO1 PB9 Application LED (LED1)

HGPIO2 PB10 Application Button (BUTTON0)

HGPIO3 PB11 Application Button (BUTTON1)

HGPIO4 PC6 Application Speaker (PIEZO)

HGPIO5 PC7 Spare GPIO


HGPIO7 PA8 Temperature Sensor Enable (TEMP_ENABLE)

HGPIO8 PC0 Temperature Sensor ADC (TEMP_SENSOR)


HGPIO10 PB6 Spare GPIO

HGPIO11 PB7 DataFlash Shutdown (DF_nSD)

HGPIO12 PB12 DataFlash SPI Chip Select (DF_nCS)

HGPIO13 PB13 DataFlash SPI Clock (DF_SCK)

HGPIO14 PB15 DataFlash SPI Serial In (DF_SI)

HGPIO15 PB14 DataFlash SPI Serial Out (DF_SO)


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Page 5


Figure 3. Board-to-board connector for the STM32 NCP host module

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

1

2

3

4

5

6

7

8

9

10

11

12

13

14

EZSP_nRTS2

EZSP_nCTS2

EZSP_RXD2

EZSP_TXD2

TEMP_ENABLE

PC8

PC7

PIEZO

DF_SO

DF_SI

DF_SCK

DF_nCS

BUTTON1

BUTTON0

BTL

NCP_nRESET

nWAKE

N/C

VDD_3V

PB6

PB7

LED0

LED1

nRESET

TEMP_SENSOR

PC1

SER_nCTS1

SER_nRTS1

SER_TXD1

SER_RXD1

nSS

SCK

MISO

J2

J1

15 MOSI

16 nHOST_INT

36GND

Figure 4. Board-to-board connector dimensions for the STM32 NCP host module

Table 3 describes the pinout and signal names at J1 and J2.


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Page 6


For more information on the functions of the STM32 GPIO, refer to the STM32 datasheet


Table 3. Pinout and signal names of the interface connectors

Pin # Signal name Direction2 Connector Description

1 PB6 I/O J1 Spare STM32 GPIO (HGPIO10)

2 PB7 I/O J1 Spare STM32 GPIO (HGPIO11)

3 LED0 I/O J1 STM32 PB8 (HGPIO0)

4 LED1 I/O J1 STM32 PB9 (HGPIO1)

5 nRESET I/O J1 STM32 Reset

6 TEMP_SENSOR I/O J1 STM32 PC0 (HGPIO8)

7 PC1 I/O J1 Spare STM32 GPIO (HGPIO9)

8 SER_nCTS1 I/O J1 STM32 PA11

9 SER_nRTS1 I/O J1 STM32 PA12

10 SER_TXD1 I/O J1 STM32 PA9

11 SER_RXD1 I/O J1 STM32 PA10

12 nSS I/O J1 STM32 PA4

13 SCK I/O J1 STM32 PA5

14 MISO I/O J1 STM32 PA6

15 MOSI I/O J1 STM32 PA7

16 nHOST_INT I/O J1 STM32 PC4

17 VDD_3V Power J2 3V Source Pin

18 EZSP_nRTS2 I/O J2 STM32 PA1

19 EZSP_nCTS2 I/O J2 STM32 PA0-WKUP

20 EZSP_RXD2 I/O J2 STM32 PA3

21 EZSP_TXD2 I/O J2 STM32 PA2

22 TEMP_ENABLE I/O J2 STM32 PA8 (HGPIO7)



25 PIEZO I/O J2 STM32 PC6 (HGPIO4)

26 DF_SO I/O J2 STM32 PB14 (HGPIO15)

27 DF_SI I/O J2 STM32 PB15 (HGPIO14)

28 DF_SCK I/O J2 STM32 PB13 (HGPIO13)

29 DF_nCS I/O J2 STM32 PB12 (HGPIO12)

30 BUTTON1 I/O J2 STM32 PB11 (HGPIO3)

31 BUTTON0 I/O J2 STM32 PB10 (HGPIO2)

32 BTL I J2 Inverted and routed to STM32

BOOT0

33 NCP_nRESET I/O J2 STM32 PB0

34 nWAKE I/O J2 STM32PC5

35 NC N/A J2 Not connected

36 GND Power J2 Ground connection

2with respect to the STM32


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Page 7


JTAG Programming and Debug Connector (J3)

The STM32 NCP Host module includes a 14-pin 0.1 dual-row header for JTAG

programming and debug access. Figure 5 shows the pinout of this header. Note that the

EM35x NCP Kit does not ship with a programmer that interfaces to this header. Third-

party programmers may connect to this header. For example, the J-Link ARM 14-pin

Adapter from SEGGER (http://www.segger.com/cms/jlink-

adapters.html#14pinAdapter) may be connected directly to this header.

Figure 5. JTAG Connector Pinout (J3)

1

GND

2

J3

GND

GND

GND

GND

nRESET

GND

13

14

VDD_

3V

nJTRST

JTDI

JTMS-SWDIO

JCLK-SWCLK

JTDO

VDD_

3V

Unused STM32 GPIO (TP0-TP10)

The STM32 NCP Host module routes all GPIO not routed to the mating connectors to

test points TP0 through TP10. This allows the developer to utilize all STM32 GPIO for

their application, if required. Table 4 lists these test points.

Table 4. STM32 Unused GPIO Routed to Test Points

Test Point Signal name Test Point Signal name

TP0 VBAT TP6 PC9

TP1 PB1 TP7 PC10

TP2 PB2_BOOT1 TP8 PC11

TP3 PB5 TP9 PC12

TP4 PC2 TP10 PD2

TP5 PC3

The STM32 NCP Host Module schematic is included at the end of this document.

If you have questions or require assistance with the procedures described in this

document, contact Ember Customer Support. The Ember Customer Support portal

provides a wide array of hardware and software documentation such as FAQs,

reference designs, user guides, application notes, and the latest software available to

download. To obtain support on all Ember products and to gain access to the Ember

Customer Support portal, visithttp://www.ember.com/support_index.html.

STM32 NCP HostModule Schematic

After Reading ThisDocument
http://www.segger.com/cms/jlink-adapters.html#14pinAdapterhttp://www.segger.com/cms/jlink-adapters.html#14pinAdapterhttp://www.segger.com/cms/jlink-adapters.html#14pinAdapterhttp://www.segger.com/cms/jlink-adapters.html#14pinAdapterhttp://www.ember.com/support_index.htmlhttp://www.ember.com/support_index.htmlhttp://www.ember.com/support_index.htmlhttp://www.ember.com/support_index.htmlhttp://www.segger.com/cms/jlink-adapters.html#14pinAdapterhttp://www.segger.com/cms/jlink-adapters.html#14pinAdapter


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COVER SHEETEM35X NCP HOST MODULE (STM32

SCH0820

1

2 134

4 3 2 1

TITLE

SIZE B

DWG

SHEET:DATE:

Ember Corporation, 47 Farnsworth Street, Boston, MA 02210

The information in this document is subject to change without notice. The statements, configur ations, technical data and recommenddocument are believed to be accurate and reliable, but are presented without express or implied warranty. The info rmation in this dothe proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicaused without the express permission of Ember Corporation

TEL: 617-951-0200, FAX: 617-951-0999

PAGE

www.ember.com

19-09-2010_21:15

Sheet Details

EM35x NCP Host Module (STM32)

2 STM32 MICRO, INTERFACE CONNECTORS

1 COVER SHEET

3 REVISION NOTES


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STM32 MICRO, INTERFACE CONNECEM35X NCP HOST MODULE (STM3

SCH0820

2

2 134

4 3 2 1

TITLE

SIZE B

DWG

SHEET:DATE:

Ember Corporation, 47 Farnsworth Street, Boston, MA 02210

The information in this document is subject to change without notice. The statements, configur ations, technical data and recommenddocument are believed to be accurate and reliable, but are presented without express or implied warranty. The info rmation in this dothe proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicaused without the express permission of Ember Corporation

TEL: 617-951-0200, FAX: 617-951-0999

PAGE

www.ember.com

19-09-2010_21:15

PCB1

710-0820-000

U1

64636261605958575655545352515049

48474645444342414039383736353433

32313029282726252423222120191817

16151413121110987654321

VBAT

PC13_TAMP

ER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_O

UT

NRST

PC0

PC1

PC2

PC3

VSSA

VDDA

PA0-WKUP

PA1

PA2

PA3

VSS_4VDD_4

PA4PA5PA6PA7PC4PC5PB0PB1PB2

PB10PB11

VSS_1VDD_1

PB12

PB13

PB14

PB15

PC6

PC7

PC8

PC9

PA8

PA9

PA10

PA11

PA12

PA13

VSS_2

VDD_2

PA14PA15PC10PC11PC12PD2PB3PB4PB5PB6PB7BOOT0PB8PB9VSS_3

VDD_3

DatasheetSTM32F103RET6

10NF

C1

1UF

C2

FID1

100NF

C3

DatasheetABS07-32.768KHZ-T

Y1

21

18PF

C4

18PF

C5

18PF

C6

18PF

C7

VDD_3V

VDD_3V

TP0

VDD_3VVDD_3V

100NF

C8

100NF

C9

100NF

C10

U2

5

43

2

1NCNC

A

GND Y

VCC

Datasheet74AUP1G04GW,125

VDD_3V

4.7UF

C11

Datasheet8MHZ

Y2

21

VDD_3V VDD_3V

J3

1413121110987654321

S-HEADER-14

Datasheet

VDD_3V

130-0820-000SN1

R210K

R40_Ohm

VDD_3V

HOST_INTERFACEX1

3635 NC

343332313029282726252423222120191817

16151413121110987654321

DatasheetHEADER-16J1

VDD_3V

TP1

TP4

TP5

TP2

TP6

R3DNI

TP7

TP8

TP9

TP10

TP3

DD_3V

R5DNI

R610K

VDD_3V

HEADER-20Datasheet

J2

VDD_3VR110K

VDD_3V

OSC_OUTOSC_IN

OSC32_OUTOSC32_IN

PC13

nRESET

nRESET

nRESET

TEMP_SENSOR

TEMP_SENSOR

nSS

nSS

SCK

SCK

MISO

MISO

MOSI

MOSI

nHOST_INT

nHOST_INT

nWAKE

nWAKE

JTMS-SWDIO

JTMS-SWDIO

JCLK-SWCLK

JCLK-SWCLK

JTDI

JTDI

JTDO

JTDO

nJTRST

nJTRST

BOOT0

BOOT0

VBAT

VBAT

PC2

PC2

PC3

PC3

PC9

PC9

PC10

PC10

PC11

PC11

PC12

PC12

PD2

PD2

PB5

PB5

PB2_BOOT1

PB2_BOOT1

PC1

PC1

NCP_nRESET

NCP_nRESET

PB6

PB6

PB7

PB7

LED0

LED0

LED1

LED1

BUTTON0BUTTON0BUTTON1BUTTON1

DF_nCS

DF_nCS

DF_SCK

DF_SCK

DF_SO

DF_SO

PIEZO

PIEZO

PC8

PC8PC7

PC7

TEMP_ENABLE

TEMP_ENABLE

PB1

PB1

BTL

BTL

EZSP_nCTS2

EZSP_nCTS2

EZSP_nRTS2

EZSP_nRTS2

EZSP_TXD2

EZSP_TXD2

EZSP_RXD2

EZSP_RXD2

SER_TXD1

SER_TXD1

SER_RXD1

SER_RXD1

SER_nCTS1

SER_nCTS1

SER_nRTS1

SER_nRTS1

DF_SI

DF_SI

EM35x EZSP Breakout Board Interface Connectors

U1p12,13 (VDDA) U1p18,19 (VDD_4) U1p63,64 (VDD_3)U1p31,32 (VDD_1) U1p47,48 (VDD_2)

Power Supply Decoupling

JTAG Connector

NOTE: Place as close to noted U1 pins as possible

J1p35 - NC, can be used later as needed

Test Points - Unused IO

Bootload Signal Inverter

Fiducials

PCB Informatio

STM32 EZSP Host Micro
http://www.st.com/stonline/products/literature/ds/14611.pdfhttp://www.st.com/stonline/products/literature/ds/14611.pdfhttp://www.abracon.com/Resonators/ABS07.pdfhttp://www.abracon.com/Resonators/ABS07.pdfhttp://www.nxp.com/documents/data_sheet/74AUP1G04.pdfhttp://www.abracon.com/Resonators/abls.pdfhttp://www.abracon.com/Resonators/abls.pdfhttp://documents.tycoelectronics.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=5103309&DocType=CD&DocLang=ENhttp://www.molex.com/pdm_docs/sd/022284163_sd.pdfhttp://www.molex.com/pdm_docs/sd/022284203_sd.pdfhttp://www.molex.com/pdm_docs/sd/022284203_sd.pdfhttp://www.molex.com/pdm_docs/sd/022284163_sd.pdfhttp://documents.tycoelectronics.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=5103309&DocType=CD&DocLang=ENhttp://www.abracon.com/Resonators/abls.pdfhttp://www.nxp.com/documents/data_sheet/74AUP1G04.pdfhttp://www.abracon.com/Resonators/ABS07.pdfhttp://www.st.com/stonline/products/literature/ds/14611.pdf


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EM35X NCP HOST MODULE (STM32)

3 3

SCH0820 A

REVISION NOTES

12

2 1

Ember Corporation, 47 Farnsworth Street, Boston, MA 02210TEL: 617-951-0200, FAX: 617-951-0999www.ember.com

REV

TITLE

SIZE A

DWG

SHEET: ofDATE:

The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in thisdocument are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document isthe proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwiseused without the express permission of Ember Corporation

PAGE

19-09-2010_21:15

2) Renamed UART1 nets to SER_TXD1, etc.

7) Removed InSight Port connector footprint J4.

*Released: 2010-08-03

8) Replaced J3 with 14-pin 0.1" JTAG connector.

*Changes from P0 to P1:

-- Version P1 --

1) Swapped UART1 with UART2 on X1 (J1, J2). 1) Added Inverter IC U2.*Changes from P0 to P1:*Released: 2010-08-03-- Version P1 --

2) Changed R2 from 0 ohm to 10k ohm.3) Changed R6 from DNI to 10k ohm.4) Changed U1.27 net connection from BTL to PB1.5) Change TP1 to TP0 for VBAT net.6) Added TP1 for PB1 net.7) Added inverter IC U2 for inverting BTL net for connection to BOOT0 net.

2) Re-routed UART1 and UART2 nets.3) Added missing test points from P0 version.

*Changes from P1 to A0:

-- Version A0 --*Released: 2010-09-20

3) Renamed UART2 nets to EZSP_TXD1, etc.4) Added 10k pull-up R7 to U2 BTL net.

1) Removed DS1 and R1 for lowest current capability.

-- Version A0 --

*Changes from P1 to A0:

*Released: 2010-09-20

5) Updated title from EZSP to NCP.6) Corrected DF_SO/_SI error at X1 J2p26/27 (reversed).

*Production version release

*Production version release

SCHEMATIC NOTES:

-- Version P0 --*Released: 2010-06-11*Initial version released, Version P0 (initial draft)

1) All schematic notes reflected in layout.

*Released: 2010-06-11

PCB LAYOUT NOTES:

*Initial version released, Version P0 (initial draft)

-- Version P0 --


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Copyright 2010 Ember Corporation

All rights reserved.

The information in this document is subject to change without notice. The statements,

configurations, technical data, and recommendations in this document are believed to be

accurate and reliable but are presented without express or implied warranty. Users must

take full responsibility for their applications of any products specified in this document. The

information in this document is the property of Ember Corporation.

Title, ownership, and all rights in copyrights, patents, trademarks, trade secrets and other

intellectual property rights in the Ember Proprietary Products and any copy, portion, or

modification thereof, shall not transfer to Purchaser or its customers and shall remain in

Ember and its licensors.

No source code rights are granted to Purchaser or its customers with respect to all Ember

Application Software. Purchaser agrees not to copy, modify, alter, translate, decompile,

disassemble, or reverse engineer the Ember Hardware (including without limitation any

embedded software) or attempt to disable any security devices or codes incorporated in theEmber Hardware. Purchaser shall not alter, remove, or obscure any printed or displayed legal

notices contained on or in the Ember Hardware.

Ember is a registered trademark, and the Ember logo and InSight are trademarks of Ember

Corporation.

All other trademarks are the property of their respective holders.

Ember Corporation

47 Farnsworth Street

Boston, MA 02210

+1 (617) 951-0200

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88118505-120-2013-000-STM32-EM35x-NCP-Host-Module

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