INTEL CORPORATION 1997 April 1997 Order Number: 290562-001

Supported Kits for both Pentium and Pentium II Microprocessors

82430TX ISA Kit 82440LX ISA/DP Kit

Multifunction PCI to ISA Bridge Supports PCI at 30 MHz and 33 MHz Supports PCI Rev 2.1 Specification Supports Full ISA or Extended I/O

(EIO) Bus Supports Full Positive Decode or

Subtractive Decode of PCI Supports ISA and EIO at 1/4 of PCI

Frequency Supports both Mobile and Desktop

Deep Green Environments 3.3V Operation with 5V Tolerant

Buffers Ultra-low Power for Mobile

Environments Support Power-On Suspend, Suspend to

RAM, Suspend to Disk, and Soft-OFF System States

All Registers Readable and Restorable for Proper Resume from 0.V Suspend

Power Management Logic Global and Local Device

Management Suspend and Resume Logic Supports Thermal Alarm Support for External Microcontroller Full Support for Advanced

Configuration and Power Interface (ACPI) Revision 1.0 Specification and OS Directed Power Management

Integrated IDE Controller Independent Timing of up to

4 Drives PIO Mode 4 and Bus Master IDE

Transfers up to 14 Mbytes/sec Supports Ultra DMA/33

Synchronous DMA Mode Transfers up to 33 Mbytes/sec

Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers

Supports Glue-less Swap-Bay Option with Full Electrical Isolation

Enhanced DMA Controller Two 82C37 DMA Controllers Supports PCI DMA with 3 PC/PCI

Channels and Distributed DMA Protocols (Simultaneously)

Fast Type-F DMA for Reduced PCI Bus Usage

Interrupt Controller Based on Two 82C59 15 Interrupt Support Independently Programmable for

Edge/Level Sensitivity Supports Optional I/O APIC Serial Interrupt Input

Timers Based on 82C54 System Timer, Refresh Request,

Speaker Tone Output USB

Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec

Supports Legacy Keyboard and Mouse Software with USB-based Keyboard and Mouse

Supports UHCI Design Guide SMBus

Host Interface Allows CPU to Communicate Via SMBus

Slave Interface Allows External SMBus Master to Control Resume Events

Real-Time Clock 256-byte Battery-Back CMOS SRAM Includes Date Alarm Two 8-byte Lockout Ranges

Microsoft Win95* Compliant 324 mBGA Package

82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)

82371AB (PIIX4)

2

The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions found in ISA-based PC systemstwo 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real Time Clock. In addition to compatible transfers, each DMA channel supports Type F transfers. PIIX4 also contains full support for both PC/PCI and Distributed DMA protocols implementing PCI-based DMA. The Interrupt Controller has Edge or Level sensitive programmable inputs and fully supports the use of an external I/O Advanced Programmable Interrupt Controller (APIC) and Serial Interrupts. Chip select decoding is provided for BIOS, Real Time Clock, Keyboard Controller, second external microcontroller, as well as two Programmable Chip Selects. PIIX4 provides full Plug and Play compatibility. PIIX4 can be configured as a Subtractive Decode bridge or as a Positive Decode bridge. This allows the use of a subtractive decode PCI-to-PCI bridge such as the Intel 380FB PCIset which implements a PCI/ISA docking station environment.

PIIX4 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD ROMs. Up to four IDE devices can be supported in Bus Master mode. PIIX4 contains support for Ultra DMA/33 synchronous DMA compatible devices.

PIIX4 contains a Universal Serial Bus (USB) Host Controller that is Universal Host Controller Interface (UHCI) compatible. The Host Controllers root hub has two programmable USB ports.

PIIX4 supports Enhanced Power Management, including full Clock Control, Device Management for up to 14 devices, and Suspend and Resume logic with Power On Suspend, Suspend to RAM or Suspend to Disk. It fully supports Operating System Directed Power Management via the Advanced Configuration and Power Interface (ACPI) specification. PIIX4 integrates both a System Management Bus (SMBus) Host and Slave interface for serial communication with other devices.

Information in this document is provided in conjunction with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The 82371AB PIIX4 may contain design defects or errors known as errata. Current characterized errata are available on request. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not infringe such rights. I2C is a two-wire communication bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementation of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Third-party brands and names are the property of their respective owners.

82371AB (PIIX4)

3

PCICLKAD[31:0]

C/BE[3:0]#FRAME#

TRDY#IRDY#

STOP#DEVSEL#

SERR#PAR

IDSELPHOLD#PHLKA#

CLKRUN#

RCIN#PWROK

CPURSTRSTDRV

INITPCIRST#

IRQ0//GPO14IRQ8#/GPI6

IRQ12/MINTRNMI

IRQ[15,14,11:9,7:3,1]SERIRQ/GPI7

PRIQ[A:C]PIRQD

IRQ9OUT#/GPO29

SMI#STPCLK#EXTSMI#

SLP#SUSCLK

BATLOW#/GPI9CPU_STP#/GPO17PCI_STP#/GPO18

THRM#/GPI8LID//GPI10RI#/GPI12RSMRST#PWRBTN#

SUSA#SUSB#/GPO15SUSC#/GPO16

SUS_STAT1#/GPO20SUS_STAT2#/GPO21

ZZ/GPO19PCIREQ[D:A]#

SPKROSC

DREQ[7:5,3:0]DACK[7:5,3:0]#

TCREFRESH#

REQ[A:C]#/GPI[2:4]GNT[A:C]#/GPO[9:11]

CLK48USBPOUSBP1OC[1:0]#

CONFIG[2:1]TEST#

PCI BusInterface

ISA BusInterface

SystemReset

Interrupt

PrimaryIDE

Interface

SecondaryIDE

Interface

SystemPowerMgmt.

X-BusSupport

Logic

Timers/Counters

DMA

I/O APICSupportLogic

UniversalSerialBus

RTC

SMBUS

GeneralPurposeInputsand

Outputs

Test

SD[15:0]IOCS16#MEMCS16#MEMR#MEMW#AENIOCHRDYIOCHK#/GPI0SYSCLKBALEIOR#IOW#SMEMR#SMEMW#ZEROWS#SA[19:0]LA[23:17]/GPO[7:1]SBHE#

PDCS1#PDCS3#PDA[2:0]PDD[15:0]PDDACK#PDDREQPDIOIR#PDIOW#PIORDY

SDCS1#SDCS3#SDA[2:0]SDD[15:0]SDDACK#SDDREQSDIOR#SDIOW#SIORDY

PCS[1:0]#XDIR#/GPO22XOE#/GPO23RTCALE/GPO25FERR#IGNNE#BIOSCS#RTCCS#/GPO24KBCCS#/GPO26A20M#A20GATEMCCS#

APICCS#/GPO13APICACK#/GPO12APCIREQ#/GPI5

RTCX[2:1]

SMBALERT#SMBCLKSMBDATA

GPI[21:13,1]GPI[12:2,0] (Multiplexed)GPO[30,28:27,8,0]GPO[29,26:9,7:1] (Multiplexed)

Pix4_blk

Simplified Block Diagram

82371AB (PIIX4)

4

CONTENTS

PAGE

1.0. ARCHITECTURAL OVERVIEW................................................................................................................ 12

2.0. SIGNAL DESCRIPTION ........................................................................................................................... 15 2.1. PIIX4 Signals ......................................................................................................................................... 16

2.1.1. PCI Bus Interface............................................................................................................................ 16 2.1.2. ISA Bus Interface............................................................................................................................ 18 2.1.3. X-Bus Interface ............................................................................................................................... 21 2.1.4. DMA Signals ................................................................................................................................... 23 2.1.5. Interrupt Controller/APIC Signals.................................................................................................... 24 2.1.6. CPU Interface Signals .................................................................................................................... 26 2.1.7. Clocking Signals ............................................................................................................................. 28 2.1.8. IDE Signals ..................................................................................................................................... 28 2.1.9. Universal Serial Bus Signals........................................................................................................... 33 2.1.10. Power Management Signals..............................