80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353...
Transcript of 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353...
![Page 1: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/1.jpg)
80856 PIN DIAGRAM
![Page 2: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/2.jpg)
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as ADDRESS BUS ALONG WITH A15-A8
1 1 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select
signal
![Page 3: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/3.jpg)
0100 1111 (4F H)
ON
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as ADDRESS BUS ALONG WITH A15-A8
1 1 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 4: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/4.jpg)
0100 1111 (4F H)
1 1 1ALE RD WR
![Page 5: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/5.jpg)
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as ADDRESS BUS ALONG WITH A15-A8
1 1 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 6: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/6.jpg)
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
µP Puts 2005 H address on Address BUS (A15-A0)
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 7: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/7.jpg)
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0 µP Puts 2005 H address on Address BUS (A15-A0)
ENABLE of 2005 H Memory location (Register) gets 1
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 8: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/8.jpg)
0100 1111 (4F H) 1 1 1ALE RD WR
![Page 9: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/9.jpg)
0100 1111 (4F H) 1 1 1ALE RD WR
![Page 10: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/10.jpg)
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as ADDRESS BUS ALONG WITH A15-A8
1 1 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 11: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/11.jpg)
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as DATA BUS to read content of 2005 H
location
0 0 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 12: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/12.jpg)
0
0100 1111 (4F H)
0 0 1ALE RD WR
![Page 13: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/13.jpg)
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as DATA BUS to read content of 2005 H
location
0 0 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 14: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/14.jpg)
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-1 (FIRST CLOCK CYCLE)
1, 1, 1ALE RD WR Microprocessor Control Unit
Generates
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 15: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/15.jpg)
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-1 (FIRST CLOCK CYCLE)
1, 1, 1ALE RD WR Microprocessor Places 2005 H Address on Address bus (A15 – A0)
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 16: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/16.jpg)
1, 1, 1ALE RD WR
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-1 (FIRST CLOCK CYCLE)
![Page 17: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/17.jpg)
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-2 (SECOND CLOCK CYCLE)
Microprocessor Control Unit generates: 0, 0, 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 18: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/18.jpg)
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-2 (SECOND CLOCK CYCLE)
Microprocessor Control Unit generates: 0, 0, 1ALE RD WR
![Page 19: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/19.jpg)
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-3 (THIRD CLOCK CYCLE)
Opcode 4F H is placed on data lines
0, 0, 1ALE RD WR
74LS353
OCTAL
LATCH
![Page 20: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/20.jpg)
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-3 (THIRD CLOCK CYCLE)
Opcode 4F H is placed on data lines
![Page 21: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/21.jpg)
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-4 (FOURTH CLOCK CYCLE)
Opcode 4F H goes to INSTRUCTION DECODER
And get Executed 0, 1, 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
![Page 22: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/22.jpg)
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-4 (FOURTH CLOCK CYCLE)
Opcode 4F H goes to INSTRUCTION DECODER
And get Executed 0, 1, 1ALE RD WR
![Page 23: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/23.jpg)
/
34
IO M
PIN
![Page 24: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/24.jpg)
0 & 1
29 &33
S S
PIN
![Page 25: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/25.jpg)
8085 REMAINING PINS
![Page 26: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/26.jpg)
![Page 27: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/27.jpg)
![Page 28: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/28.jpg)
![Page 29: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/29.jpg)
![Page 30: 80856 PIN DIAGRAM - Wikimedia CommonsOpcode 4F H is placed on data lines ALE RD WR 0, 0, 1 74LS353 OCTAL LATCH . MICROPROCESSOR COMMUNICATION & BUS TIMING STEP-3 (THIRD CLOCK CYCLE)](https://reader030.fdocuments.in/reader030/viewer/2022040912/5e867108a681bf0ada6c6bc6/html5/thumbnails/30.jpg)