Intel 8085

Signals and I/O Pins

The 8085 is an 8-bit general purpose microprocessor that can address 64K Byte of memory.

It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz.◦ The pins on the chip can be grouped into 6 groups:

Address Bus. Data Bus. Control and Status Signals. Power supply and frequency. Externally Initiated Signals. Serial I/O ports.

The address bus has 8 signal lines A8 – A15 which are unidirectional.

The other 8 address bits are multiplexed (time shared) with the 8 data bits.◦ So, the bits AD0 – AD7 are bi-directional and serve as A0

– A7 and D0 – D7 at the same time. During the execution of the instruction, these lines

carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits.

◦ In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes.

There are 4 main control and status signals. These are: ALE: Address Latch Enable. This signal is a pulse that

become 1 when the AD0 – AD7 lines have an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the address bits from the AD lines.

RD: Read. Active low. WR: Write. Active low. IO/M: This signal specifies whether the operation is a

memory operation (IO/M=0) or an I/O operation (IO/M=1).

S1 and S0 : Status signals to specify the kind of operation being performed .Usually un-used in small systems.

There are 3 important pins in the frequency control group.◦ X0 and X1 are the inputs from the crystal or clock

generating circuit. The frequency is internally divided by 2.

So, to run the microprocessor at 3 MHz, a clock running at 6 MHz should be connected to the X0 and X1 pins.

◦ CLK (OUT): An output clock pin to drive the clock of the rest of the system.

We will discuss the rest of the control signals as we get to them.

In addition to the arithmetic & logic circuits, the ALU includes an accumulator, which is a part of every arithmetic & logic operation.

Also, the ALU includes a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer.

Registers•General Purpose Registers

• B, C, D, E, H& L(8 bit registers)• Can be used singly• Or can be used as 16 bit register pairsBC, DE, HL• H & L can be used as a data pointer (holds memory

address)

• Special Purpose Registers• Accumulator(8 bit register)• Store 8 bit data• Store the result of an operation• Store 8 bit data during I/O transfer

Programming Model

8 bit register –shows the status of the microprocessor before/after an operation

–S (sign flag), Z (zero flag), AC (auxiliary carry flag), P (parity flag) & CY (carry flag)

Flag Register

◦ There is also a flag register whose bits are affected by the arithmetic & logic operations. S-sign flag

The sign flag is set if bit D7 of the accumulator is set after an arithmetic or logic operation.

Z-zero flag Set if the result of the ALU operation is 0. Otherwise is

reset. This flag is affected by operations on the accumulator as well as other registers. (DCR B).

AC-Auxiliary Carry This flag is set when a carry is generated from bit D3 and

passed to D4 . This flag is used only internally for BCD operations.

P-Parity flag After an ALU operation, if the result has an even # of 1s,

the p-flag is set. Otherwise it is cleared. So, the flag can be used to indicate even parity.

CY-carry flag This flag is set when a carry is generated from bit D7 after

an unsigned operation.

Now, Let us see how the different units and bus systems stay connected:

A15-A8

LatchAD7-AD0

D7- D0

A7- A0

8085

ALE

IO/MRDWR

1K ByteMemory

Chip

WRRD

CS

A9- A0

A15- A10Chip Selection

Circuit

The 8085 executes several types of instructions with each requiring a different number of operations of different types. However, the operations can be grouped into a small set.

The three main types are: Memory Read and Write. I/O Read and Write. Request Acknowledge.

These can be further divided into various smaller operations (machine cycles).

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The first step of executing any instruction is the Opcode fetch cycle.◦ In this cycle, the microprocessor brings in the

instruction’s Opcode from memory. To differentiate this machine cycle from the very similar

“memory read” cycle, the control & status signals are set as follows: IO/M=0, s0 and s1 are both 1.

◦ This machine cycle has four T-states. The 8085 uses the first 3 T-states to fetch the opcode. T4 is used to decode and execute it.

◦ It is also possible for an instruction to have 6 T-states in an opcode fetch machine cycle.

The memory read machine cycle is exactly the same as the opcode fetch except:◦ It only has 3 T-states◦ The s0 signal is set to 0 instead.

◦ To understand the memory read machine cycle, let’s study the execution of the following instruction:

MVI A, 32◦ In memory, this instruction looks like:

The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A), the second byte is the data to be loaded.

◦ The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it will need at least two machine cycles.

The first machine cycle is the opcode fetch discussed earlier.

The second machine cycle is the Memory Read Cycle.

2000H

2001H

3E

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Machine cycles and instruction length, do not have a direct relationship. ◦ To illustrate, let’s look at the machine cycles needed

to execute the following instruction. STA 2065H This is a 3-byte instruction requiring 4 machine

cycles and 13 T-states. The machine code will be stored

in memory as shown to the right This instruction requires the following 4 machine

cycles: A ‘Opcode fetch’ to fetch the opcode (32H) from location 2010H,

‘decode’ it and determine that 2 more bytes are needed (4 T-states).

A ‘Memory read’ to read the low order byte of the address (65H) (3 T-states).

A ‘Memory read’ to read the high order byte of the address (20H) (3 T-states).

A ‘memory write’ to write the contents of the accumulator into the memory location.

2010H

2011H

2012H

32H

65H

20H

In a memory write operation:◦ The 8085 places the address (2065H) on the

address bus◦ Identifies the operation as a ‘memory write’

(IO/M=0, s1=0, s0=1).◦ Places the contents of the accumulator on the

data bus and asserts the signal WR.◦ During the last T-state, the contents of the data

bus are saved into the memory location.

There needs to be a lot of interaction between the microprocessor and the memory for the exchange of information during program execution.◦ Memory has its requirements on control signals

and their timing.◦ The microprocessor has its requirements as

well.

The interfacing operation is simply the matching of these requirements.

The way of interfacing the above two chips to the microprocessor is the same. ◦ However, the ROM does not have a WR signal.

AddressLines

DateLines

CS

RDOutput Buffer

ROM

AddressLines

Data Lines

CS

RDOutput Buffer

RAMWRInput Buffer

Data Lines

◦ Accessing memory can be summarized into the following three steps:

Select the chip. Identify the memory register. Enable the appropriate buffer.

◦ Translating this to microprocessor domain: The microprocessor places a 16-bit address on the

address bus. Part of the address bus will select the chip and the

other part will go through the address decoder to select the register.

The signals IO/M and RD combined indicate that a memory read operation is in progress. The MEMR signal can be used to enable the RD line on the memory chip.

The result of ‘address decoding’ is the identification of a register for a given address.◦ A large part of the address bus is usually

connected directly to the address inputs of the memory chip.

◦ This portion is decoded internally within the chip.

◦ What concerns us is the other part that must be decoded externally to select the chip.

◦ This can be done either using logic gates or a decoder.

A15-A8

LatchAD7-AD0

D7- D0

A7- A0

8085

ALE

IO/MRDWR

1K ByteMemory

Chip

WRRD

CS

A9- A0

A15- A10Chip Selection

Circuit

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Figure 3: Moving data form memory to MPU using instruction MOV C, A (code machine 4FH = 0100 1111)

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The Fetch Execute Sequence :1. The μp placed a 16 bit memory address from PC

(program counter) to address bus. – Figure 4: at T1

– The high order address, 20H, is placed at A15 – A8. – the low order address, 05H, is placed at AD7 - AD0 and

ALE is active high. – Synchronously the IO/M is in active low condition to

show it is a memory operation.2. At T2 the active low control signal, RD, is activated

so as to activate read operation; it is to indicate that the MPU is in fetch mode operation.

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Figure 4: 8085 timing diagram for Opcode fetch cycle for MOV C, A .

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3. T3: The active low RD signal enabled the byte instruction, 4FH, to be placed on AD7 – AD0 and transferred to the MPU. While RD high, the data bus will be in high impedance mode.

4. T4: The machine code, 4FH, will then be decoded in instruction decoder. The content of accumulator (A) will then copied into C register at time state, T4.

To understand how the microprocessor operates and uses these different signals, we should study the process of communication between the microprocessor and memory during a memory read or write operation.

Lets look at timing and the data flow of an instruction fetch operation.

Lets assume that we are trying to fetch the instruction at memory location 2005. That means that the program counter is now set to that value.◦ The following is the sequence of operations:

The program counter places the address value on the address bus and the controller issues a RD signal.

The memory’s address decoder gets the value and determines which memory location is being accessed.

The value in the memory location is placed on the data bus.

The value on the data bus is read into the instruction decoder inside the microprocessor.

After decoding the instruction, the control unit issues the proper control signals to perform the operation.

Now, lets look at the exact timing of this sequence of events as that is extremely important. (figure 3.3)◦ At T1 , the high order 8 address bits (20H) are placed on

the address lines A8 – A15 and the low order bits are placed on AD7–AD0. The ALE signal goes high to indicate that AD0 – AD8 are carrying an address. At exactly the same time, the IO/M signal goes low to indicate a memory operation.

◦ At the beginning of the T2 cycle, the low order 8 address bits are removed from AD7– AD0 and the controller sends the Read (RD) signal to the memory. The signal remains low (active) for two clock periods to allow for slow devices. During T2 , memory places the data from the memory location on the lines AD7– AD0 .

◦ During T3 the RD signal is Disabled (goes high). This turns off the output Tri-state buffers in the memory. That makes the AD7– AD0 lines go to high impedence mode.

◦ From the above description, it becomes obvious that the AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information.

◦ The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most.

◦ To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7– AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.

◦ Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as the bi-directional data lines.

A15-A8

LatchAD7-AD0

D7- D0

A7- A0

8085

ALE

From the above discussion, we can define terms that will become handy later on:◦ T- State: One subdivision of an operation. A T-state

lasts for one clock period. An instruction’s execution length is usually

measured in a number of T-states. (clock cycles). ◦ Machine Cycle: The time required to complete one

operation of accessing memory, I/O, or acknowledging an external request. This cycle may consist of 3 to 6 T-states.

◦ Instruction Cycle: The time required to complete the execution of an instruction. In the 8085, an instruction cycle may consist of 1

to 6 machine cycles.

The 8085 generates a single RD signal. However, the signal needs to be used with both memory and I/O. So, it must be combined with the IO/M signal to generate different control signals for the memory and I/O.◦ Keeping in mind the operation of the IO/M signal we can

use the following circuitry to generate the right set of signals:

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8085 μp has several interrupt signals as shown in the following table.

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An interrupt is a hardware-initiated subroutine CALL. When interrupt pin is activated, an ISR will be called,

interrupting the program that is currently executing.

PinPin Subroutine LocationSubroutine Location

TRAPTRAP 00240024

RST 5.5RST 5.5 002C002C

RST 6.5RST 6.5 00340034

RST 7.5RST 7.5 003C003C

INTRINTR **

Note: * the address of the ISR is determined by the external Note: * the address of the ISR is determined by the external hardware.hardware.

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INTR input is enabled when EI instruction is executed.

The status of the RST 7.5, RST 6.5 and RST 5.5 pins are determined by both EI instruction and the condition of the mask bits in the interrupt mask register.

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When INTR is asserted, 8085 response with INTA pulse.

During INTA pulse, 8085 expect to see an instruction applied to its data bus.

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Following are the two kind of RESET signals:◦ RESET IN: an active low input signal, Program

Counter (PC) will be set to 0 and thus MPU will reset.

◦ RESET OUT: an output reset signal to indicate that the μp was reset (i.e. RESET IN=0). It also used to reset external devices.

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DMA is an IO technique where external IO device requests the use of the MPU buses.

Allows external IO devices to gain high speed access to the memory.◦ Example of IO devices that use DMA: disk memory system.

HOLD and HLDA are used for DMA. If HOLD=1, 8085 will place it address, data and

control pins at their high-impedance. A DMA acknowledgement is signaled by HLDA=1.