8051_bao_memorydecode

8/7/2019 8051_bao_memorydecode

http://slidepdf.com/reader/full/8051baomemorydecode 1/56

University of Technology 1

Microprocessor System Design

BÙI QUC BO

([email protected])




Outline

� Address decoding

� Chip select

� Memory configurations




MEMORY INTERFACE

When Memory is selected?

MEMORY

D7 - D0

A19 - A0

RD

WR

SimplifiedDrawing of

8088 MinimumMode

D7 - D0

A19 - A0

MEMR

MEMW

cs




Minimum Mode

MEMORY

D7 - D0

A19 - A0

RD

WR

SimplifiedDrawing of

8088 MinimumMode

D7 - D0

A19 - A0

MEMR

MEMWCS

220 bytes or 1MB




What are the memory locations of a1MB (220 bytes) Memory?

A19 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

00000 0000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

Example: 34FD0

0011 0100 11111 1101 0000




Interfacing a 1MB Memory to the 8088 Microprocessor

2300000

00001

10000

10001

10002

10003

10004

10005

10006

10007

10008

95

:

:

45

98

27

39

42

88

07

F4

8A

:

:

20020

20021

20022

20023

FFFFD

FFFFE

FFFFF

29

12

7D

13

19

25

36

:

:

:

:

:

:

:

:A19

A0

:

D7

D0

:

RD

WR

A19

A0

:

D7

D0

:

MEMR

MEMW

XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

CS




Instead of Interfacing 1MB, what will happen if you interface a 512KB Memory?




What are the memory locations of a512KB (219 bytes) Memory?

A18 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111




Interfacing a 512KB Memory to the 8088 Microprocessor

A18

A0

:

D7

D0

:

MEMR

MEMW XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

2300000

00001 95

:

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS

A19What do we do with A19?




What if you want to read physical address A0023?

A18

A0

:

D7

D0

:

MEMR

MEMW XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

A000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

2300000

00001 95

:

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS

A19




What if you want to read physicaladdress A0023?

A19 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

A0023 1010 0000 0000 0010 0011

A19 is not connected to the memory soeven if the 8088 microprocessor

outputs a logic ³1´, the memory

cannot ³see´ this.




What if you want to read physicaladdress 20023?

A18 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

20023 0010 0000 0000 0010 0011

For memory it is the same as previousone.




Interfacing two 512KB Memory to the 8088 Microprocessor

A 18

A 0

:

D7

D0

:

MEMR

MEMW

XXXX

BP

ES

DS

SS

CX

BX

A X

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA 1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

A 19

2300000

00001 95

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

A 18

A 0

:

D7

D0

:

RD

WR

CS

9700000

00001 D4

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

A 3

92

45

33

2C

98

12

:

:

:

A 18

A 0

:

D7

D0

:

RD

WR

CS





� Problem: ng bus (bus conflict). Hai RAMs xut d liu cùng lúc khi VXL thc hinlnh c b nh

� Solution: dùng A19 làm b phân x bus (busarbiter), trong trng hp này có th gi làb gii mã a ch (address decoder).

� Khi A19 = 0, b nh thp hn c cho phép,

b nh cao b cm. Tng t khi A19 = 1.





A 18

A 0

:

D7

D0

:

MEMR

MEMW

XXXX

BP

ES

DS

SS

CX

BX

A X

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA 1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

A 19

2300000

00001 95

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

A 18

A 0

:

D7

D0

:

RD

WR

CS

9700000

00001 D4

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

A 3

92

45

33

2C

98

12

:

:

:

A 18

A 0

:

D7

D0

:

RD

WR

CS




What are the memory locations of twoconsecutive 512KB (219 bytes) Memory?

A19 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

80000 1000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111




A18

A0

:

D7

D0

:

MEMR

MEMW

XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

A19

2300000

00001 95

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS

9700000

00001 D4

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

A3

92

45

33

2C

98

12

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS


When the QP outputsan address between

80000 to FFFFF,

this memory is

selected


00000 to 7FFFF,

this memory is

selected





A18

A0

:

D7

D0

:

MEMR

MEMW

XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

A19

2300000

00001 95

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS

9700000

00001 D4

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

A3

92

45

33

2C

98

12

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS





A18

A0

:

D7

D0

:

MEMR

MEMW

XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

A19

2300000

00001 95

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS

9700000

00001 D4

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

A3

92

45

33

2C

98

12

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS

A18

A0

:

D7

D0

:

RD

WR

A19




A18

A0

:

D7

D0

:

MEMR

MEMW

XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

A19

2300000

00001 95

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS

9700000

00001 D4

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

A3

92

45

33

2C

98

12

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS

What if we remove the lower memory?




What if we remove the lower memory?

A18

A0

:

D7

D0

:

MEMR

MEMW

XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

A19

2300000

00001 95

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CSWhen the QP outputsan address between

80000 to FFFFF,

this memory is

selected


00000 to 7FFFF, no

memory chip is

selected

!




Full and Partial Decoding

� Full Decoding± When all of the ³useful´ address lines are connected the

memory/device to perform selection

� Partial Decoding± When some of the ³useful´ address lines are connected

the memory/device to perform selection

± Using this type of decoding results into roll-over addresses




Full Decoding

A18

A0

:

D7

D0

:

MEMR

MEMW

XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

A19

2300000

00001 95

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS




Full Decoding

A19 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

80000 1000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

A19 should be a logic ³1´ for thememory chip to be enabled




Full Decoding

A19 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

Therefore if the microprocessoroutputs an address between 00000 to

7FFFF, whoseA19 is a logic ³0´, the

memory chip will not be selected




Partial Decoding

A18

A0

:

D7

D0

:

MEMR

MEMW XXXX

BP

ES

DS

SS

CX

BX

AX

XXXX

XXXX

XXXX

2000

0000

0023

3F1C

FCA1

SP

DX

XXXX

CS

SI

XXXX

XXXXIP

XXXXDI

2300000

00001 95

:

:

20020

20021

20022

20023

7FFFD

7FFFE

7FFFF

29

12

7D

13

19

25

36

:

:

:

:

:

:

A18

A0

:

D7

D0

:

RD

WR

CS

A19




Partial Decoding

A19 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

80000 1000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

The value of A19 is INSIGNIFICANT to the

memory chip, thereforeA19 has no bearing

whether the memory chip will be enabled or not




Partial Decoding

A19 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

00000 0000 0000 0000 0000 0000

7FFFF 0111 1111 1111 1111 1111

80000 1000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

ACTUAL ADDRESS




Interfacing two 512K Memory Chips tothe 8088 Microprocessor

8088Minim m

Mo e

A18

A0

:

D7

D0

:

MEMR

MEMW

A19

512KB

#2

A18

A0

:

D7

D0

:

RD

WR

CS

512KB#1

A18

A0

:

D7

D0

:

RD

WR

CS




Interfacing one 512K Memory Chips tothe 8088 Microprocessor

8088Minim m

Mo e

A18

A0

:

D7

D0

:

MEMR

MEMW

A19

512KB

A18

A0

:

D7

D0

:

RD

WR

CS




Interfacing one 512K Memory Chips tothe 8088 Microprocessor (version 2)

8088Minim m

Mo e

A18

A0

:

D7

D0

:

MEMR

MEMW

A19

512KB

A18

A0

:

D7

D0

:

RD

WR

CS




Interfacing one 512K Memory Chips tothe 8088 Microprocessor (version 3)

8088Minim m

Mo e

A18

A0

:

D7

D0

:

MEMR

MEMW

A19

512KB

A18

A0

:

D7

D0

:

RD

WR

CS




Interfacing four 256K MemoryChips tothe 8088 Microprocessor

8088Minimum

Mode

A 17

A 0

:

D7

D0

:

MEMR

MEMW

A 18

256KB#3

A 17

A 0

:

D7

D0

:

RD

WR

CS

A 19

256KB#2

A 17

A 0

:

D7

D0

:

RD

WR

CS

256KB#1

A 17

A 0

:

D7

D0

:

RD

WR

CS

256KB#4

A 17

A 0

:

D7

D0

:

RD

WR

CS





8088Minimum

Mo e

A17

A0

:

D7

D0

:

MEMR

MEMW

A18

256KB

#3

A17

A0

:

D7

D0

:

RD

WR

CS

A19

256KB

#2

A17

A0

:

D7

D0

:

RD

WR

CS

256KB

#1

A17

A0

:

D7

D0

:

RD

WR

CS

256KB

#4

A17

A0

:

D7

D0

:

RD

WR

CS




Memory chip#__ is mapped to:

A19 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

----- ---- ---- ---- ---- ----

----- ---- ---- ---- ---- ----





8088Minimum

Mo e

A17

A0

:

D7

D0

:

MEMR

MEMW

A18

256KB

#3

A17

A0

:

D7

D0

:

RD

WR

CS

A19

256KB

#2

A17

A0

:

D7

D0

:

RD

WR

CS

256KB

#1

A17

A0

:

D7

D0

:

RD

WR

CS

256KB

#4

A17

A0

:

D7

D0

:

RD

WR

CS





8088Minimum

Mo e

A17

A0

:

D7

D0

:

MEMR

MEMW

A18

256KB

#3

A17

A0

:

D7

D0

:

RD

WR

CS

A19

256KB

#2

A17

A0

:

D7

D0

:

RD

WR

CS

256KB

#1

A17

A0

:

D7

D0

:

RD

WR

CS

256KB

#4

A17

A0

:

D7

D0

:

RD

WR

CSI1

I0O3

O2

O1

O0




Interfacing several8K Memory Chips tothe 8088 QP

8088Minimum

Mode

A 12

A 0

:

D7

D0

:

MEMR

MEMW

A 13

A 14

8KB#2

A 12

A 0

:

D7

D0

:

RD

WR

CS

8KB#1

A 12

A 0

:

D7

D0

:

RD

WR

CS

8KB#?

A 12

A 0

:

D7

D0

:

RD

WR

CS

A 15

A 16

A 17

A 18

A 19

::




8088Minimum

Mode

A 12

A 0

:

D7

D0

:

MEMR

MEMW

A 13

A 14

8KB#2

A 12

A 0

:

D7

D0

:

RD

WR

CS

8KB#1

A

12

A 0

:

D7

D0

:

RD

WR

CS

8KB#128

A 12

A 0

:

D7

D0

:

RD

WR

CS

A 15

A 16

A 17

A 18

A 19

::

Interfacing 1288K Memory Chips tothe 8088 QP




8088Minimum

Mode

A 12

A 0

:

D7

D0

:

MEMR

MEMW

A 13

A 14

8KB#2

A 12

A 0

:

D7

D0

:

RD

WR

CS

8KB#1

A 12

A 0

:

D7

D0

:

RD

WR

CS

8KB#128

A 12

A 0

:

D7

D0

:

RD

WR

CS

A 15

A 16

A 17

A 18

A 19

::





Memory chip#__ is mapped to:

A19 to

A0

(HEX)

AAAA

1111

9876

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

----- ---- ---- ---- ---- ----

----- ---- ---- ---- ---- ----




8088Minimum

Mode

A 12

A 0

:

D7

D0

:

MEMR

MEMW

A 13

A 14

8KB#2

A 12

A 0

:

D7

D0

:

RD

WR

CS

8KB#1

A 12

A 0

:

D7

D0

:

RD

WR

CS

8KB#128

A 12

A 0

:

D7

D0

:

RD

WR

CS

A 15

A 16

A 17

A 18

A 19

::





MEMORY DECODER DESIGN

DataMemory 1

DataMemory 2

Peripherals

24

16 Address

Address

Data

Data

DataBus

AddressBus

WR RD Clk IRQ Reset

CPU

Address

Data

Address

cs

cs

cs

cs1

cs2

cs3

Address bus




� Ngõ vào ca address decoder là các ng a ch cn cho gii mã.

� Ngõ r a là các ng Chip select (CS).

� Ti mt thi im có nhiu nht mt ng CStích cc.

� Mc tích cc ph thuc vào tính cht ca b nhhoc ngoi vi cn gii mã.




Design Step

� Xây dng bn b nh (Memory map)

� Thit lp các hàm cho các ng Chip Select

� Xây dng Address Decoder bng các cnghoc bng các vi mch LSI nh 74LS138,PAL, GAL, CPLD«




Example

� Thit k mch gii mã a ch cho 2 RAM, cóng chip select tích cc thp. rngaddress bus ca CPU là 16. a ch bt u là

0000H� RAM1: 2K

� RAM2: 4K




Memory mapA15 to

A0

(HEX)

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

CS

0000H07FFH

00000000

00000111

00001111

00001111

/CS0 = 0

0800H

17FFH

0000

0001

1000

0111

0000

1111

0000

1111 /CS1 = 0




A15 to

A0

(HEX)

AAAA

11115432

AAAA

11981000

AAAA

7654

AAAA

3210

CS

0000H

07FFH

0000

0000

0000

0111

0000

1111

0000

1111

/CS0 = 0

0000H

07FFH

0000 0xxx xxxx xxxx /CS0 = 0




A15 to

A0

(HEX)

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

CS

0800H

17FFH

0000

0001

1000

0111

0000

1111

0000

1111 /CS1 = 0

0800H

17FFH

0000

0000

0001

0001

1000

1111

0000

0111

0000

1111

0000

1111

0000

1111

0000

1111

/CS1 = 0

0800H

17FFH

0000

0001

1xxx

0xxx

xxxx

xxxx

xxxx

xxxx

/CS1 = 0




A15 to

A0

(HEX)

AAAA

1111

5432

AAAA

1198

1000

AAAA

7654

AAAA

3210

CS

0000H

07FFH

0000 0xxx xxxx xxxx /CS0 = 0

0800H

17FFH 0000

0001

1xxx

0xxx

xxxx

xxxx

xxxx

xxxx

/CS1 = 0




15 14 13 12 11/ 0CS A A A A A!

15 14 13 12 11 15 14 13 12 11

/ 1 ( )( )CS A A A A A A A A A A!




THIT K DÙNG 74138

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

C (MSB)

B

A

G

G2A

G2B

0 2 2

1 2 2

2 2 2

3 2 2

4 2 2

5 2 2

6 2 2

6 2 2

Y G G A G B C B A

Y G G A G B C B A

Y G G A G B C B A

Y G G A G B C B A

Y G G A G B C B A

Y G G A G B C B A

Y G G A G B C B A

Y G G A G B C B A

!

!

!

!

!

!

!

!




15 14 13 12 11/ 0CS A A A A A!

15 14 13 12 11 15 14 13 12 11/ 1 ( )( )C S !

15 14 13 12 11 13 12 11( )( )A A A A A A A A!




/ 1 Y1.Y2CS !

/ 0 0C S Y !Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

C (MSB)

B

A

G

G2A

G2B

A15

A14

A13

A12

A11

1

/ 1 Y1.Y2C S !

CS0

CS1

15 14 13 12 11/ 0C S !

15 14 13 12 11 15 14 13 12 11/ 1 ( )( )C S !

15 14 13 12 11 13 12 11( )( )A A A A A A A A!

8051_bao_memorydecode

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Transcript of 8051_bao_memorydecode