8051 REGISTERS · SNSCE/ III-CSE/ 8051-SFR 5. SNSCE/ III-CSE/ 8051-SFR 6. 8051 CPU Registers A...

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8051 REGISTERS By A. Vignesh III-CSE

Transcript of 8051 REGISTERS · SNSCE/ III-CSE/ 8051-SFR 5. SNSCE/ III-CSE/ 8051-SFR 6. 8051 CPU Registers A...

Page 1: 8051 REGISTERS · SNSCE/ III-CSE/ 8051-SFR 5. SNSCE/ III-CSE/ 8051-SFR 6. 8051 CPU Registers A (Accumulator) B PSW (Program Status Word) SP (Stack Pointer) PC (Program Counter) DPTR

8051 REGISTERS

ByA. VigneshIII-CSE

Page 2: 8051 REGISTERS · SNSCE/ III-CSE/ 8051-SFR 5. SNSCE/ III-CSE/ 8051-SFR 6. 8051 CPU Registers A (Accumulator) B PSW (Program Status Word) SP (Stack Pointer) PC (Program Counter) DPTR

On-Chip Memory

Internal RAM

SNSCE/ III-CSE/ 8051-SFR 2

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Registers

R7R6R5R4R3R2R1R0

080706050403020100

100F

1F

1817

Bank 3

Bank 2

Bank 1

Bank 0

Four Register BanksEach bank has R0-R Selectable by psw.2

SNSCE/ III-CSE/ 8051-SFR 3

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Bit Addressable Memory

20h – 2Fh (16

locations X 8-bits =

128 bits)

7F 78

1A

10

0F 08

07 06 05 04 03 02 01 00

2F

2E

2D

2C

2B

2A

29

28

27

26

25

24

23

22

21

20 SNSCE/ III-CSE/ 8051-SFR 4

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Special Function Registers

DATA registers

CONTROL registersTimersSerial portsInterrupt systemAnalog to Digital converterDigital to Analog converterEtc.

Addresses 80h – FFhDirect Addressing used to access SFRs

SNSCE/ III-CSE/ 8051-SFR 5

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SNSCE/ III-CSE/ 8051-SFR 6

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8051 CPU Registers

A (Accumulator)BPSW (Program Status Word)SP (Stack Pointer)PC (Program Counter)DPTR (Data Pointer)

Used in assembler instructions

SNSCE/ III-CSE/ 8051-SFR 7

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A

B

R0

R1

R2

R3

R4

R5

R6

R7

DPH DPL

PC

DPTR

PC

Some 8051 16-bit Register

Some 8-bit

Registers of the

8051

SNSCE/ III-CSE/ 8051-SFR 8

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PROGRAM STATUS WORD

SNSCE/ III-CSE/ 8051-SFR9

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IE: Interrupt Enable Register (bit addressable)

• If the bit is 0, the corresponding interrupt is disabled. Otherwise, the interrupt is enabled.

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IP: Interrupt Priority Register (bit addressable)

• If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1, the interrupt has a higher priority

SNSCE/ III-CSE/ 8051-SFR 11

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TCON: Timer/Counter Control Register (bit addressable)

SNSCE/ III-CSE/ 8051-SFR 12

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TMOD: Timer/Counter Mode Control Register (not bit addressable)

SNSCE/ III-CSE/ 8051-SFR 13

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PCON – Power Control Register

Address: 87H (not bit addressable)

SMOD – Serial mode bit used to determine the baud

rate with Timer 1.

GF1 and GF0 are General purpose flags not

implemented on the standard device

PD is the power down bit. Not implemented on the

standard device

IDL activate the idle mode to save power. Not

implemented on the standard device

SNSCE/ III-CSE/ 8051-SFR 14

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SNSCE/ III-CSE/ 8051-SFR 15

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