8051 Architecture and Programming by S Gupta

8/3/2019 8051 Architecture and Programming by S Gupta

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The 8051 Architecture and Programming

Supratim Gupta


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Hardware Information

Architecture of the rocessor

Architecture of the peripheral interconnection

Software Instructions

Complex Instruction Set Computer (CISC)

135 Instructions for 8051


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8051 Architecture

S ecific Features

1. 8-bit CPU with registers A (accumulator) and B

2. 16-bit program counter (PC) and data pointer (DPTR)

3. 8-bit program status word (PSW)

4. 8-bit stack pointer (SP)

5. Internal ROM or EPROM of 4k (8051)

6. Internal RAM of 128 bytes

4 register banks each containing 8 registers of 8-bit

16-bytes bit addressable registers

80 bytes general purpose data memory


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8051 Architecture

Cntd

pec c ea ures

7. 32 input-output pins arranged as 4 eight-bit ports (P0 P3)

8. Two 16 bit timer/counters : T0 and T1

9. Full duplex serial data receiver/transmitter

10. Control registers : TCON, TMOD, SCON, PCON, IP, and IE

11. 2 external and 3 internal interrupt sources

12. Oscillator and clock circuit


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Cntd

8051 Architecture


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8051 Pro rammin Model

8 B8* 8 A8* 8 89 8 88*8 B8* 0FFF

IP IE TMOD TCONIP

8 B8*

IP

8 8C

TH0

8 8A

TL0

8 8D

TH1

8 8B

TL1

8 98*

SCON

8 99

SBUF

8 87

PCON

8 D0*

PSW

7F

302F

General

Purpose

8 81

SP

16 No Address8 83 8 82

100F

201F1817

Bank 3

Bank 2

.

8 80* 8 90* 8 A0* 8 B0*

PCDPH DPL

Data Pointer

08

07

R4

R7

R6R5

P0 Latch P1 Latch P2 Latch P3 Latch0000

Internal ROM

R3

00 R0

R2

R1Internal RAM * => bit addressable


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Pin Descri tion of 8051

P1.0

P1.1P1.2P1.3

Vcc

P0.0(AD0)P0.1(AD1)P0.2(AD2)

1

234

40

393837

.P1.5P1.6

P1.7RST

.P0.4(AD4)P0.5(AD5)

P0.6(AD6)P0.7 AD7

67

8

3534

3332

(RXD)P3.0(TXD)P3.1(INT0)P3.2(INT1)P3.3

EA/VPPALE/PROGPSENP2.7(A15)

10111213

31302928

8051

.(T1)P3.5

XTAL2(RD)P3.7(WR)P3.6

.P2.5(A13)P2.4(A12)P2.3(A11)P2.2 A10

15161718

26252423

XTAL1GND

P2.1(A9)P2.0(A8)

1920

2221


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A Pin of Port 1

Vcc

Load(L1)

Read latch TB2

D QInternal CPU

bus

P1.X

pinP1.X

Clk QWrite to latch M1

Read pin

TB1

P1.x


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A Pin of Port 0

Read latch

TB2

Internal CPU

bus

P0.X

pinD Q

P0.X

Write to latch M1Clk Q

Read pin

TB1

P0.x


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Cr stal Oscillator Connection

Usin a uartz cr stal oscillator

We can observe the frequency on the XTAL2 pin.

C2

33pF

XTAL2

C1XTAL1

33pF


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nnunc onunc on

1111TxDTxDP3.1P3.1

..

1313INT1INT1P3.3P3.3

..

1616WRWRP3.6P3.6

1515T1T1P3.5P3.5

1717RDRDP3.7P3.7


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RESET Value of Some 8051 Registers

0000PCReset ValueRegister

0000B

0000ACC

0007SP

0000PSW

0000DPTR

..


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TMOD Register

Timer 1Timer 0

ate : en set, t mer on y runs w e , s g .

C/T : Counter/Timer select bit. 0 to set it in timer mode

M1 : Mode bit 1.

M0 : Mode bit 0.


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TCON Re ister

TF1: Timer 1 overflow flag.

TR1: Timer 1 run control bit. : mer over ag.

TR0: Timer 0 run control bit.

IE1: External interru t 1 ed e fla .

IT1: External interrupt 1 type flag.

IE0: External interrupt 0 edge flag.

: x erna n errup ype ag.


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Interrupt Enable Register

: o a ena e sa e.

--- : Undefined.

ET2 :Enable Timer 2 interru t.

ES :Enable Serial port interrupt.

ET1 :Enable Timer 1 interrupt.

: na e x erna n errup . ET0 : Enable Timer 0 interrupt.

EX0 : Enable External 0 interrupt.


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Interrupt Vector Address

0003HIE0AddressType of Interrupt

0013HIE1

000BHTF0

0023HSERIAL

001BHTF1


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Peripheral Architecture

Block Diagram of ADC0808


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Input pins : 8 channels in multiplexed fashion

ress p ns : a ress ts e nes eac nput c anne s

ALE pin : Latches the address bits

SC in : Instructs the ADC to start conversion

Clock pin : Provides clock input to the ADC

EOC pin : Low state on EOC indicates end of conversion


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Block Diagram of DAC0808


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7 2

. . . . . . . . . .2 4 4 2 5 6

M S B L S B

o u t r e f

A A AA

V V


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Programming the 8051

Modules:

Initialization module

ata n t a zat ons or or s

Configuration of Control registers

Address Vectoring

un o u e Main program for performing a specific

task or group of tasks


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State and Explain an algorithm for square


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One Simple Solution:

Ste 1: Make a ort in low

Step 2: Give necessary delay

Step 3: Toggle the port pin

Step 4: Go to Step 2.

Note: Multi-task is not possible with this algorithm


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RTOS in the 8051

Concept:

All the tasks are time-multiplexed

Requirements:

pec e me nterva generat on

Overall tasks divided into two broad categories

Background tasks (Time critical job)

oregroun as s on me cr ca o


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Interrupt

Time

Time

ISR: Interrupt Service Routine


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RTOS in the 8051

Resource for time interval generation:

Design Issues:

-

tim_mod .equal 02h

mov TMOD, #tim mod_

Computation of content to be used for initialization of timer


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Timer Interrupt Generation

12Oscillator

Frequency(fosc)

o

Timer/Countercircuit

Interrupt Interval:

max min1d

dosc

t R Rf

Rmax = FFFF (for 16-bit mode)

= FF (for 8-bit mode)

Rmin = User settable


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RTOS in the 8051

Time Slot Generation using single timer interrupt by multiplying factor with basic

timer interrupt interval

TM0: push ACC

;----------Basic time interval------------------

tm_0: mov A,tickN, , _

;----------Basic time interval*tickN------------

sjmp back

tm_1: dec ACC

mov tick10,A

pop ACC

reti


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RTOS in the 8051

Configuration of ports as input or output

,

mov P1, #00h ; Set port1 as output

ress ector ng

.org 0

a m main

.org 000bh

ajmp TM0 ;jump to timer0 routine


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RTOS in the 8051

ons sts o n n te oop

main: acall level1 ;jump to service routine for foreground task

s m main


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Serial Communication

SM0 : Serial port mode bit 0

SM1 : Serial port mode bit 1

SM2 : Multiprocessor communication enable

REN : Receiver enable. Set this bit to receive characters

th .

RB8 : Receive bit 8. The 9th bit in case of mode 2 and 3

TI : Transmit flag. Set when a byte transmitted completely

RI : Receive flag. Set when a byte transmitted completely


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SM0 SM1 Mode SMOD1 of PCON Baud Rate

0 0 0 X fosc/12

0 1 10 B0 = Set by Timer 1/2

1 B1 = 2*B0 = Set by Timer 1/2

0 f /641 0 2

1 fosc/32

1 1 30 B0 = Set by Timer 1/2

= = et y mer


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B1 2 5 6

3 8 4T H

1 2 5 6o s c r e q

f BT H


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Transmission

clr TI ; Clear the transmit flag

mov SBUF, #D ; Send letter D to transmit

Loop: jnb TI , Loop ; Check for transmission over

Rece tion

Loop: jnb RI , Loop ; Check for reception complete

mov , ; ea rece ve ata


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Serial Communication with PC

Microcontroller TTL/CMOS Logic

PC Serial Port RS232 Logic

Logic

Protocol Low Voltage Level (0) High Voltage Level (1) Note

CMOS 0-Vcc/2 Vcc/2 - Vcc Vcc= Supply

TTL 0-0.8V 2V-0-Vcc Vcc is 4.75 5.25 V

Logic

Protocol

Transmission Reception

Low Voltage

Level 0

High Voltage

Level 1

Low Voltage

Level 0

High Voltage

Level 1

RS232 (+5)- (+25)V (-5)- (-25)V > (+3)V < (-3) V


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Serial Communication with PC


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Implementation

Hardware: Universal Microcontroller Programmer

Software:

Assembler for 8051

Converts *.asm file to *.obj

Linker for 8051

Links several *.obj files and converts the whole to *.hex

Hex code downloader application program

Provided with universal programmer

Download the hex code into the microcontroller

8051 Architecture and Programming by S Gupta

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