Name : Sudhanshu Sharma

Regd. No. : 11112071

Section : E2101 A-14

Date of performance : (4th April, 2014)Aim : To write a program in verilog to implement various flip-flops (SR-

latch,JK flip-flop, D and T flip-flop)

Description :A flip-flop  is a circuit that has two stable states and can be used to store state information. Aflip-flop is a bistable multivibrator. The circuit can be made to change state by signals appliedto one or more control inputs and will have one or two outputs. It is the basic storage elementin sequential logic. Flip-flops and latches are a fundamental building block of digitalelectronics systems used in computers, communications, and many other types of systems.

Verilog Code for SR flip-flop :module sr_latch(q,rst,clk,r,s);output q;input s,r,clk,rst;reg q,qbar;always@(posedge clk)

 beginif(rst)q=0;case({s,r})2'b00 :q<=q;2'b01 :q<=0;2'b10 :q<=1;2'b11 :q<=1'bx;endcaseendendmodule

 

Test Fixture code :

module srltch_txt_v;// Inputs

reg s;reg r;reg rst;reg clk;

// Outputswire q;

// Instantiate the Unit Under Test (UUT)sr_latch uut (

.q(q),

.s(s),

.r(r),

.rst(rst),

.clk(clk));

initial begins=0;r=0;rst=1;clk=0;#10;s=0;r=0;rst=0;#10;s=0;r=1;#10;s=1;r=0;#10;s=1;r=1;#10;$stop;

endalways begin#5;clk=~clk;end

endmodule

Simulation Result for SR flip-flip : 

 

Verilog Code for JK flip-flop :  

module jk_flip(q,rst,clk,j,k);output q;input j,k,clk,rst;reg q;always@(posedge clk)

 beginif(rst)q=0;case({j,k})2'b00 :q<=q;2'b01 :q<=0;2'b10 :q<=1;2'b11 :q<=~q;endcaseendendmodule

Simulation Result for JK flip-flip :

Verilog Code for D flip-flop :module d_ff(q,clk,reset,d);output q;input clk,reset,d;reg q;always @ (posedge clk)

 beginif(reset)q<=0;elseq<=d;endendmodule

 

Simulation Result for D flip-flip :

Verilog Code for T flip-flop :

module t_ff1(q,clk,reset,t);output q;input clk,reset,t;reg q;initial q=0;always @ (posedge clk)

 beginif(reset)q<=0;case({t})

1'b0 :q<=q;1'b1 :q<=~q;endcaseendendmodule

txt :initial begin

// Initialize Inputsclk = 0;reset = 1;t = 0;#10 reset=0;t=0;#10 t=1;#10;

endalways begin#5;clk=~clk;

endo/p :

 

Simulation Result for T flip-flip :