8 Bit A L U
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Transcript of 8 Bit A L U
![Page 1: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/1.jpg)
8-bit ALU
(AND, OR, ADD, SUB)
![Page 2: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/2.jpg)
Basic Building Blocks
• To initiate the project, we needed to create the basic building blocks: AND, NAND, OR, and NOR gates.
• Since a NOR gate and NAND gate input with Anot and Bnot are a AND gate and a OR gate, respectively, we need only design a NOR and NAND.
![Page 3: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/3.jpg)
NOR Layout
![Page 4: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/4.jpg)
NOR Transient
![Page 5: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/5.jpg)
NAND Layout
![Page 6: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/6.jpg)
NAND Transient
![Page 7: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/7.jpg)
Data Holding and Selection
• To store data, we used D flip-flops at data input and data output.– Usage of the D flip-flops also gave our team
access to the Anot and Bnot needed for the AND and OR gates.
• For data selection at the output, we used 4-1 MUX’s for each bit.
![Page 8: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/8.jpg)
D Flip-Flop Schematic/Transient
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D Flip-Flop Layout
![Page 10: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/10.jpg)
MUX Schematic/Transient
![Page 11: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/11.jpg)
Mux Layout
![Page 12: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/12.jpg)
XOR (used in Adder/Subtractor)
XOR Layout XOR Transient
![Page 13: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/13.jpg)
1-bit Full Adder
![Page 14: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/14.jpg)
Schematic
![Page 15: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/15.jpg)
Transient
![Page 16: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/16.jpg)
Layout
![Page 17: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/17.jpg)
1-bit Full Subtractor
![Page 18: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/18.jpg)
Schematic
![Page 19: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/19.jpg)
Transient
![Page 20: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/20.jpg)
Layout
![Page 21: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/21.jpg)
1-bit ALU
![Page 22: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/22.jpg)
1-bit ALU
![Page 23: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/23.jpg)
1-bit ALU
![Page 24: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/24.jpg)
8-bit AND
![Page 25: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/25.jpg)
8-bit OR
![Page 26: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/26.jpg)
8-bit ALU Layout
![Page 27: 8 Bit A L U](https://reader036.fdocuments.in/reader036/viewer/2022062307/5561af60d8b42afd708b561a/html5/thumbnails/27.jpg)
Conclusion
• This project was successful due to teamwork and dedication.
• My team and I were able to design, test, and build an 8-bit ALU with emphasis on minimum chip size and maximum speed.