8 7 6 5 4 3 REV MLB, DYN SCHEMATIC - Assistenza PC · k24_mlb 33 ethernet connector 39 04/06/2009...

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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL


TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPDCK

DESCRIPTION OF REVISION

Schematic / PCB #’s

03/19/2010MLB, "DYN" SCHEMATIC

1 OF 77

0000876898B

051-8568

B.0.0

1 OF 109

PRODUCTION RELEASED 2010-03-19

External USB Connectors3502/05/200946

K24_MLB

SATA Connectors3401/19/200945

K24_MLB

ETHERNET CONNECTOR3304/06/200939

K24_MLB

Ethernet & AirPort Support3204/06/200938

K24_MLB

Ethernet PHY (RTL8211CL)3104/06/200937

K24_MLB

X16 WIRELESS CONNECTOR3001/27/200934

K24_MLB

DDR3 Support2904/06/200933

K24_MLB

DDR3 SO-DIMM Connector B2802/05/200932

K24_MLB

DDR3 SO-DIMM Connector A2702/05/200931

K24_MLB

FSB/DDR3 Vref Margining2604/06/200929

K24_MLB

SB Misc2502/15/200928

K24_MLB

MCP Graphics Support2404/06/200926

K24_MLB

MCP Standard Decoupling2304/06/200925

K24_MLB

MCP Power & Ground2204/06/200922

K24_MLB

MCP HDA & MISC2103/24/200921

K24_MLB

MCP SATA & USB2004/06/200920

K24_MLB

MCP PCI & LPC1904/06/200919

K24_MLB

MCP Ethernet & Graphics1804/06/200918

K24_MLB

MCP PCIe Interfaces1704/06/200917

K24_MLB

MCP Memory Misc1604/06/200916

K24_MLB

MCP Memory Interface1504/06/200915

K24_MLB

MCP CPU Interface1404/06/200914

K24_MLB

eXtended Debug Port(MiniXDP)1302/25/200913

K24_MLB

CPU Decoupling1203/30/200912

K24_MLB

CPU Power & Ground1104/06/200911

K24_MLB

CPU FSB1004/06/200910

K24_MLB

SIGNAL ALIAS902/04/20099

K24_MLB

Power Aliases802/04/20098

K24_MLB

FUNC TEST702/04/20097

K24_MLB

Revision History601/19/20096

K24_MLB

Revision History501/19/20095

K24_MLB

BOM Configuration401/19/20094

K24_MLB

Power Block Diagram33

System Block Diagram201/19/20092

K24_MLB

CPU/FSB Constraints100

K24_MLB

04/06/2009

70

LCD Backlight Support98

K24_MLB

04/06/2009

69

LCD Backlight Driver (MC34845)97

VEMURI_K19I

02/09/2009

68

DisplayPort Connector94

K24_MLB

04/06/2009

67

DISPLAYPORT SUPPORT93

K24_MLB

04/06/2009

66

LVDS CONNECTOR90

K24_MLB

02/15/2009

65

POWER FETS79

K24_MLB

02/15/2009

64

POWER SEQUENCING78

K24_MLB

02/15/2009

63

MISC POWER SUPPLIES77

K24_MLB

03/24/2009

62

CPU VTT(1.05V) SUPPLY76

K24_MLB

02/04/2009

61

MCP CORE REGULATOR75

K24_MLB

02/15/2009

60

IMVP6 CPU VCore Regulator74

K24_MLB

03/03/2009

59

1.5V/0.75V DDR3 SUPPLY73

58

5V/3.3V SUPPLY72

57

PBUS Supply/Battery Charger70

K24_MLB

02/05/2009

56

DC-In & Battery Connectors69

K24_MLB

02/05/2009

55

AUDIO: JACK TRANSLATORS68

AUDIO

06/09/2009

54

AUDIO: JACK67

AUDIO

06/09/2009

53

AUDI0: SPEAKER AMP66

AUDIO

02/16/2010

52

AUDIO: HEADPHONE FILTER65

AUDIO

06/09/2009

51

AUDIO: LINE INPUT FILTER63

AUDIO

06/09/2009

50

AUDIO: CODEC/REGULATOR62

AUDIO

06/09/2009

49

SPI ROM61

K24_MLB

02/15/2009

48

DEBUG SENSORS AND ADC60

K19_IMLB

02/25/2009

47

SMS59

K24_MLB

03/04/2009

46

WELLSPRING 258

K24_MLB

02/25/2009

45

WELLSPRING 157

K24_MLB

03/04/2009

44

Fan56

K24_MLB

04/06/2009

43

Thermal Sensors55

K24_MLB

02/04/2009

42

Current Sensing54

K24_MLB

01/27/2009

41

VOLTAGE SENSING53

K24_MLB

04/06/2009

40

K84 SMBUS CONNECTIONS52

K24_MLB

01/19/2009

39

LPC+SPI Debug Connector51

K24_MLB

02/15/2009

38

SMC Support50

K24_MLB

02/04/2009

37

77 K84 RULE DEFINITIONS109 01/19/2009

K24_MLB

76 K84 SPECIAL CONSTRAINTS107 01/19/2009

K24_MLB

75 SMC Constraints106 04/06/2009

K24_MLB

74 Ethernet Constraints104 04/06/2009

K24_MLB

73 MCP Constraints 2103 04/06/2009

K24_MLB

72 MCP Constraints 1102 03/30/2009

K24_MLB

Date(.csa)

Contents SyncPage

CRITICAL1 SCH051-8568 SCHEM,MLB_DYN,K84A

PCB CRITICAL1820-2883 PCBF,MLB_DYN,K84A

71 Memory Constraints101 04/06/2009

K24_MLB

PageDate

Sync(.csa)

ContentsContents Sync(.csa) Date

PageTable of Contents1

01/19/20091

K24_MLB SMC49

K24_MLB

04/02/2009

36

SCHEM,MLB_DYN,K84

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:


36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MINI DISPLAY PORT

10/100/1000M E-NET

USB 2.0

PG 56-64PG 55

PG 45

PG 27,28

PG 43

PG 42

PG 48

PG 46

PG 38

PG 36,37

PG 35

PG 65PG 45PG 30

PG 53

PG 53

PG 52

PG 51

PG 49

PG 33

PG 31

PG 30

MINI PCI-E

AirPort

J3401

PG 17

J3900

GIGABIT

RTL8211CL

PG 18

PG 19 PG 21

MIC

LINE-IN/LINE OUT

Amp

U6700

HEADPHONE/LINE OUT

MUX

LINE-IN

Speaker

U6500

U6610,U6620,U6630

J6700,J6701,J6702,J6703,J6704

Conns

Audio

U6201

CIRRUS LOGIC CS4206

Codec

Audio

PG 21

SMB

TRACKPAD

A BSAB,0

SUDDEN MOTION SENSORU5920

U5515,U5535

Boot ROMCURRENT & VOLTAGE SENSORS

Ser

Port80,serial

PG 53,54,60

U4900

FAN CONN AND CONTROL

ADC

CPU & MCP THERMAL SENSORS

J6950,J6900

DC-DC POWER SUPPLIESDC/BATT CONN

J5601

SPI

SMC

H8S/2117

MEMORY

MAIN

J3100,J3200

DIMM

U6100

PG 13

XDP CONN

U1300

B03

MCP79

PG 21

PG 21

Misc

FSB INTERFACE

2 SODIMMS

DDR3 1067MHZ

PG 15,16

PG 14

64-Bit

FSB

1067 MHZ

CORE 2 DUO

INTEL CPU

2.26 GHZ

PG 10

PENRYN

SYNTH

NVIDIA

U3700

RGMII

HDMI OUT

DP OUT

LVDS OUT

UP TO 20 LANES3

PCI-E

DVI OUT

U1400

Bluetooth

76

01

CAMERA

HDA

RGB OUT

SATA

GPIOs

LPC ConnPrt

Fan

J5100

SPI

TRACKPAD/

KEYBOARD

Conn

ODD

HD

U1000

Amps

E-NET

Conn

SATA

98

PCI(UP TO FOUR PORTS)

SATA

CLK

CTRL

TMDS OUT

Conn

LVDS

CONN

J9000

J9400

PWR

LPC

PG 19

USB

Connectors

EXTERNAL

23

(UP TO 12 DEVICES)

PG 20

J3401

J5800

J5800 J4600,4610J9000

54

SMCMIKEYDIMMS

CONN

PG 18

PG 65

PG 67

PG 20PG 34

PG 34

J4501

J4500

System Block DiagramSYNC_DATE=01/19/2009SYNC_MASTER=K24_MLB

2 OF 109

B.0.0

051-8568

2 OF 77




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

04-1

PM_WLAN_EN_L

NANDGATE

GATE

15

PM_SLP_S3_L

PCI_RESET0#

RC

DELAY

=DDRREG_EN

=DDTVTT_EN

TPS51116

PM_SLP_S3_L

P1V8S0_EN

PPVIN_S5_1V5S30V75S0

MCPCORES0_EN

PPVIN_S3_5VS3/PPVIN_S5_3V3S5

PP3V42_G3H_REG

P3V3S0_EN

PPVIN_S0_CPUVTTS0

PPCPUVCORE_VTT_ISNS_R

PPCPUVTT_S0_REG

Q5315

02

CPUVTT

(1.05V)

P5VS3_EN_L

SMC

SMC_PM_G2_EN

PPVOUT_S0_LCDBKLT

PP3V42_G3H_REG

CPU_RESET#

Q7800P60

04

SMC_PM_G2_EN

EN0

EN2P3V3S5_EN_L

U9700MC34845

VIN

IN

ADAPTER

PPVIN_S0_MCPCORE

(13A MAX CURRENT)

PPMCPCORE_S0_REGPPMCPCORE_S0_R R7525

(13A MAX CURRENT)

(10A MAX CURRENT)

PP5V_S3_REG

CURRENT)

P5V3V3_PGOOD

P1V05S0_LDO_PGOOD

P5V3V3_PGOOD

PLT_RST*

IMVP_VR_ON(P16)

ALL_SYS_PWRGD

09PP3V3_S0_FET

PP3V3_S0_PWRCTL

MCPCORESO_PGOOD

CPUVTTS0_PGOOD

P3V3S0_EN

Q7930

PP5VLT_S0_FET

Q7948

U6200VOUT

P5VS0_EN

PP5VRT_S0_FET

P5VS0_EN

Q7940PP5V_S3_REG

EN

VIN

VIN

EN1

U7750

(Q3841,Q3840)

FETS

28

1.05V SO

PPVIN_S5_CPU_IMVP

K84A POWER SYSTEM ARCHITECTURE

PPVCORE_S0_CPU_REG

ISL9504BCRZ

PPBUS_G3H

CPUVTTS0_PGOOD

(7.2A MAX CURRENT)

ENABLE

3.425V G3HOTLT3470

U6990

23PPCPUVCORE_VTT_ISNS

0.01 OHM

VOUTPBUS_VSENSE

02

EN_PSV

PP18V5_DCIN_CONN

SMC RESET "BUTTON"

NCP303LSN

U5000

VOUT

U7000

SLP_S5_L(P95)

LTC2909

PPVBAT_G3H_CHGR_OUT

02

PM_RSMRST_L

J6950

(9 TO 12.6V)

6A FUSE

PPVBAT_G3H_CHGR_REG

BATT_POS_F

PM_SLP_S4_L

F6905

TPS51117U7600

PP1V05_ENET_FET

VR_ON

(44A MAX CURRENT)

1.05V (S5)

P3V3S3_EN

Q7910

P1V05ENET_EN

P1V05_S5_EN

3.3V

06

VOUT

08

VR_PWRGOOD_DELAY

PP1V05_S5_REG

PGOOD

U7400

01

U4900

Q7050

V

(S0)

PGOOD

05

VIN

VOUT1

VOUT2

Q3810

RCDELAY

VOUT

VOUT1(RT)

DDRREG_EN

D6905

PP3V3_S5_REG

MCP79

V2

(S5)

AC

99ms DLY

PM_PWRBTN_L

SMC_RESET_L

IMVP_VR_ONPWRGD(P12)

7A FUSE

CPU_PWRGD

VIN

P3V3_ENET_FET

MCPCORES0_EN

PBUSVSENS_EN

(S0)

(S0)

RC

RC

RC

DELAY

V3

CHGR_BGATE

FETS

S3 TO S0

PWRBTN*

01

D6905

02 26

06

3S2P

11 11-1

RCDELAY

11-3

15

16-2

16-1

02

21

20

18

24 10

03

17

06-1

02

25

SMC

25

SLP_S4_L(P94)

PP1V8_S0_REG

P3V3ENET_EN_L

IMVP_VR_ON

RSMRST_PWRGD

U4900

SLP_S3_L(P93)

S0PGOOD_PWROK

19-1

PP3V3_S0

PP1V05_S0

RSMRST_IN(P13)

RSMRST_OUT(P15)

U7760

CHGR_EN

02

DELAY

DELAY

F7000

14

S5

MCP79

MCPDDR_EN

CPUVTTS0_EN

1.8V LDO

PP1V5_S0

V1

RST*

MCP_CORE

S3

DCIN(16.5V)

U7870

SLP_S5_L

SMC_ONOFF_LPWR_BUTTON(P90)

RST*

P17(BTN_OUT)

PP1V5_S3_REG

(Q7901 & Q7971)

PP0V75_S0_REG

P3V3S3_EN

15-111-2

0.75V

5V

PP1V5_S0_FET

(1A MAX CURRENT)

30

PLTRST*

EN

VIN

PPVIN_G3H_P3V42G3H

32

RESET*

CPU

U1000

U1400

29

07

13

PS_PWRGD

LPC_RESET_L

31

FSB_CPURST_L

CPUPWRGD(GPIO49)

PP3V3_S3_FET

04

CPU VCORE

VINVOUT

V

PP3V3_S5

MCP_PS_PWRGDSMC_CPU_VSENSE

R5492

U2850

VOUT

VIN

VREG3

VOUT2

PGOOD1,2

PP1V5_S0

P16

(S5)

05

SLP_S4_L

CPUVTTS0_EN

PWRGOOD22

RSMRST*

4.5V AUDIO

PP4V5_AUDIO_ANALOG

PP5V_S3

(4A MAX

TPS51125

U7200

TPS62202

SLP_S3_L

1.5V

U7300

ISL6263D

U7500

VOUT

EN

ISL8009B

TPS71745

SLP_S3#

PPBUS_S0_LCDBKLT_PWR

DELAY

RC

RC

DELAY

16-3

16-4

16-6

16-5

16-1

P5VS0_EN

U1400

VIN

BATTERY CHARGER

PBUS SUPPLY/

ENABLES

ISL6258AHRTZ

P5VS3_EN_L

SMC_ADAPTER_EN

AP_PWR_EN 16

OR

Q3801,Q3805

Q3801,Q3805

Power Block Diagram

3 OF 109

B.0.0

051-8568

3 OF 77

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD


TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD




36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

514-0718 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0694 PART FOR AUDIO CONNECTOR

514-0704 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0692 PART FOR RJ45 CONNECTOR353S2718 IS NEW INTERSIL PART FOR FIXING B4 DONGLE ISSUE

514-0705 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0689 PART FOR USB CONNECTORS

514-0706 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0691 PART FOR MINI DP CONNECTOR

DEVELOPMENT BOM

BOM Groups

Module Parts

BOARD STACK-UP

3

Top

SIGNALBOTTOM

SIGNAL(High Speed)

SIGNAL(High Speed)

8

9

2

4

5

6

7

GROUND

SIGNAL

10

POWER

11 GROUND

GROUND

POWER

GROUND

SIGNAL(High Speed)

SIGNAL(High Speed)

BAR CODE LABELS / EEEE #’S

BOM Variants

Programmable Parts

Alternate Parts

337S2983

ONEWIRE_PU,DP_ESD,MIKEY,LDO_NO,MEM_SENSE,1P05_HIGH_SIDE_SENSE,MCP_T_DIODE_SENSOR,MCPSMC_DIGITEMP_YES

BOOTROM_PROG,SMC_PROG,WELLSPRING_PROG

BOOTROM_PROG

341S2485

U5701

WELLSPRING_PROG1 U5701

CRITICALU61001

1 WELLSPRING_BLANK

1085-1651

PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA

CONN,RCPT,60P,P=0.4,STK HT 1.0

POGO PIN,THIN,NOISE-IMPROVED,K84

POGO PIN,TALL,NOISE-IMPROVED,K84

353S2718

1

CRITICAL

IC,SMC,K84

870-1887

2

3

CRITICAL

U6100

FOX_DDR_CONN

CRITICAL

CRITICAL

CRITICAL

CRITICAL

SMC_DEBUG_YES,XDP

SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

639-1144

DEVEL_BOM_PVT,SMC_DEBUG_YES,XDP,NO_VREFMRGN

DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN

XDP_CONN,LPCPLUS,VREFMRGN

PCBA,MLB_DYN,MLX DDR CONN,K84

MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC

K84_DEVEL_PVT

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

337S3680 CPU:2.4GHZCRITICALU1000

XDP_CONN518S0774 J13001

870-1885

870-1886

IC,ISL88042,4X V MONTR,2.78/2.86V,TDFN8

POGO PIN,MED,NOISE-IMPROVED,K844

K84_PROGPARTS

FOX_DDR_CONN

POGO PIN,TALL,NOISE-IMPROVED,K845 ZS0912,ZS0913,ZS0914,ZS0915,ZS0919

ZS0917,ZS0918,ZS0916 CRITICAL

ZS0904,ZS0905,ZS0906,ZS0907,ZS09105870-1886

3 ZS0908,ZS0909,ZS0911POGO PIN,MED,NOISE-IMPROVED,K84

CRITICALZS0900,ZS0901,ZS0902,ZS0903870-1885

U78701 CRITICAL

K84_DEBUG_PVT

CONN,204P,SODIMM,P=0.6MM,HF

CONN,RCPT,RJ45,PLASTIC,HF,K83/K84

CONN,RCPT,USB,4P,PLASTIC,HF,K83/K84

826-4393

K84_COMMON_PVT

CONN,204P,SODIMM,P=0.6MM

CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC

1

514-0706

DEVEL_BOM_PVT

CRITICAL

K84_DEBUG_ENG

EEEE_DD2Y

EEEE_DD2X

[EEEE_DD2Y] CRITICAL

[EEEE_DD2X]

1826-4393

CRITICAL1

K84_COMMON

K84_DEBUG_PROD

K84_MCP

U49001

K84_MISC

J39001514-0704

337S3769 U1000 CRITICAL

MLX_DDR_CONNJ31001 CRITICAL516-0213

K84_DEVEL_ENG

338S0710 MCP_B03U1400 CRITICAL1

1 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA J3200 CRITICAL516S0706

CRITICALJ31001516-0201

CRITICALSCREW1,SCREW2,SCREW3,SCREW44452-1708 SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97

MLX_DDR_CONNCRITICAL1516S0790

514-0705 CRITICALJ4600,J4610

1 CONN,RCPT,MDP,20P,PLASTIC,HF,K83/K84 J9400 CRITICAL

CRITICALDEVEL_PVT

1

1

SYNC_DATE=01/19/2009SYNC_MASTER=K24_MLB

BOM Configuration

COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_PROD,K84_PROGPARTS

J3200

IC,GMCP,MCP79,35X35MM,BGA1437,B03

PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7550 CPU:2.26GHZ

K84_COMMON_PVT,CPU:2.26GHZ,FOX_DDR_CONN,EEEE_DD2X

K84_COMMON_PVT,CPU:2.26GHZ,MLX_DDR_CONN,EEEE_DD2Y

K84_DEVEL_PVT

PCBA,MLB_DYN,FOX DDR CONN,K84

639-1145

085-1651 K84 MLB_DYN DEVELOPMENT PVT

COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_ENG,K84_PROGPARTS

SMC_PROG

335S0610

CRITICAL

CRITICAL

BOOTROM_BLANK

IC,SMC,HS8/2117,9X9MM,TLP,HF

K84 MLB_DYN DEVELOPMENT PVT

U4900 CRITICAL SMC_BLANK

IC,WELLSPRING CONTROLLER,K84

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

IC,PRGRM,EFI BOOTROM,K84A

338S0563

341T0281

341S2491

157S0055 ALL DELTA AS ALTERNATE

ALL CYNTEC AS ALTERNATE152S0796

DALE/VISHAY, MAGLAYERS AS ALTERNATEALL

ALL

ALL

152S0586 ALL

KEMET AS ALTERNATEALL128S0218

152S0516

104S0018 104S0023 ALL

ALL

138S0602

152S0685

157S0058

138S0603

128S0093

152S0874

152S0847

353S2989 353S2811

MURATA AS ALTERNATE

DALE/VISHAY AS ALTERNATE

MAGLAYERS AS ALTERNATE

MAGLAYERS AS ALTERNATE

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

152S0778152S0693

ISL6258AHRTZ-TR5394A AS ALTERNATE

4 OF 109

B.0.0

051-8568

4 OF 77




36

BRANCH

REVISION

DRAWING NUMBER SIZE

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PAGE TITLE

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

4/2/2009: RELEASE 9.2.0 (MAJOR):

- PAGE 97:DISCONNECTED PINS 2 AND 5 FROM GND PINS(13,19,21)AND CONNECTED SEPARATELY TO

- PAGE 97: RENAMED SINGLE PIN NET GND_LCDBKLT TO GND_LCDBKLT_PGND

- PAGE 49: FIXED PLACEMENT NOTE ASSOCIATED WITH C4907 (SHOULD BE: PLACE NEAR PIN E1)- PAGE 7: SCRUBBED TPS AS PER UPDATE FROM TOM

- PAGE 4: CHANGED MCP P/N TO 338S0702 AS PER CHALLEE

- PAGE 90: ADDED C9017 (1000PF) CAP AS PER JOHN SCHEN

GND_LCDBKLT_PGND AND ASSIGNED MIN_LINE/NECK_WIDTH ATTRIBUTES

- PAGE 97: REPLACED D9710 WITH 40V PART- APN 371S0580 AS PER DEREK- PAGE 97: STUFFED R9726 AND SWAPPED C9705 AND R9705 AS PER FREESCALE FOR COMPENSATION.

- ADDED BOMOPTION = NOSTUFF ATTRIBUTE TO R6725

C6871, U6870, C6872, R6872, & R6873

- PAGE 74: CHANGE L7400 AND L7401 TO 152S1019 AS PER DAYU FOR COST SAVING. ALSO, UPDATED ASSOCIATED TEXTS

- PAGE 94: REPLACED C9486 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY)

- PAGE 74: REMOVED C7400, C7402, R7451 AND R7452 AS PER DAYU

- PAGE 70: REPLACED R7080 WITH APN 107S0142 WHICH IS TRUE 4-TERMINAL SENSE RESISTOR WITH SMALLER PACKAGE

3. PAGES 31, 32: REPLACED 0.1UF 0204 TYPE DDR3 DECOUPLING CAPS WITH 0402 TYPE CAPS ( APPLE P/N : 132S1059)

- UPDATED THE SCHEMATICS, PCBF AND PCBA PART NUMBER INFO

- DELETED IR SPECIFIC NETS ON SATA CONNECTOR

- CORRECTD BOM CONFIG TABLES

1/23/2009: RELEASE 0.0.5-

1. PAGE 75: MCP VCORE INDUCTOR CHECK FOR PD: CHANGED L7560 TO 152S0966 AND THEN TO 152S0867. BUT NOW IT IS BACK TO 13A PART FOR NOW

15: PAGE 97: REPLACED BKLT DRIVER CKT WITH THAT OF FREESCALE PART, SIMILAR TO K19I

- PAGE 9: DELETED R0950 PCIE_FW_PRSNT_L ’S PD RESISTOR

- PAGE 54: REMOVED BMON CURRENT SENSE CIRCUIT- UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_PROD AND BLANK PROGRAMMED PARTS. ALSO, DELETED BMON_ENG BOM OPTION

- DELETED KB BACKLIGHT DRIVER/DETECTION CKT

AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_NO WITH THESE 0 OHMS

- PAGE 50: ADDED UNUSED NET ALIAS FOR SMC_BIL_BUTTON_L (NC_SMC_BIL_BUTTON_L)

- PAGE 70: ADDED TP TO PIN 13

- REMOVED BOMOPTION = NOSTUFF ATTRIBUTE FROM R6724

- PAGE 39: REPLACED ETHERNET CONNECTOR WITH THAT OF M97A/K24 PART APN 514-0636 (SYNC’ED WITH K24)

- PAGE 60: CORRECTED PLACEMENT NOTE ASSOCIATED TO XW6080 TO REFLECT D9710 INSTEAD OF D9701

- PAGE 57: ADDED PLACEMENT NOTES TO C5702 AND C5704 AS PER JOHN SCHEN’S FEEDBACK

SEL1 SIGNAL AND REMOVED 10K PD ON ST PIN. REPLACED C5926 WITH 0.01UF CAP AS PER DATA SHEET. AND,

- PAGE 4: ADDED 138S0603 AS ALT FOR 138S0602B FOR SUPPLY REDUNDANCY

- PAGE 76: REPLACED L7620 WITH ITS REPLACEMENT - APN 152S0518

- PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 & C7240 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS

- PAGE 9: CHANGED ALIAS OF FW_PME_L TO TP_FW_PME_L

USB_IR_N/P

- PAGE 31 & 32: PIN SWAPS ON THE DDR3 CONNECTOR PAGES FOR ROUTING PURPOSES (REFER TO RON’S EMAIL)

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.0.0***

- PAGE 73: ADDED SHORT XW7304 FROM PIN 1 OF C7300 TO POWER GND (PIN 18)

- ADDED PLACEMENT NOTES TO XW SHORTS AS PER DAYU

13. PAGE 69: REPLACED BATTERY CONNECTER WITH PN 518S0540 AND BIL CONNECTOR WITH PN 518S0588. UPDATED CONNECTIONS ACCORDINGLY

6. PAGE 45: REPLACED SATA HDD CONNECTOR WITH APPLE PN 516S0350 AND UPDATED CONNECTIONS ACCORDINGLY

- NO CHANGES SINCE LAST MINOR RELEASE 0.0.2

- PAGE 70: DELETED R7050 CONNECTION BETWEEN CHGR_AGATE AND CHGR_LOWCURRENT_GATE

-PG. 67, NO STUFFED R6724

-PG. 67, DELETED L6706-PG. 67 ADDED =PP3V3_S3_AUDIO NET

(MATCHES UPDATED ALIASES ON PAGE 8)

- PAGE 9: ADDED OMIT ATTRIBUTE TO THE LVDS HOLE

- PAGE 8: ADDED =PP5V_S3_P5VRTS0FET ALIAS, GOING TO 5V RT S0 FET CIRCUIT

- DELETED PAGES 41,42,43,48,97,98,105 [FIREWIRE, IR CONTROLLER, BACKLIGHT CKT]

INITIAL RELEASE 0.0.1-

- SET SOURCE SYNC OF AUDIO PAGES (62-63, 65-68) FROM LENG’S AUDIO PAGES

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

- PAGE 97: ADDED BOM OPTION - NOSTUFF- TO R9702 AS PER K19I

2/26/2009: RELEASE 4.0.0 (RFA RELEASE):

- PAGE 78: DELETING P5VLTS3_EN RC CIRCUIT AS IT IS NO LONGER NEEDED (SEE ABOVE). ALSO UPDATED

- NAME CHANGED TO TMLB. SO CALLING IT RELEASE 0.0.1

- PAGE 51: R5156, R5157 AND R5158 ARE NOW 0 OHM ISOLATION RESISTORS PLACED ON SPI BUS NEXT TO THE LOCATION WHERE

- PAGE 34: R3453 IS MODIFIED TO 110K RESISTOR, R3454 IS NOSTUFF AND R3453 IS PULLED UP TO PP3V3_WLAN_F.

- PAGE 9: ADDED UNUSED FIREWIRE LANE NETS AS TEST POINTS

- PAGE 4: UPDATED EEE NUMBER - 8CG

- PAGE 9: ADDED SMC_SYS_KBDLED TP ALIAS

- PAGE 8: DIVIDED PP5V_S3_REG INTO TWO BRANCHES - PP5VRT_S3_REG & PP5VLT_S3_REG- PAGE 8: ADDED PP5V_S3_DEBUG_ADC_AVDD/DVDD & PP5V_S3_DEBUG_ISNS ALIASES FOR NEW SENSOR PAGE 60

- PAGE 28: REMOVED RTC POWER SOURCES CIRCUIT AND SUPERCAP_NO BOM OPTION FROM R2820- PAGE 34: SINCE X16 AIRPORT CARD SOLUTION IS BEING USED, PP5V_S3_WLAN IS REPLACED BY PP3V3_S3_WLAN

- PAGE 34: DISCONNECTED PP5V_S3_BTCAMERA_F POWER RAIL FROM THE CONNECTOR AND REPLACED IT WITH PP3V3_S3_BT

ALONG WITH THE USB CAMERA SIGNALS TO LVDS PAGE. ALSO, RENAMED THIS POWER RAIL TO PP5V_S3_CAMERA ON LVDS

- PAGE 34: REPLACED L3404 WLAN INDUCTOR WITH LOW DCR 0603 PART - APN 155S0367

- PAGE 45: CHANGED SATA HDD CONNECTOR TO APN 516S0616- PAGE 45: ADDED SENSE RESISTORS R4598 AND R4599 ON 5V ODD AND 5V HDD RAILS RESPECTIVELY

- PAGE 39: REPLACED ETHERNET CONNECTOR WITH APN 514-0668 (SIMILAR TO K36B)

- PAGE 34: ADDED SENSE RESISTOR R3452 ON PP3V3_WLAN SIGNAL

(SIMILAR TO M96). CAMERA SIGNALS ARE ROUTED VIA LVDS CONNECTOR. MOVED PP5V_S3_BTCAMERA POWER CIRCUIT

THIS IS TO ENSURE 3.3V LEVEL AT THE INPUT OF U3402 AND MAINTAIN 100MS DELAY SPEC BETWEEN 3.3V POWER

(GOING TO Q3450). ALSO, REPLACED PP5V_WLAN WITH PP3V3_WLAN ON PAGE 6 (FUNCTIONAL TEST POINTS)

- PAGE 8: ADDED ALIAS PP5VLT_S3_V5IN UNDER PP5VRT_S3_REG- PAGE 8: ADDED ALIAS PPVIN_S3_5VLTS3 UNDER PPBUSB

- PAGE 50: UNSTUFFED R5055 AND USED SMC_NB_MISC_ISENSE SIGNAL PORT (SMC) FOR CONNECTING PPBUSA ISENSE SIGNAL.

- PAGE 51: REPLACED TWO DEMUX SOLUTION WITH A SINGLE DEMUX 1X2 SOLUTION. APN USED - 353S2220

- PAGE 52: ADDED SENSOR ADC CONNECTION BLOCK UNDER ’SMC 0 SMBUS CONNECTIONS’ SECTION

- PAGE 70: ADDED BYPASS 0 OHM RESISTOR R7050 (NOSTUFF FOR NOW) OPTION FOR NEW CHIP WHICH WON’T REQUIRE U7060 SOLUTION

- PAGE 4: REMOVED 104S0018 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE

- PAGE 8: RENAMED PPVIN_S5_1V5S3_0V75S0 TO PPVIN_S5_1V5S30V75S0- PAGE 8: DELETED PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_BKL_VDDIO, PP3V3_S0_MCP_PLL_VLDO

- PAGE 78: ADDED P5V_LTS3_PGOOD POWER GOOD SIGNAL (WIRED AND WITH OTHER S0 RAILS PGOOD) CORRESPONDING TO 5V LT

IT BRANCHES INTO TWO - ONE GOING TO MLB SPI ROM AND THE OTHER GOING TO LPC CONNECTOR. THESE RESISTORS ARE

- PAGE 4: REMOVED 152S0778 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE SINCE L7260 AS HAS BEEN REPLACED WITH THIS PART

- PAGE 54: MOVED PBUS INA210 CIRCUIT TO THIS CURRENT SENSOR PAGE. RENAMED REF DES AS PER THIS PAGE 54- PAGE 55: DELETED J5590 CONNECTOR (CONNECTED TO HEAT-PIPE TEMPERATURE DETECTION RAILS)

- PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 WITH 68UF OSCON CAP (APN 128S0275) & C7240 WITH 39UF (APN 128S0248)

- PAGE 55: REPLACED U5515 & U5535 WITH CHEAPER APN 353S2571

- PAGE 78: RENAMED P5VS3_EN_L TO P5VRTS3_EN_L (RT POWER SUPPLY ENABLE) AND ADDED R7814, C7814 S3 ENABLE CIRCUIT- PAGE 75: CHANGED C7571 & C7560 TO 68UF OSCON CAPS (APN 128S0275)- PAGE 77: REMOVED 1.05V S0 PLL LDO CIRCUIT. AND, REMOVED LDO_NO BOM OPTION FROM R7745

- PAGE 72: REPLACE Q7220 WITH SIZ700DT AND L7260 WITH SMALLER 10A PART (APN 152S0778)- PAGE 71: CHANGED C7160 TO 39UF OSCON CAP (APN 128S0248)

- PAGE 69: REPLACED BATTERY CONNECTOR J6950 WITH APN 518S0540 (M96) CONNECTOR- PAGE 69: ADDED D6951 ESD DIODE ON BIL SMBUS SIGNALS (NOSTUFF FOR NOW)

- PAGE 61: RENAMED SPI SIGNALS TO MATCH WITH CHANGES ON PAGE 51

PLACED ON THE LPC CONNECTOR BRANCH. THIS IS TO AVOID STUBS IN PRODUCTION

TO THE CARD GETTING STABLE AND AIRPORT GETTING OUT OF RESET

2. ADAPT JACK INSERT DETECT CIRCUIT TO CD3282 JACK INSERT DETECT FUNCTION.

5. PAGE 34: REPLACED SCHMITT’S TRIGGER WITH PN 311S0449

- PAGE 73: ADDED SENSE RESISTOR R7350 ON 1.5V DDR3 SUPPLY RAIL

- PAGE 69: ADDED BOM OPTION NOSTUFF TO D6950 FOR NOW

8. PAGE 46: REPLACED ESD DIODES WITH CHEAPER PN 377S00667. PAGE 45: ADDED 2 PIN CONNECTOR (APPLE PN 518S0519) FOR SIL

- PAGE 60: REMOVED WELLSPRING 3 PAGE (GOING BACK TO K24 SOLUTION) AND REPLACED IT WITH K19I DEBUG SENSOR PAGE (SCHUTIL SYNC)

- PAGE 73: UPDATED 1.5V/0.75V POWER SUPPLY WITH CORRECT NET NAMES REFLECTING 1.5V/0.75V INSTEAD OF 1.8V/0.9V AND

- PAGE 8: ADDED PP3V3_S3_BT ALIAS FOR BLUETOOTH ON RIGHT CLUTCH CONNECTOR PAGE

5V S3 IS DIVIDED INTO RT AND LT POWER SUPPLY AND WILL HAVE CORRESPONDING S0 FETS)- PAGE 8: DIVIDED PP5V_S0_FET INTO TWO BRANCHES - PP5VRT_S0_FET & PP5VLT_S0_FET (FOR ROUTING PURPOSE,

- PAGE 4: CORRECTED APN FOR PROGRAMMED PARTS - SMC, BOOT ROM, WELLSPRING

- PAGE 4: REMOVED SUPERCAP_NO BOM OPTION. ADDED DEBUG_ADC BOM OPTION UNDER K84_DEVEL_ENG

***PAGES SYNC’ED FROM K24 SINCE LAST RELEASE 1.0.0***

3. REMOVED JACK EXTRACT CIRCUITRY, FUNCTION IS TAKEN OVER BY CD3282

- PAGE 34: ADDED CHOKES ON PCIE TX/RX SIGNALS. UPDATED PAGE 6 (FUNCTIONAL TEST POINTS) ACCORDINGLY

- PAGE 71: ADDED NEW PAGE FOR PP5V_LT_REG POWER SUPPLY. UPDATED ALL THE REF DES AS PER THE PAGE NUMBER

- PAGE 60: UPDATED WLAN DIVIDER CIRCUIT WITH 3V3 POWER RAIL INSTEAD OF 5V

[ONLY CHIP SELECT IS BEING DEMUXED]

ADDED ALIAS ON THIS PAGE

PAGE

- PAGE 76: REPLACE Q7620 WITH SIZ700DT

1. REPLACED MIKEY CD3272 WITH CD3282

(THIS IS FOR NEW SENSOR PAGE 60)

- PAGE 4: REMOVED LDO_YES BOM OPTION

4. REMOVE FM ANTENNA NET.

2. ADDED DIDT TO ALL THE GATE AND PHASE NETS

- ADDED DIDT ATTRIBUTE

- PAGE 28: DELETED FW_RESET_L SIGNAL- PAGE 58: DELETED KB BKLT CIRCUIT

IN SYNC WITH PAGE 8 ALIASES

- PG 50: SWAPPED THE PART NUMBER AND THE ALTERNATE PART NUMBER FOR VR5020. MADE ISL60002 THE ALTERNATE PART

***PAGES SYNCED FROM K24 SINCE LAST RELEASE 2.0.0***

- CHANGED SPEAKER AMPS TO LM48310, PLACEHOLDERS FOR LM48311. LM48311 IS THE CSP VERSION OF THE LM48310.***PAGES SYNCED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 2.0.0***

- REMOVED OPTIONAL STUFFING RESISTORS AROUND THE RE-TASKING JACK ANALOG SWITCH.- CHANGED LDO TO B LP5900.

- PAGE 75: CHANGED R7525 TO 107S0132 FOR COST SAVING AS PER DAYU- PAGE 74: CHANGED Q7401 AND Q7403 TO 376S0771 AS PER DAYU- PAGE 74: CHANGED Q7400 AND Q7402 TO 376S0772 AS PER DAYU

- PAGE 74: REMOVED UNUSED NETWORK ON U7400 PIN 5 AND PIN 6 AS PER DAYU [R7406, C7410, R7427, R7426]- PAGE 73: MOVED THE SENSE RESISTOR NEXT TO INDUCTOR- PAGE 73: ADDED ONE MORE OSCON 39UF CAP ON INPUT SIDE- PAGE 72: L7220 CHANGED TO 152S0778 FOR COST SAVING AS PER DAYU

- PAGE 71: DISCONNECTING EN_PSV (PIN 34) FROM P5VLTS3_EN SIGNAL AND CONNECTING IT TO- PAGE 70: CHANGED Q7000 AND Q7001 CHEAPER TO 376S0667 (HAT1128) AS PER DAYU’S RECOMMENDATION- PAGE 70: CHANGED Q7050 TO 376S0761 AS PER DAYU & K24 DESIGN- PAGE 69: DELETED NOTE REGARDING INDUCTOR FILTER REQUIREMENT ON BATT_POS_F (AS PER JOHN SCHEN)- PAGE 69: REPLACED BATTERY CONNECTOR WITH THAT OF K24 (APN 518-0359)- PAGE 57: REPLACED KEYBOARD CONNECTOR WITH THAT OF K24 (APN 518S0637) - SYNC’ED FROM K24- PAGE 34: ADDED A TEXT NOTE THAT J3401 (AIRPORT CONNECTOR) COULD CHANGE TO 1.8MM HEIGHT APN 516S0582

- PAGE 90: REFRESHED THE SYMBOL OF U9000, PART NUMBER CHANGED TO 353S2603

- PAGE 57: REPLACED KEYBOARD CONNECTOR WITH APN 518S0738

POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET- PAGE 34: ADDED NOTE WITH REGARD TO 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN- PAGE 34: ADDED NOTE WITH REGARD TO SMBUS CONNECTIONS TO THE AIRPORT CONNECTOR- PAGE 13: REPLACED XDP CONNECTOR WITH MINI XDP CONNECTOR APN 516S0625- PAGE 8: ADDED BACK - PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_MCP_PLL_VLDO- PAGE 8: RENAMED PP1V05_S0_MCP_PLL_UF BACK TO PP1V05_S0_MCP_PLL_UF_R

- PAGE 74: STUFF R7413 AS PER DAYU

PP5VLT_S3_V5IN (5VRT PS)

- PAGE 4: ADDED LDO_NO BOM OPTION

- PAGE 54: REMOVED NOTE ON AMON AND BMON

- PAGE 77: ADDED BACK - 1.05 PLL LDO CIRCUIT

1/21/2009: RELEASE 0.0.4-

2/6/2009: MAJOR RELEASE 0.1.0 -

2/6/2009: WEEKLY RFA BOM RELEASE 1.0.0-

2/15/2009: RELEASE 2.0.0 (WEEKLY RFA)-

2/25/09: WEEKLY RFA RELEASE (3.0.0)

3/4/2009: RELEASE 5.0.0 (RFA)-

ASSOCIATED TEXT NOTE- PAGE 97: FIXED CONNECTION POINT (DOT) FOR LCDBKLT_VIN- PAGE 97: ADDED 0 OHMS SERIES RESISTOR ON LCD_BKLT_PWM FOR DEBUGGING PURPOSES- PAGE 97: RENAMED LCD_BKLT_PWM TO LVDS_IG_BKL_PWM- PAGE 97: CHANGED VOVP VALUE TO 6.9V AS PER FREESCALE FEEDBACK- PAGE 97: ADDED R9726 (22K) AND SWAPPED C9705 AND R9705 LOCATIONS FOR NOISE REDUCTION- PAGE 97: DELETED C9712 AS IT IS REDUNDANT- PAGE 97: ADDED PLACEMENT NOTE ATTRIBUTE TO C9713 AND C9710 FOR PLACING THOSE NEAR L9710

- PAGE 78: ADDED 0 OHM ISOLATION RESISTORS ON POWER GOOD SIGNALS (BEFORE WIRED AND)

- PAGE 8: DELETED PP5V_S0_BKL, RENAMED PP1V05_S0_MCP_PLL_UF_R TO PP1V05_S0_MCP_PLL_UF

- PAGE 90: UPDATED LVDS CONNECTOR CONNECTIONS AS PER STEVE’S RECOMMENDATION. ADDED CAMERA SIGNALS- PAGE 79: ADDED 5V LT S0 FET AND UPDATED NET NAMES FOR BOTH RT AND LT S0 FET CIRCUITS ACCORDINGLY

POWER SUPPLY

FOR GENERATING P5VLTS3_EN ENABLE SIGNAL FOR LT POWER SUPPLY

AS PER FREESCALE RECOMMENDATION

***PAGES SYNC’ED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 1.0.0***

17. PAGE 4: REMOVED BKLT_ENG BOM OPTION16. PAGE 69: MOVED THE DECAP C6908 TO CORRECT PART U6901.5 ( SIMILAR TO K24)

- PAGE 45: CHANGED J4501 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA- PAGE 50: DELETED SMC_PPBUSA_ISENSE ALIAS AND STUFFED R5055- PAGE 54: DELETED U5470 INA210 CIRCUIT AS THERE IS NO NEED

R7051 (6259_YES) CONNECTION BETWEEN CHGR_PIN26 AND CHGR_LOWCURRENT_GATE;

R7054 (6259_NO) CONNECTION BETWEEN CHGR_PIN6 AND GND_CHGR_SGND- PAGE 73: RENAMED TEXT NOTE FOR =PP1V5_S3_REG NET TO VOLTAGE=1.5V

- PAGE 45: MIRROR’ED J4500 AND RECONNECTED PINS AS PER NEW PIN OUT DESCRIPTION FROM DIANA

R7052 (6259_NO) CONNECTION BETWEEN CHGR_PIN26 AND GND_CHGR_SGND;R7053 (6259_YES) CONNECTION BETWEEN CHGR_PIN6 AND PIN 12 (VHST);

TO HAVE TWO PPBUS BRANCHES

- PAGE 97: STUFF R9716 AS PER KIRAN’S FEEDBACK

-PG. 68, ADDED R6873

-PG. 67, DELETED R6726

3/20/2009: RELEASE 7.1.0 (MAJOR)-

- PAGE 9: ADDED LVDS HOLE APN 998-1521

- PAGE 70: AS PER DAYU, ADDED:

- PAGE 4: CHANGE THE CPU TO NEW APNB 337S3704

3/24/2009: RELEASE 7.2.0 (MAJOR)-

AS PER DAYU

- PAGE 7: RENAMED PP5VRT_S3 TO PP5V_S3 ["LT" & "RT" NOMENCLATURE CLEAN-UP]

- DELETED PAGE 71 (5V S3 LT POWER SUPPLY) AS THERE IS NO NEED OF A SEPARATE 5V S3/S0 SUPPLY

- PAGE 8: COMBINED 5V S3 LT AND RT ALIASES INTO ONE =PP5V_S3_REG AND RENAMED NETS

- PAGE 21: UNSTUFFED R2143 PU ON MCP_GPIO_4 AS THERE IS ALREADY A 100K PU ON AUDIO PAGE

- PAGE 55: ADDED BC846BM NPN TRANSISTOR (APN 372S0129) TO MCP T-DIODE SENSOR CIRCUIT SIMILAR TO

- PAGE 9: ADDED ALIAS MCP_GPIO_4 FOR MIKEY MIC LOAD DETECT CIRCUIT

- PAGE 72: RENAMED NETS AND NOTES TO REMOVE REFERENCES TO RT POWER SUPPLY

- PAGE 72: ADDED C7282 APN 128S0218 IN PARALLEL WITH C7280 AS PER DAYU- PAGE 73: REPLACED Q7320 AND Q7321 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU

- PAGE 75: REPLACED C7576 WITH 0.022UF APN 132S0102 CAP TO INCREASE THE SLEW RATE

- PAGE 76: CORRECTED MAX OUTPUT NOTE TO REFLECT 7.2A INSTEAD OF 8A- PAGE 75: REPLACED Q7560 AND Q7565 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU

- PAGE 76: REPLACED Q7620 WITH 2 CSD58858 APN 376S0790 MOSFETS AS PER DAYU

- PAGE 78: ROUTED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL TO THE WIRED AND CIRCUIT

- PAGE 60: REPLACED DUAL PACKAGE OPA330 OPAMPS WITH SINGLE PACKAGE ONES - APN 353S2179

- PAGE 9: DELETED EXTRA MEDIUM POGO PIN ZS0912 AND SCREW HOLES Z0908, Z0909

- PAGE 74: REPLACED C7433 AND C7431 WITH 0.001UF CAPS APN 132S1035

- PAGE 77: ADDED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL VIA A 0 OHM RESISTOR TO PIN 3 (PG) OF THE LDO- PAGE 78: DELETED P5V_LTS3_PGOOD AS THERE IS NO 5V LT POWER SUPPLY ANYMORE

[U6030, U6031, U6040, U6041]. ALSO, ADDED C6031 & C6041

- PAGE 7: DELETED PP5VLT_S3 NETS

- PAGE 8: DELETED =PPVIN_S3_5VLTS3, =PP5VLT_S3_V5IN NETS

3/25/2009: RELEASE 7.3.0 (MAJOR)-

(LT & RT NOMENCLATURE CLEAN-UP)

- PAGE 45: ADDED APN TEXT NOTE FOR SIL CONNECTOR

- PAGE 75: ADDED A NOTE OCP=14.5A TO R7575

3/26/2009: RELEASE 7.4.0 (MAJOR)-

- PAGE 72: REPLACED L7260 WITH APN 152S0959 AS PER DAYU

THAT IN CPU T-DIODE SENSOR AND STUFFED C5540

3/26/2009: RELEASE 7.5.0 (MAJOR)-

- PAGE 78: RENAMED =P5VRTS3_EN_L TO =P5VS3_EN_L

- PAGE 7: DELETED PP5V_S0, PP5V_S3 AND ADDED PP5VRT_S0,PP5VLT_S0, PP5VRT_S3, PP5VLT_S3 DEBUG

- PAGE 4: DELETING ENTRIES FOR 107S0138 AND 107S0139 FROM ALTERNATES PARTS TABLE AS THEY WOULD BE REPLACING

- PAGE 97: FOR 25KHZ OPERATION, CHANGE R9726 TO NO STUFF, INTERCHANGE R9705(6.8K) WITH C9705

- PAGE 25: CHANGED C2500,C2501,C2502,C2503,C2515,C2520,C2528,C2540,C2580,C2582,C2584,C2586,C2588,

- PAGE 74: ADDED PLACEMENT NOTES TO C7419,C7422 AND C7423 AS PER JOHN SCHEN’S FEEDBACK

- PAGE 72: CONNECTED SMC_PM_G2_EN SIGNAL TO EN0 PIN 13 OF U7200 VIA A 100K RESISTOR FOR KEEPING THE POWER SUPPLY

- PAGE 73: MOVED C7344 NEXT TO R7350 AND ADDED PLACEMENT NOTE (JOHN SCHEN WANTED IT TO BE NEXT TO L7320

- PAGE 97: CHANGED C9711 FROM 0.1UF TO 1.0UF 0603 TYPE CAP AS PER FREESCALE FEEDBACK- PAGE 97: CHANGED C9715 AND C9716 TO 50V CAPS FOR COST SAVING AND AS PER FREESCALE FEEDBACK

- PAGE 97: CHANGED R9710 TO 6.65K APN 114S0298 AND R9716 TO 226K APN 114S0445 PARTS AS PER

- PAGE 107: REMOVED FOLLOWING SENSOR NETS CONSTRAINTS: ISNS_P1V5S0MCP_P/ISNS_P1V5S0MCP_N;

- PAGE 9: REPLACED 5 SHORT POGO PINS WITH MEDIUM ONES AND ADDED THREE EXTRA MEDIUM ONES (TOTAL MEDIUM

-PG. 67, CONNECTED HP OUTPUTS TO NC OF U6700 AND LINE INPUTS TO NO OF U6700.

- PAGE 90: ADDED EMI CAPS (C9017-C9025) ON I2C, LED_RETURNS AND LCD_BKLT POWER RAILS GOING TO LVDS.

- PAGE 73: REPLACED C7307,C7308 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY)

- PAGE 70: ADDED BOM OPTION 6259_YES TO R7050 AND 6259_NO TO U7060 AND AMON PULLDOWN LOGIC

- PAGE 70: MOVED C7028 TO PPVBAT_G3H_CHGR_REG AS PER JOHN SCHEN’S FEEDBACK

REPLACED C5923-C5925 CAPS WITH 0.033 UF VALUES FOR CUT-OFF FREQUENCY OF ~146HZ

- PAGE 45: RENAMED =PP5V_S0_HDD_R TO PP5V_S0_HDD_R (AS PER UNALIASED.LST REPORT)

- PAGE 34: REPLACED THE AIRPORT CONNECTOR WITH 1.8 MM HEIGHT CONNECTOR APN 516S0582

- PAGE 52: REMOVED REFERENCES TO THE LED BACKLIGHT AS FREESCALE PART DOESN’T HAVE I2C BUS ACCESS

- PAGE 79: REPLACE Q7940 AND Q7948 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24- PAGE 90: REMOVED EMI CAPS [C9017-C9025] ON LED_RETURN, I2C AND LCD_BKLT POWER NETS- PAGE 90: UPDATED LVDS CONNECTOR PINOUT CONNECTIONS AS PER STEVE’S NEW SPREADSHEET

- PAGE 97: CHANGED R9717 - R9722 FROM 0.1% TO 1% PARTS FOR COST SAVINGS AND AS PER FREESCALE FEEDBACK

- PAGE 107: ADDED CONSTRAINTS FOR FOLLOWING SENSOR NETS: ISNS_HDD_P/ISNS_HDD_N; ISNS_ODD_P/ISNS_ODD_N;

3/6/2009: RELEASE 6.0.0 (RFA:)-

- PAGE 74: STUFFED C7432 AS PER DAYU

OFF IN CASE IF SMC TURNS OFF

- PAGE 4: ADDED DALE/VISHAY ALTERNATES FOR 104S0023 --> 104S0018

- PAGE 73: DELETED NOTES AT THE BOTTOM RIGHT AFTER CONSULTING WITH DAYU

- PAGE 4: ADDED BOM OPTION 6259_NO TO THE TABLE UNDER K84_MISC BOM GROUP

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 5.0.0***-PG. 67, CHANGED U6700 CB INPUT TO BE CONTROLLED BY CS4206 GPIO0.

- PAGE 75: ADDED PLACEMENT NOTE TO C7563 AS PER JOHN SCHEN’S FEEDBACK

- PAGE 52: DELETED TERM BIL FROM SMC BATTERY & BIL CONNECTIONS

- PAGE 9: ADDED TP ALIASES TO IMVP6_VR_TT AND IMVP6_NTC

- PAGE 8: DELETED =PP3V42_G3H_5V3V3_EN AS IT IS NO LONGER USED- PAGE 8: DELETED =PP3V3_S0_TPAD AS THERE IS NO KEYBOARD BACKLIGHT DRIVER- PAGE 8: DELETED =PP3V42_G3H_AUDIO AS IT IS NO LONGER USED

- PAGE 4: ADDED 152S0693 AS ALT FOR 152S0778 FOR SUPPLY REDUNDANCY

-PG. 62, CHANGED TP_AUD_GPIO_0 TO AUD_GPIO_0.

- PAGE 72: REMOVED NOSTUFF’ED C7251 AS PER DAYU

- PAGE 69: CHANGED L6995 TOB APN 152S1017 FOR COT SAVING AND EFFICIENCY


CIRCUIT COMPONENTS. TURNED ON 6259_NO, FOR NOW, ON PAGE 4 TABLE



DAYU PERFERRED IT TO BE AFTER THE SENSE RESISTOR

- PAGE 75: MOVED C7569 TO PPMCPCORE_S0_R AS PER JOHN SCHEN’S FEEDBACK

-PG.66, REPLACED THE LM48310’S (U6610/20/30) WITH LM48311’S

ADDED PLACEMENT NOTES TOO

(DAYU’S RECOMMENDATION)

ISNS_PVCORES0MCP_P/ISNS_PVCORES0MCP_N

-PG. 67, CHANGEED J6703 TO TWO PIN CONN.-PG. 67, DELETED C6760/1/2/3.

-PG. 66, CHANGED C6630/31 TO 0.022UF-PG. 66, CHANGED C6610/11 TO 0.022UF

-PG. 66, ADDED R6613/14/15/16/17

ISNS_LCDBKLT_P/ ISNS_LCDBKLT_N

POGO PINS = 8) AS PER NEW MCO

3/17/2009: RELEASE 7.0.0 (RFA)-

- PAGE 74: ADDED XW7401-XW7404 SHORTS ACROSS L7400 AND L7401

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 6.0.0***-PG. 67, DELETED R6725 AND NET =PP3V42G3H_AUDIO

-PG. 62, ADDED PLACEMENT COMMENT ATTR. TO XW6200/1-PG. 67, ADDED PLACEMENT COMMENT ATTR. TO XW6700/1/10/11-PG. 68, ADDED PLACEMENT COMMENT ATTR. TO XW6851/80-PG. 66, REPLACED U6610/30 WITH LM48556 CKTS

-PG. 62, REPLACED C6225 WITH APN: 128S0216

- PAGE 9: REMOVING 2 EXTRA TALL POGO PINS (ZS0911, ZS0912) AS PER NEW MCO

- PAGE 45: REPLACE Q4590 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24

- PAGE 59: REMOVING R5923 AND ONLY 1 PU ON SEL LINES IS ENOUGH- PAGE 70: REPLACING R7020 WITH APN 107S0138 PART FOR COST SAVING- PAGE 70: REPLACING R7008 WITH APN 107S0139 PART FOR COST SAVING- PAGE 70: R7080 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER- PAGE 73: R7350 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER

ISNS_AIRPORT_P/ISNS_AIRPORT_N; ISNS_1V5_S3_P/ISNS_1V5_S3_N;

- PAGE 77: CHANGED U7740 TO 500MA 1.05V LDO

- PAGE 7: RENAMED PP5V_S3_BTCAMERA_F WITH PP3V3_S3_BT_F

- PAGE 8: DELETED ALIAS =PP1V05_S0_SMC_LS AS IT IS NO LONGER NEEDED

- PAGE 52: DELETE J6955 REFERENCE AS THERE IS NO BIL CONNECTOR

- PAGE 54: REPLACING R5492 WITH APN 107S0139 PART FOR COST SAVING

- PAGE 97: ADDED DIDIT=TRUE ATTRIBUTE TO THE SWITCHING NODE PINS 3 & 4

- PAGE 97: NO STUFF’ED C9721 - C9726 AS PER FREESCALE FEEDBACK

-PG. 68, CHANGED AUD_PORTB_DET_L TO AUD_PORTA_DET_L.-PG. 68, CHANGED AUD_PORTG_DET_L TO AUD_PORTB_DET_L.-PG. 67, SET MIN. LINE AND NECK WIDTHS FOR AUD_CONN_L AND AUD_CONN_R

***PAGES SYNCED FROM K24 SINCE LAST RELEASE 5.0.0***

- PAGE 26: CHANGED C2615,C6210 TO 138S0653

- ADDED PLACEMENT NOTES (ATTRIBUTE) TO ALL XW SHORTS

- PAGE 7: ADDED PPBUS_R_G3H DEBUG VOLTAGE TEST POINT

- PAGE 34: REPLACE Q3450 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24

-PG. 67, ADDED J6704

-PG. 65, DELETED R6521

-PG. 66, ADDED C6634/5-PG. 66, ADDED R6631/2/3/4/5-PG. 66, ADDED C6612/13

-PG. 65, ADDED R6523/4

FREESCALE FEEDBACK

VOLTAGE TEST POINTS

C2595 TO 138S0653

THE 107S0074/75 PARTS

AS IN K19I

-PG. 67, ADDED XW6702-PG. 66, UPDATED 5V S3 ALIAS NOTES

1. PAGE 3: POWER BLOCK DIAGRAM - ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR. ALSO, ADDED SENSE RESISTOR ON PPBUS

- PAGE 8: ADDED =PP3V42_G3H_HALL FOR THE HALL EFFECT CONNECTOR

***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.5.0***

- PAGE 69: ADDED HALL EFFECT CONNECTOR CIRCUIT J6955 APN 516S0787

- PAGE 8: ADDED PLACEMENT NOTE TO Q5502

- PAGE 8: DELETED =PP3V42_G3H_PPBUSAISNS AS PPBUS SENSE CIRCUIT HAS BEEN REMOVED

- PAGE 72: REPLACED C7282 WITH OSCON APN 128S0248 IN PARALLEL WITH C7280 AS PER DAYU

3/26/2009: RELEASE 7.6.0 (MAJOR)-

- ADDED OMIT BOM OPTION TO ALL THE XW SHORTS- ADDED DIDT=TRUE ATTRIBUTE TO BOOT/VBST SIGNALS OF ALL THE SWITCHING SUPPLIES- PAGE 8: DELETED =PP3V42_G3H_BATT AS THERE IS NO BIL CONNECTOR

- PAGE 8: ADDED =PP3V3_S3_AUDIO ALIAS NET FOR CASEY’S NEW CHANGES BELOW

- PAGE 8: RENAMED ALIAS =PP5V_S3_P5VS0FET TO =PP5V_S3_P5VLTS0FET AS THIS GOES TO 5V LT S0 FET CIRCUIT

- PAGE 79: RENAMED INPUT VOLTAGE NETS OF 5V S0 FET CIRCUITS TO REFLECT RT AND LT

1P05_HIGH_SIDE_SENSE OPTIONS UNDER K84_COMMON BOM GROUP- PAGE 4: ADDED MCP_T_DIODE_SENSOR, MCPSMC_DIGITEMP_NO BOM OPTIONS UNDER

K84_COMMON BOM GROUP

- PAGE 4: UPDATED DESCRIPTION FOR THE CPU- PAGE 7: UPDATED TPS AS PER NEW UPDATE FROM TOM (SPREADSHEET ATTACHED TO THE RADAR)- PAGE 12: REPLACED C1260 WITH APN 128S0267 AS PER DAYU- PAGE 34: DELETED TEXT NOTE ASSOCIATED WITH J3401

ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 OHMS

OHMS

CONSTRAINT SET

3/31/2009: RELEASE 9.0.0 (RFA)-

- ADDED BACK PAGES 97-98 (LCD BACKLIGHT DRIVER AND SUPPORT CKT)

1/27/2009: TMLB FIRST RELEASE 0.0.1-

- REPLACED TEXT TMLB WITH MLB THROUGH OUT THE SCHEMATICS

2/5/2009: RELEASE 0.0.2 -- COPIED TMLB OVER TO MLB AS K84 WILL BE PENRYN SKU WHILE K83 WILL BE ATOM SKU

- PAGE 4: UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_ENG FOR K84_COMMON BOM GROUP

- PAGE 8: DELETED FIREWIRE, IR AND BMON SPECIFIC NETS

- PAGE 55: REPLACED CPU/MCP THERMAL SENSORS U5515 ANDB U5535 WITH THE CHEAPER VERSION APNB 353S2573

2. PAGE 8: ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR, WHILE PPBUSB FEEDS 5V/3.3 V SUPPLY, LCD BKLT & PPBUS VOLTAGE SENSE CKT

- PAGE 4: ADDED CYNTEC ALTERNATES FOR 107S0074 --> 107S0138 [R7020] AND 107S0075

-PG. 67, ADDED R6725

- PAGE 70: REMOVED R7080 SENSE RESISTOR AND RENAMED =PPBUSB_G3H TO =PPBUS_G3H AS NO NEED

- PAGE 34: CHANGED J3401 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA

- PAGE 7: DELETED PPBUS_R_G3H AS NO NEED OF TWO PPBUS BRANCHES

-PG. 66, CHANGED C6610/11/30/31 TO 0.015UF-PG. 68, ADDED MIKEY MIC LOAD COMPARATOR CKT

-PG. 68, CORRECTED CODEC OUTPUT SIGNALS TABLE COMMENTS

- PAGE 8: COMBINED TWO SEPARATE PPBUSA/B BRANCHES INTO ONE =PPBUS_G3H

- PAGE 70: ADDED R7050 (6259_YES) CONNECTION FROM PIN 4 (VREF) TO PM_SLP_S3_L AS PER DAYU

- PAGE 59: REPLACED SMS PART WITH THE NEW BOSCH BMA141 ANALOG PART. ADDED R5923 10K PU RESISTOR ON

- DELETED NOTE ABOVE U6500

PP3V3_WLAN, R6010 HAS BEEN CHANGED TO 634K TO GET VDIVIDER = ~2V

- PAGE 55: ADDED MCP_T_DIODE_SENSOR BOM OPTION TO THE MCP T-DIODE THERMAL

CURRENT SENSE CIRCUIT AND WITH 1P05_HIGH_SIDE_SENSE FOR CPU 1.05V AND

CONNECTIONS. AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0

TO SMB_0_S0_DATA NETS

R9730 PIN

SHORT TO ISOLATE NOISY PGND FROM THE SYSTEM GND. NAMED IT

- PAGE 97: RENAMED GND_LCDBKLT TO GND_LCDBKLT_SGND

SYSTEM GND

ALSO, CHANGED R9705 TO 10K 1% VALUE - APN 114S0315

4/1/2009: RELEASE 9.1.0 (MAJOR)-

14. PAGE 70: DIVIDED PPBUS INTO TWO BRANCHES - PPBUSA & PPBUSB. ADDED SENSE RESISTOR R7080 (2 MOHMS) ON PPBUSA. ALSO ADDED INA210 AMPLIFIER CKT ACROSS SENSE LINES. ADDED PP3V42_G3H_PPBUSAISNS (IN210 POWER) ALIAS ON PAGE 8

12. ADDED PAGE 60 AND COPIED OVER ZEPHYR2 SCHEMATICS PAGE FROM M97 IPD_FLEX_WELLSPRING. DELETED THE IPD BOARD CONNECTOR. CALLING IT WELLSPRING 3

10. PAGE 4: ADDED DEBUG_SENSE BOM OPTION TO THE K84_DEVEL_ENG BOM GROUP11. PAGE 58: DELETED IPD FLEX CONNECTOR J5800. RENAMED PP18V5_S3, PP3V3_S3_LDO_R, PP3V3_S3_LDO TO PP18V5_S3_LDO, PP3V3_S3_IPD_R AND PP3V3_S3_IPD RESPECTIVELY TO MATCH WITH NEW ADDED PAGE 60 NET NAMES. UPDATED THESE NET NAMES ON PAGE 7 ALSO

9. PAGE 54: ADDED BOM OPTION- DEBUG_SENSE- TO CPU 1.05V/CPU VCORE HIGH SIDE CURRENT SENSE AND MCP MEM VDD CURRENT SENSE CIRCUITS FOR DEVELOPMENT BOM

4. PAGE 34: REPLACED AIRPORT CONNECTOR WITH PN 516S0580 AND UPDATED CONNECTIONS ACCORDINGLY

- NO CHANGES SINCE LAST MAJOR RELEASE 0.1.0

- PAGE 72: REPLACE Q7220 WITH SIZ700DT

- PAGE 7: DELETED IR_RX_OUT, PP5V_S3_IR_R, KBDLED_ANODE, SMC_KBDLED_PRESENT_L

- REMOVED ALS SPECIFIC NETS (PAGE 34 & 52)

- UPDATED PAGES 72-73 : 5V/3.3V & DDR3 POWER SUPPLIES AS PER FLO’S RECOMMENDATIONS

- CORRECTED BOM CONFIG TABLE (ADDED BACK BKLT_ENG)

1/21/2009: RELEASE 0.0.3-

- UPDATED BOM CONFIGURATIONS

1/21/2009: RELEASE 0.0.2-

- UPDATED SCHEMATIC AND PCB PART NUMBER INFO- REPLACED K24 REFERENCES WITH K84- ALL PAGES SYNC’ED FROM K241/19/2009:

Revision History

- PAGE 73: REPLACE 16V INPUT SIDE CAPS C7331 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS

[R7008] --> 107S0139

- PAGE 69: REMOVED BIL CIRCUIT AS IT NO LONGER A POR [R6960, C6954, D6951, C6953, C6952, J6955, C6951]

- PAGE 102: ADDED CONN_PCIE_MINI_R2D_P/N AND CONN_PCIE_MINI_D2R_P/N NETS IN THE

SENSOR CIRCUIT

- PAGE 54: REPLACED DEBUG_SENSE BOM OPTION WITH MEM_SENSE FOR MCP MEMORY VDD

- PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN SMC B SMBUS AND MCP SMBUS 1

- PAGE 9; ADDED 3 ADDITIONAL TALL POGO PINS AS PER NEW MCO AND DELETED ZS0909 SHORT POGO AS IT WAS EXTRA

- PAGE 7: DELETED SMC_BIL_BUTTON_L NET FROM BATT SIGNAL CONN GROUP AS BIL IS NO LONGER A POR

- PAGE 97: DISCONNECTED PGND (OF CAPS) FROM XW9700 AND ADDED A SEPARATE XW9701

- PAGE 97: FIXED THE LCDBKLT_VIN SIGNAL NAME ASSOCIATION TO THE CORRECT NET INSTEAD OF

- PAGE 69: REFRESHED HALL EFFECT SENSOR WITH THE NEW SYMBOL

- PAGE 52: FIXED SENSOR ADC SMBUS CONNECTIONS (BOTH SCL AND SDA WERE WRONGLY CONNECTED

- REMOVED NOTE RE: ROUTING TO MCP79 GPIO ABOVE U6870

- ADDED BOMOPTION = MIKEY ATTRIBUTE TO R6860, C6860, Q6802, R6864, R6865, & R6861- UPDATED SIGNAL PATH CHART TO INCLUDE MCP79 GPIO ASSIGNMENTS- ADDED BOMOPTION = MIKEY_LOAD_DET ATTRIBUTE TO R6870, R6871, C6870,

- CHANGED R6211 & R6212 FROM 39 OHMS TO 22 OHMS***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 8.0.0***

- PAGE 4: ADDED MIKEY_LOAD_DET BOM OPTION UNDER K84_MISC BOM GROUP

- PAGE 75: ADDED C7590 (2.2UF) APN 138S0579 IN PARALLEL WITH C7563 AS PER DAYU

K19I UPDATES, EXCEPT VOLTAGE DIVIDER FOR PP3V3_WLAN [K19I USES 5V RAIL]. FOR

- PAGE 59: DELETED R5923 FROM THE TEXT NOTE

CPU VCORE HIGH SIDE CURRENT SENSE CIRCUIT

- PAGE 52: ADDED BOM OPTION MCPSMC_DIGITEMP_NO TO R5230 AND R5231

- PAGE 34: ADDED LC FILTER (L3406 AND C3432) ON PP3V3_S3_BT POWER RAIL AS PER JOHN SCHEN’S FEEDBACK

- PAGE 60: MANUALLY UPDATED RESISTORS VALUES (VOLTAGE DIVIDERS,AMPLIFIER GAINS, RC) TO MATCH WITH

- UPDATED SCHEM AND PCBF PART NUMBER INFO

- PAGE 4: ADDED 085 DEVELOPMENT BOM VARIANT & K84_DEVEL_ENG, K84_DEVEL_PVT BOM GROUPS

- PAGE 66: FIXED UNNAMED NETS CONNECTED TO - R6632

- PAGE 7: RENAMED RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR

- PAGE 7: DELETED THERMAL FUNC_TEST SECTION

- PAGE 9: FIXED BAD_TP_NC NETS - TP_RTL8211_CLK125, TP_PP3V3_ENET_PHY_VDDREG

- PAGE 34: RENAMED TITLE: RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR

- PAGE 69: CHANGE PIN OUTS OF J6955 AS PER CHINMAY

- PAGE 78: FIXED BAD_TP_NC NETS - TP_DDRREG_PGOOD

- PAGE 9: DELETED Z0912 MLB MOUNTING HOLE AS NO LONGER NEEDED

- PAGE 7: DELETED BATT SIGNAL CONN AND ADDED HALL EFFECT CONNECTOR TEST POINTS

- PAGE 7: SCRUBBED THROUGH THE FUNCTIONAL TEST POINTS AGAINST TOM’S SPREADSHEET

- PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN MIKEY AND MCP SMBUS 1 CONNECTIONS.

- PAGE 45: ADDED VOLTAGE, MIN LINE AND NECK WIDTH FOR PP5V_S0_HDD_FLT

- PAGE 4: ADDED SHORT POGO PIN 870-1699 AS ALTERNATE FOR THE MEDIUM ONES

- PAGE 4: DELETED DEBUG_SENSE BOM OPTION AND ADDED MEM_SENSE AND

- PAGE 74: FIXED UNNAMED NETS CONNECTED TO - XW7401, XW7402, XW7403 AND XW7404

- PAGE 9: ADDED TP_ ALIASES FOR - CARDREADER_RESET, USB_CARDREADER_N/P, AND

3/29/2009: RELEASE 8.0.0 (RFA)-

- PAGE 50: REPLACED R5030 WITH APN: 114S0114,(IT’S A 1% TOL, 1/16W, 0402, 84.5OHM RESISTOR)

- PAGE 52: ADDED 0 OHMS STUFFING OPTION TO CONNECT MIKEY SMBUS CONNECTIONS TO MCP SMBUS 0.

- PAGE 90:RE-ROUTED LED_RETURN SIGNALS FOR LAYOUT FEASIBILITY(CHIP WAS MOVED TO TOP SIDE)

- PAGE 49:FIXED PLACEMENT NOTES ASSOCIATED WITH R4999,C4920(SHOULD BE:PLACE NEAR PIN M12)- PAGE 51: FIXED PLACEMENT NOTE ASSOCIATED WITH R5146 - PLACE NEAR U5110 INSTEAD OF SMC- PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH SMBUS_SMC_B_S0_SCL/SDA

SYNC_MASTER=K24_MLB

Revision HistorySYNC_DATE=01/19/2009

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11/01/2009: RELEASE C.0.0 (FAB)-

- FINAL PVT OK2FAB RELEASE

09/21/2009: RELEASE A.0.0 (FAB)-

- PAGE 3: UPDATED POWER SYSTEM BLOCK DIAGRAM- PAGE 2: UPDATED SYSTEM BLOCK DIAGRAM- PROD (POST 1ST MONTH OF PRODUCTION) OK2FAB RELEASE

09/16/2009: RELEASE 17.0.0 (FAB)-

- FINAL DVT OK2FAB RELEASE

- PAGE 4: ADDED 1 NEW POR BOMS 639-0554, 639-0555 AND 1 NEW DEVELOPEMENT BOM

NUMBERS AS PER KIRAN’S EMAIL

- PAGE 57 : CHANGED R5714 TO 165 OHMS APN 114S0141 AS PER

05/11/2009: RELEASE 12.14.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL):

05/10/2009: RELEASE 12.13.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL):

- REMOVED R6725 AND =PP3V3_S3_AUDIO CONNECTION TO MAX14504 ANALOG SWITCH

- PAGE 4: DELETED 152S0694 ALTERNATE ENTRY FOR 152S0138 AS IT IS NOT USED

I2C_MIKEY_SCL/SDA_R

- PAGE 9: ADDED 7 EXTRA TALL POGO PINS FOR EMI - 4 STUFFED AT THE BOTTOM,

- PAGE 8: ADDED GLOBAL DIGITAL GROUND NET WITH MIN_LINE/NECK_WIDTH

- PAGE 97: CHANGED MIN_NECK_WIDTH ASSOCIATED WITH PPVOUT_S0_LCDBKLT TO 0.24MM

4/2/2009: RELEASE 9.3.0 (MAJOR):

- PAGE 4: REMOVED 514-0706, 514-0705 AND 514-0718 FROM THE ALTERNATES TABLE

POR IS LOW NOISE POGO PINS

- PAGE 4: ADDED NEW INTERSIL ISL6258A (WITH IMPROVED CHARGE CURRENT ACCURACY

TO K84- PAGE 4: REPLACED CPU APN 337S3704 WITH 337S3769 IN MODULE PARTS TABLE AND

REMOVED 337S3704 FROM THE ALTERNATE PART TABLE AS POR IS 337S3769

- PAGE 4: REMOVE 870-1794, 870-1698 & 870-1820 FROM THE ALTERNATES TABLE AS

05/20/2009: AGILE RELEASE PROTO 2 OK2FAB 13.0.0 (FAB):

- FINAL PROTO 2 OK2FAB RELEASE

***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 9.2.0***

- PAGE 4:B ADDED 5.95MM SANYO PART 128S0288 AS ALTERNATE TO 128S0271

- PAGE 4: REMOVED 138S0606 FROM THE ALTERNATES TABLE AS IT DOESN’T PERTAIN

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

**PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.6.0***

AND TO K84 MISC BOM GROUP. THIS IS TO STUFF ISL6258 PART

WITH EITHER ISL6258 OR ISL6259 DEPENDING UPON PAGE 4 BOM TABLE

- PAGE 52: DELETED TEXT NOTE ON BATTERY LED DRIVER AS IT IS NA TO K84

- PAGE 13: FIXED THE NOTE ON THE XDP PAGE- REPLACING 920-0620 ADAPTER

- PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER

08/05/2009: RELEASE 15.3.0 (MAJOR)-

- PAGE 4: ADDED PDNI PLATED AUDIO CONNECTOR W/ CHAMFER APN 514-0718 AS AN

- PAGE 4: ADDED GOLD PLATED AUDIO CONNECTOR W/O CHAMFER APN 998-2622 AS ANALTERNATE FOR J6700 APN 514-0694

- PAGE 4: ADDED GOLD PLATED RJ45 CONNECTOR APN 998-2621 AS AN ALTERNATE FOR

- PAGE 97: REFRESHED THE SYMBOL OF C9715 4.7UF APN 138S0661

08/27/2009: AGILE PDFC OK2FAB RELEASE 16.0.0 (FAB)-

- PAGE 59: ADDED NOSTUFF BOM OPTION ATTRIBUTE TO C5923-C5925 AS STATED

- PAGE 70: CHANGED R7047 FROM 10 OHM TO 0 OHM, 5%, APN:116S0004 TO FIX SLOW

- PAGE 4: ADDED GOLD PLATED MINI DP CONNECTOR APN 998-2626 AS AN ALTERNATE

- PAGE 4: ADDED LOW NOISE POGO PINS 870-1885 (MEDIUM), 870-1886 (TALL), AND

- PAGE 49: CHANGED C4950, C4951, C4952 TO APN:132S0131 (CAP,0402,0.033UF,16V,10%) AS THESE WOULD BE USED TO ACHIEVE CUT-OFF FREQUENCY OF

SEEN BY SMC CHIP. CAPS ON SMS PAGE WOULD BE UNSTUFFED~146HZ FOR SMS (AS PER THE VENDOR) AND FILTER THE NOISE TOO AS

- PAGE 4: ADDED GOLD PLATED USB CONNECTOR APN 998-2624 AS AN ALTERNATE FOR

- PAGE 4: ADDED METAL PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO

REPLACED R6961 WITH A 0 OHM RESISTOR AND NOSTUFF’ED C6955

- CONNECT AUDIO JACK SHIELD TO DIGITAL GROUND.

0.6/0.24MM

- PAGE 4: ADDED APN 138S0606 (TAIYO-YUDEN) AS AN ALTERNATE FOR APN 138S0602

ALTERNATE FOR J6700 APN 514-0694

- PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER

- FINAL PDFC (PRE DVT) RELEASE!

- PAGE 70: CHANGED C7043 FROM 0.1UF TO 1UF, 10%, APN:138S0640 TO FIX SLOW

- PAGE 97: CHANGED L9710 BACK TO THE ORIGINAL APN 152S0826 AS 2525 PACKAGE CAN’T FIT IN

RJ45 J3900 CONNECTOR

- PAGE 50: CHANGED R5030 TO 48.7 OHMS APN 114S0091 (SIL CURRENT TO 12MA)

CONNECTED IT TO PIN 1 (RSMRST_PWRGD) TO FIX LEAKAGE ISSUE

3V3S5_DRVL (FIXED THE NET NAME- ADDED UNDERSCORE)

- PAGE 4:B ADDED 5.95MM SANYO PART 128S0286 AS ALTERNATE TO 128S0248

- PAGE 9: REPLACED Z0906,Z0907,Z0910 AND Z0911 MLB MOUNTING HOLES WITH 2.7 MM

- PAGE 4: UNDER K84_PROGPARTS BOM GROUP, REPLACED BLANK P/N WITH

AND VOLTAGE ATTRIBUTES- PAGE 9: REPLACED Z0905 AND Z0913 MLB MOUNTING HOLES WITH 2.7 MM

- ADDED 100PF EMC CAP ON THREE SPEAKER CONNECTORS.

- PAGE 78: DELETED SYNONYMS AS THEY ARE NOT NEEDED ANYMORE

- PAGE 28: DELETED MAKE_BASE=TRUE ASSOCIATED WITH PCIE_RESET_L

CHARGING ISSUE, PER DAYU

CHARGING ISSUE, PER DAYU

SLOW CHARGING ISSUE, PER DAYU- PAGE 70: CHANGED R7031 FROM 10 OHM TO 2.2 OHM, 5%, APN:116S0010 TO FIX

ABOVE. ALSO, EDITED THE NOTE ACCORDINGLY

870-1887 (THIN) AS ALTERNATES

J4600/J4610 APN 514-0689

FOR J9400 APN 514-0691

J3900 APN 514-0704

- PAGE 4: DELETED LOW NOISE MURRATA CAP ENTRY FROM THE ALTERNATES TABLE

ENGINEER

- PAGE 70: DISCONNECTED PM_SLP_S3_L FROM PIN 4 (VREF) AS IT WAS INCORRECTLY

- PAGE 97: NOSTUFFED C9716 AND CHANGED C9715 TO APN 138S0661 AS POR IS TO

- PAGE 46: REPLACED J4600 & J4610 USB CONNECTORS WITH POR PLASTIC CONNECTOR

- PAGE 4: DELETED CHGR_6258 AND RENAMED 6259_NO TO

07/27/2009: RELEASE 15.2.0 (MAJOR)-

HAVE SINGLE CAP LOW NOISE MURRATA CAP SOLUTION AS PER ACOUSTICS

CONNECTED, THEREBY CAUSING HIGHER SLEEP/SHUTDOWN POWER

132S0178 TO FIX THE SMART TEST FAILURE- PAGE 49: CHANGED SMS NOISE FILTERING CAPS C4950-C4952 TO 0.47UF APN

07/21/2009: RELEASE 15.1.0 (MAJOR)-

CATEGORY AS PER CASEY

PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE

- PAGE 70: DELETED OMIT BOM OPTION FROM U7000 AS ISL6259 HAVE BEEN

- NO CHANGES SINCE LAST MAJOR 14.7.0. THIS IS FINAL EVT FAB RELEASE

PRODUCTION HAS NOW MOVED TO ITS ALTERNATE PART 353S2718

: ZS0920- PAGE 78: ADDED 0 OHM BOM OPTION R7895 BETWEEN 1V05_S5_PGOOD

AND RSMRST_PWRGD FOR DEBUG PURPOSES

06/11/2009: RELEASE 14.4.0 (MAJOR)-

- PAGE 97: CHANGED MIN_LINE/NECK_WIDTH ASSOCIATED WITH GND_LCDBKLT_SGND TO

- REMOVED OPTIONAL STUFF-AROUND RESISTORS FOR ANALOG SWITCH

- PAGE 9: DELETED GND MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES

- PAGE 78: DELETED MAKE_BASE=TRUE ASSOCIATED WITH ALL_SYS_PWRGD

- PAGE 9: ADDED ONE MORE TALL POGO PIN ON BOTTOM SIDE

4/3/2009: RELEASE: 9.6.0 (MAJOR):

- PAGE 78: ADDED BOMOPTION ATTRIBUTE OMIT TO U7870 AS NEW INTERSIL PARTPART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE

- PAGE 39: ADDED BOMOPTION ATTRIBUTE OMIT TO J3900 AS NEW PG2 CONNECTOR

- PAGE 9: ADDED NOSTUFF BOM OPTION TO ZS0920

- PAGE 97: CHANGED R9710 TO 7.68K APN 114S0304 (LCD BKLT CURRENT TO 20MA)

06/25/2009: RELEASE 14.7.0 (MAJOR)-

ETHERNET JITTER ISSUE

- PAGE 49: REPLACED C4950-C4952 WITH 1UF APN 138S0640 CAPS

06/22/2009: RELEASE 14.6.0 (MAJOR)-

- PAGE 97: ADDED CRITICAL ATTRIBUTE TO C9715 & C9716

**PAGES SYNCED FROM CASEY’S AUDIO_MLB SINCE LAST RELEASE 12.1.0***

CASE_B2_SM DUE TO PACKAGING ERROR (SAME APN)

- PAGE 94: REPLACED J9400 DP CONNECTOR WITH POR PLASTIC CONNECTOR

- PAGE 75: CHANGE R7565 TO 1OHM APN 113S0023 PER RDAR://6812904

APN 514-0692

514-0691 ALTERNATE FOR 514-0690;

- NO CHANGE SINCE LAST RFA RELEASE 11.0.0.***THIS IS A RESUBMIT AS PREVIOUS RFA DIDNT GO THROUGH***

4/23/2009 - RELEASE 12.1.0 (MAJOR):

ADDED CORRESPONDING NOTES-

- NO CHANGE SINCE LAST MINOR RELEASE 10.1.1

- PAGE 4: ADDED CPU APN 337S3769 AS ALTERNATE TO 337S3704

- PAGE 13: REPLACED J1300 XDP CONNECTOR WITH MORE ROBUST CONNECTOR

- PAGE 75: CHANGE Q7560 AND Q7565 TO SIS426 APN 376S0749 PER

- PAGE 39: REPLACED J3900 ETHERNET CONNECTOR WITH POR PLASTIC CONNECTOR

UNDER MODULE PARTS TABLE .

- PAGE 4: DELETED ENTRIES IN THE ALTERNATE BOM TABLE FOR THE FOLLOWING APN:

- PAGE 70: FIXED Q7001 DRAIN-SOURCE ORIENTATION

06/12/2009: RELEASE 14.5.0 (MAJOR)-

06/11/2009: RELEASE 14.3.0 (MAJOR)-

- PAGE 77: CHANGED R7780 TO 25.5K APN 114S0354 & R7781 TO 80.6K APN

DIAMETER PLATED HOLES - APN 998-1584

REMOVED

114S0402 AS PER DAYU

NETS TO FIX NOISE ISSUE- PAGE 49: ADDED 0.1UF CAPS ON SMS_X_AXIS, SMS_Y_AXIS & SMS_Z_AXIS

- PAGE 4: ADDED APN 138S0661 LOW NOISE MURATA CAPS AS ALTERNATE FOR

4/6/2009 - RELEASE 11.0.0 (OK2FAB):

C9715 & C9716 TO FIX LCD BKLT AUDIBLE NOISE ISSUE

- PAGE 78: DISCONNECTED P1V05_S5_PGOOD FROM PIN 3 OF U7840 AND

4/5/2009: RELEASE 10.1.0 (MAJOR):

4/2/2009: RELEASE: 9.5.0 (MAJOR):

AS PER JOHN SCHEN

- PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH

05/22/2009: AGILE RELEASE PROTO 2 OK2FAB 14.0.0 (FAB)-

***RETRY***

RDAR://PROBLEM/6875543

SMC B SMBUS TO MCP79 SMBUS 1

05/08/2009: RELEASE 12.12.0 (MAJOR & WEEKLY ECO):

MIKEY TO MCP79 SMBUS 0 INSTEAD OF SMBUS 1 AND TO CONNECT

IT HAS I2C BUS PU TO S0 POWER RAIL


- PAGE 97: CHANGED L9710 TO A BIGGER 2525 PACKAGE (LOW DCR) APN 152S0585 FOR

THOUGH POR IS PLASTIC MINI DP CONNECTOR PART- PAGE 94: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS

THOUGH POR IS PLASTIC USB CONNECTOR PART- PAGE 46: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS- PAGE 4: ADDED 4 QUANTITIES OF DIMM CONNECTOR SCREWS APN 452-1708

5/01/2009: RELEASE 12.8.0 (MAJOR):- PAGE 4: ADDED A36 EEE NUMBER FOR NEW BOM CONFIGURATION 639-0254

SUPPLY RAILS TO ADC CHIP

I2C BUS

05/01/2009: RELEASE 12.9.0 (MAJOR):

- PAGE 4: UPDATED PLASTIC PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO

514-0690 PLASTIC ALTERNATE FOR 514-0691 METAL;

- PAGE 60: CHANGED U6050 INA 211 PART TO 200X GAIN INA 210 APN 353S2073

514-0688 PLASTIC ALTERNATE FOR 514-0689 METAL

- PAGE 46: REPLACED PLASTIC USB CONNECTORS WITH METAL APN 514-0689 PARTS

- PAGE 60: ADDED 0 OHMS SERIES RESISTORS R6003 AND R6004 ON AVDD AND DVDD


- PAGE 60: CHANGED R6001 & R6002 TO 33 OHMS RESISTORS TO FIX UNDERSHOOT ON

ADDED TWO ENTRIES (J3200 AND J3100) FOR FOXCONN AND TWO FOR MOLEX

- PAGE 4: ADDED NEW BOM ENTRY 639-0254 FOR MOLEX DDR3 CONNECTOR CONFIG. ALSO,

- PAGE 76: CHANGED THE CPU VTT OVER CURRENT TRIP POINT PER RDAR://6792329 BY

- PAGE 67: MOVED L6707 & L6708 TO J6703 (FULL RANGE SPEAKER CONNECTOR)4/28/2009: RELEASE 12.5.0 (MAJOR):

FOR EMI PURPOSES - L6707 & L6708

4/28/2009: RELEASE 12.4.0 (MAJOR):

- PAGE 74: CHANGED R7415 TO 10.5K AS PER RDAR://6792327

- PAGE 74: UNSTUFFED C7434 AS PER RDAR://6792327

- REPLACED J6700 WITH APN: 514-0694

4/24/2009 - RELEASE 12.2.0 (MAJOR):

- PAGE 70: ADDED OMIT BOM OPTION TO U7000 AS THIS PART WILL GET STUFFED

DIAMETER PLATED HOLES - APN 998-1584

AS PER KIRAN- PAGE 97: CHANGED R9716 FROM 226K TO 243K TO CHANGE THE OVP POINT TO 35.3V

- PAGE 4: ADDED CHGR_6258 BOM OPTION UNDER MODULE PARTS TABLE

APN 514-0690

- ADDED DZ 6702 AND L6706

4/27/2009 - RELEASE 12.3.0 (MAJOR & WEEKLY ECO):

EDITED 639-0035 BOM NAME TO REFLECT FOXCONN DDR3 CONNECTOR.

- PAGE 57: DELETED NO_TEST = TRUE ATTRIBUTE FROM Z2_SCLK AND

- PAGE 34: RENAMED P5VWLAN_SS NET TO P3V3WLAN_SS

4/3/2009: RELEASE: 10.0.0 (RFA):

(DUE TO 0 OHMS)

IN MODULE PARTS TABLE

TO SHOW A SEPARATE CONNECTION FOR CLARITY- PAGE 52: MOVED THE R5251 CONNECTION TO SENSOR ADC TO THE RIGHT SIDE

516-0213 AND 516S0709

514-0689 ALTERNATE FOR 514-0688

APN 998-2515

BOARD WITH 920-0782 ADAPTER FLEX

**SCHEMATIC AND BOM CLEAN-UP**

APN 514-0688

- PAGE 69: RENAMED 6259_NO/YES TO CHGR_6259_NO/YES

CHGR_6259_NO. REPLACED CHGR_6258 WITH CHGR_6259_NO

CHANGING R7604 FROM 8.87KN) TO 6.04KN)

RDAR://6812904

4/6/2009 - RELEASE 10.1.1 (MINOR):

- CONNECTED R6860 TO AUD_IP_PERPH_DET

- PAGE 46: DELETED TEXT NOTE RELATED TO R4691 & R4690 AS IT IS NA TO K84

- PAGE 74: CHANGED C7432 TO 0.001UF AS PER RDAR://6792327

- PAGE 74: CHANGED C7428 TO 0.47UF AS PER RDAR://6792327

BETWEEN CAPS AND CONNECTOR

BETTER EFFICIENCY


- PAGE 94: REPLACED PLASTIC MINI DP CONNECTOR WITH METAL APN 514-0691 PART

ADDED CORRESPONDING NOTES-

- PAGE 4: REMOVED SHORT POGO PIN ALTERNATE- PAGE 4: REVERTING MCP TO EARLIER USE APN 338S0710

J6704 FOR EMI PURPOSES - L6709 & L6710

05/04/2009: RELEASE 12.10.0 (MAJOR):

128S0286

128S0288

PROGRAMMED P/N

FROM FAN STANDOFF

3 UNSTUFFED ON THE TOP

- CHANGED MIN_WIDTH OF CODEC HP OUT NETS.

- PAGE 69: PUT R6961 BEFORE C6955 TO GET RC FILTER. ALSO, FOR NOW,

RDAR://PROBLEM/6752822

128S0286

- UPDATED PAGE BORDERS TO NEW E4 DSIZE STANDARDS

- PAGE 97: ADDED A 1000PF CAP (C9727) ON LCDBKLT_VIN NEAR PIN 1

- PAGE 77: CHANGED C7771 TO 47UF APN 138S0659 TO FIX ETHERNET JITTER ISSUE

- PAGE 72: REPLACED C7240 & C7282 WITH 5.95MM SANYO APN

JITTER ISSUE

RDAR://PROBLEM/6834630- PAGE 60: CHANGED R6003 AND R6004 TO 10 OHMS 5% RESISTOR VALUES

- PAGE 73: REPLACED C7331 & C7345 WITH 5.95MM SANYO APN

ISSUE

- PAGE 70: REMOVED R7050 CHGR_6259_YES COMPONENT AS IT IS NOT NEEDED

CURRENT PER RDAR://PROBLEM/6752822- PAGE 50: CHANGED R5714 TO 0 OHM APN 116S0004 PER

- PAGE 69: REFRESHED J6955 SYMBOL - APN 516S0787

- PAGE 69: REFRESHED J6955 SYMBOL (HALL EFFECT CONNECTOR)

- PAGE 59: ADDED R5922 10 OHMS SERIES R ON VDD SUPPLY TO FIX SMS NOISEZS0916-ZS0918 WITH THINBC APN 870-1820 (2 MM) ONES

- PAGE 9: REPLACED ALL MEDIUM POGO PINS WITH APN 870-1794 (2 MM) AND

- PAGE 4: ADDED NEW ISL PART APN 353S2718 AS AN ALTERNATE TO FIX B4 DONGLE- PAGE 4: REMOVING CHGR_6259_NO BOM OPTION AS ISL 6259 IS NOT POR

06/09/2009: RELEASE 14.1.0 (MAJOR)-

- ADDED R6862 PULL-UP RESISTOR TO PERPH. DETECT CKT.***PAGES SYNCED FROM CASEY HARDY?S AUDIO_MLB SINCE LAST RELEASE 14.0.0***

(APN 138S0654): TO FIX B4 DONGLE ISSUEC9400 & C9481 TO 4.7UF (APN 138S0618) & CHANGED C9480 TO 22UF

- PAGE 94: STUFFED C9485 AND CHANGED IT TO 22UF (APN 138S0654),CHANGEDWITH ISL 6258 (PM_SLP_S3_L DIRECTLY CONNECTS TO ISL 6258 PIN)

WITH XW SHORTS- XW7052 & XW7054

- PAGE 70: DELETED R7051 & R7053 CHGR_6259_YES BOM OPTIONS COMPONENTS

ISSUE

- PAGE 70: REPLACING R7052 & R7054 CHGR_6259_NO BOM OPTION COMPONENTS

4/7/2009 - RELEASE 12.0.0 OK2FAB (RFA):

- PAGE 75: CHANGED C7565 AND C7568 TO CASE_B4_SM PACKAGE FROM

- PAGE 8: DELETED =PP3V3_S3_AUDIO ALIAS AS IT IS NO LONGER APPLICABLE

Z2_MOSI AS THEY CONFLICT WITH FUNC_TEST ATTRIBUTE ON PAGE 7

**PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.5.0***

06/10/2009: RELEASE 14.2.0 (MAJOR)-

- PAGE 77: ADDED 0 OHMS BOM OPTIONS R7782 BETWEEN PIN 4 OF U7750(SKIP PIN) AND POWER RAIL AND R7783 BETWEEN PIN 4 AND GND.R7782 WILL BE NOSTUFF FOR NOW. THIS IS AS PER DAYU TO FIX

- PAGE 9: ADDED ONE MORE EXTRA TALL POGO PIN AS PER EMC RECOMMENDATION

- PAGE 57: CHANGED R5714 TO 113 OHMS APN 114S0125 (KB LED CURRENT TO 8.5MA)

07/17/2009: AGILE EVT OK2FAB RELEASE 15.0.0 (FAB)-

- PAGE 4: DELETED MIKEY_LOAD_DET BOM OPTION FROM THE TABLE UNDER K84_MISC

UPDATED NOTE BELOW THE ALTERNATES PARTS TABLE ACCORDINGLY

- PAGE 4: UPDATED ALTERNATES FOR MINI DP AND USB CONNECTORS WITH PG2

- PAGE 4: ADDED PG2 CONNECTOR APN 514-0704 IN THE MODULE PARTS TABLE FOR

- PAGE 4: DELETED 353S2310 PART FROM THE ALTERNATES BOM TABLE AS ALL

FOR U7870 TO FIX B4 DONGLE ISSUE

CIRCUIT HAS BEEN REMOVED. SO R2143 NEEDS TO BE STUFFED NOW- PAGE 21: DELETED NOSTUFF BOM ATTRIBUTE FROM R2143 AS MIKEY_LOAD_DET

- PAGE 4: ADDED NEW INTERSIL PART APN 353S2718 IN THE MODULE PARTS TABLE

PLASTIC CONNECTORS- APN 514-0706 (MDP) & 514-0705 (USB). AND,

ALTERNATE TABLE (MAKING ALTERNATES AS PRIMARY)

- FINAL PROTO 2 OK2FAB RELEASE- UPDATED PAGE BORDERS TO NEW E4 DSIZE STANDARDS

(P7550)

08/31/2009: RELEASE 16.1.0 (MAJOR)-

- PAGE 53: REPLACED APN 376S0545 WITH 376S0820 @ Q5315 - PER ECO#0000737172

- PAGE 50: REPLACED DUAL Q5032 FET WITH TWO SINGLE Q5032 & Q5033 (APN 376S0612)

- PAGE 97: REPLACED C9717 WITH 1000PF CAP APN 132S0147 AND ADDED PLACEMENT NOTE

4/2/2009: RELEASE: 9.4.0 (MAJOR):- PAGE 72: REPLACED C7252, C7291 & C7292 WITH 5.95MM SANYO APN

- PAGE 97: UPDATED SCHEMATIC NOTE RELATED TO TARGET AND ACTUAL ISET & OVP- PAGE 94: ADDED OMIT BOM OPTION TO J9400 MINI DP CONNECTOR- PAGE 67: ADDED OMIT BOM OPTION TO J6700 AUDIO CONNECTOR- PAGE 46: ADDED OMIT BOM OPTIONS TO J4600 & J4610 USB CONNECTORS- PAGE 9: ADDED OMIT BOM OPTION ON ALL THE POGO PINS

AND ADDED TO MODULE PARTS TABLE AS THEY ARE NOW POR I/O CONNECTORS

CONNECTORS AS THEY ARE NO LONGER POR FOR DVT- PAGE 4: REMOVED 998S APN FROM THE ALTERNATES TABLE PERTAINING TO I/O

LIMITS) APN 353S2811 AS AN ALTERNATE FOR APN 353S1832

870-1820) IN MODULE PARTS TABLE

- PAGE 52: CHANGED R5200, R5201, R5260 & R5261 TO 2K APN 116S0073

- PAGE 50: CHANGED R5030 TO 63.4 OHMS APN 114S0102 TO INCREASE THE SIL

- PAGE 37: CHANGED C3714 AND C3715 TO 2.2UF APN 138S0642 TO FIX ETHERNET

- PAGE 4: ADDED A TEXT NOTE STATING THAT ADC CAN ONLY WORK IN S0 STATE AS

- PAGE 4: DELETED SANYO 6.00MM OSCON CAPS 128S0248 & 128S0271 FROM THE

- PAGE 4: UPDATED BOM GROUPS TABLE TO REFLECT AFOREMENTIONED CHANGES. NEW

- PAGE 4: ADDED 2 NEW EEES TO ATTACH WITH AFOREMENTIONED NEW 639 BOMS

- PAGE 4: TURNING ON BOM OPTION MCPSMC_DIGITEMP_YES AS POR IS TO CONNECT

870-1886 (IN PLACE OF 870-1698) & 870-1887 (IN PLACE OF- PAGE 4: ADDED LOW NOISE POGO APNS 870-1885 (IN PLACE OF 870-1794),AS THAT’S THE PIN WIDTH

- PAGE 75: CHANGED L7560 TO APN 152S0526 - 0.68UH, 3.5MOHM,16A - AS PER DAYU

- PAGE 72: ADDED MIN_LINE/NECK_WIDTH ATTRIBUTES TO 5V_S3_DRVL, 3V3S5_VBST,- PAGE 54:B CHANGED R5412 TO 118OHM (114S0127)

N-CH FETS FOR ROUTING PURPOSES (SIL ANODE SIGNAL)

Revision History

- PAGE 75: CHANGED R7569 TO 11.3K APN 114S0319 FOR SETTING THE CORRECT OCSET AS PER DAYU

- PAGE 70: REMOVED CHGR_6259_YES/NO BOM ATTRIBUTES AS ISL 6259 IS NOT POR

- PAGE 70: REPLACED U7000 WITH THE NEW INTERSIL SCREENED PARTS APN 353S2811- PAGE 4: DELETED 353S2811 ENTRY FROM THE ALTERNATES TABLE

DEVELOPMENT BOM ONLY HAS XDP CONNECTOR AND LPCPLUS COMPONENTS

085-1076 FOR INITIAL RAMP

- PROD_DEBUG (POST FIRST 5K UNTIL 1 MONTH INTO PRODUCTION) OK2FAB RELEASE

10/12/2009: RELEASE B.0.0 (FAB)-

- PAGE 66: ADDED BOMOPTION OMIT TO RESISTORS R6612, R6617, R6630 & R6633

- PAGE 50: CHANGED R5030 SIL RESISTOR TO 80.6 OHMS APN 114S0112 AS PER ID- PAGE 13: ADDED OMIT TO J1300

ADDED APN 518S0774 FOR XDP CONNECTOR J1300 (TO REPLACE 998-2515)TABLE FOR R6612, R6617, R6630 & R6633

- PAGE 4: ADDED APN 104S0033 (6.8 OHMS, 1/4W) RESISTORS IN MODULE PARTS

K84_DEBUG_PROD BOM GROUP IS TURNED ON- PAGE 4: UPDATED BOM TABLES TO NOT INCLUDE ANY 085 DEVELOPMENT BOMS. AND,

- PAGE 67: CHANGED J6704 TO A THREE PIN CONNECTOR 518S0520

- PAGE 72 : CHANGED C7252, C7291 & C7292 BACK TO ORIGINAL APN 128S0271

- PAGE 4: ADDED LOCKED BOOT ROM APN 341S2488 AND TURNED IT ON IN BOM TABLE- PAGE 4: ADDED NEW SCREENED LCD BKLT CONTROLLER APN 353S2965 IN MODULE

PARTS TABLE- PAGE 97: ADDED OMIT BOM OPTION TO U9700

02/24/2010: RELEASE D.0.0 (FAB) -

Revision HistorySYNC_MASTER=K24_MLB SYNC_DATE=01/19/2009

6 OF 109

B.0.0

051-8568

6 OF 77




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(NEED TO ADD 2 GND TP)

LVDS FUNC_TEST

(NEED 2 TP)

BATT POWER CONN FUNC_TEST

SATA HDD/SIL FUNC_TEST




MIC FUNC_TEST

SPEAKER FUNC_TEST


X16 WIRELESS CONN FUNC_TEST

(NEED 2 TP)

IPD_FLEX_CONN FUNC_TEST

(NEED 2 TP)


(NEED 2 TP)

(NEED 2 TP)

(NEED 2 TP)


(NEED 2 TP)


HALL EFFECT CONNECTOR FUNC_TEST


Functional Test Points

FAN CONNECTORS FUNC_TEST


KEYBOARD CONN FUNC_TEST

SATA ODD CONN FUNC_TEST

POWER NETS FUNC_TEST

DC POWER CONN FUNC_TEST

I12

I15

I16

I226

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SYNC_MASTER=K24_MLB

FUNC TESTSYNC_DATE=02/04/2009

PP3V3_S3_BT_FTRUECONN_PCIE_MINI_D2R_PTRUECONN_PCIE_MINI_D2R_NTRUECONN_PCIE_MINI_R2D_PTRUE

CONN_USB2_BT_NTRUE

TRUE MINI_RESET_CONN_L

Z2_SCLKTRUE

WS_KBD3TRUE

WS_KBD5TRUEWS_KBD6TRUE

WS_KBD4TRUE

WS_KBD1TRUETRUE PP3V42_G3H

PP3V3_S3TRUE

SMBUS_SMC_A_S3_SCLTRUE

SMBUS_SMC_A_S3_SDATRUETRUE PSOC_SCLK

PSOC_MOSITRUE

PICKB_LTRUE

TRUE LED_RETURN_6PP5V_S3_CAMERA_FTRUE

USB_CAMERA_CONN_PTRUE

TRUE PSOC_MISOTRUE Z2_RESET

Z2_KEY_ACT_LTRUETRUE Z2_CLKINTRUE Z2_HOST_INTNTRUE Z2_BOOST_EN

Z2_MISOTRUEZ2_MOSITRUE

TRUE Z2_DEBUG3

PPVOUT_S0_LCDBKLTTRUE

PP18V5_S3TRUETRUE PP3V3_S3_LDO

TRUE MINI_CLKREQ_Q_L

TRUE Z2_CS_L

TRUE PP3V3_S0_LCD_FTRUE PP3V3_LCDVDD_SW_F

PSOC_F_CS_LTRUE

WS_KBD9TRUE

WS_KBD11TRUE

TRUE WS_KBD13WS_KBD14TRUE

SATA_ODD_R2D_PTRUE

SATA_ODD_D2R_C_NTRUE

SYS_LED_ANODE_RTRUE

SATA_ODD_R2D_NTRUE

PP5V_S0_HDD_FLTTRUE

TRUE SATA_HDD_R2D_N

TRUE SATA_HDD_D2R_C_P

TRUE FAN_RT_TACH

SPKRAMP_L_N_OUTTRUETRUE SPKRAMP_L_P_OUT

SPKRAMP_R_N_OUTTRUE

SPKRAMP_SUB_N_OUTTRUETRUE SPKRAMP_SUB_P_OUT

PCIE_CLK100M_MINI_CONN_NTRUEPP3V3_WLANTRUE

LED_RETURN_4TRUE

LED_RETURN_3TRUE

LED_RETURN_1TRUE

LVDS_IG_A_CLK_F_PTRUE

TRUE CONN_PCIE_MINI_R2D_N

PCIE_WAKE_LTRUE

SATA_HDD_D2R_C_NTRUE

SMBUS_SMC_BSA_SCLTRUESMBUS_SMC_BSA_SDATRUE

PP3V42_G3HTRUE

BATT_POS_FTRUETRUE SYS_DETECT_L

TRUE CONN_USB2_BT_PTRUE BI_MIC_SHIELD

FAN_RT_PWMTRUE

BI_MIC_LOTRUE

USB_CAMERA_CONN_NTRUE

PCIE_CLK100M_MINI_CONN_PTRUE

PPVCORE_S0_CPUTRUE

PP1V05_S0TRUETRUE PP1V5_S0

TRUE PP5V_SW_ODD

TRUE PP3V3_LCDVDD_SW_F

LED_RETURN_5TRUE

TRUE SMC_PM_G2_ENPM_SLP_S4_LTRUE

PP4V5_AUDIO_ANALOGTRUE

PPVOUT_S0_LCDBKLTTRUE

TRUE PP3V3_G3_RTCPP3V3_WLANTRUE

TRUE PP5V_S0_HDD_FLT

PP1V2R1V05_ENETTRUETRUE PP3V3_ENET_PHYTRUE PPBUS_G3HTRUE PP3V42_G3H

PP3V3_S5TRUETRUE PP1V1R1V05_S5

TRUE PP3V3_S0

TRUE PP3V3_S3TRUE PP1V5_S3

TRUE PP5V_S3

TRUE PP5VRT_S0

PPVCORE_S0_MCPTRUE

LED_RETURN_2TRUE

SATA_ODD_D2R_C_PTRUESMC_ODD_DETECTTRUE

WS_KBD19TRUE

PP18V5_DCIN_FUSETRUE

TRUE LVDS_IG_A_DATA_P<2>

TRUE LVDS_IG_DDC_CLK

TRUE LVDS_IG_A_CLK_F_N

TRUE SATA_HDD_R2D_P

TRUE PP5V_SW_ODD

TRUE WS_KBD10

TRUE LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_P<0>TRUE

ADAPTER_SENSETRUE

WS_KBD16_NUMTRUE

TRUE PP0V75_S0

TRUE WS_KBD2

WS_KBD15_CAPTRUE

TRUE PP5VRT_S0

TRUE LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_N<1>TRUE

WS_KBD12TRUE

TRUE WS_KBD18

TRUE WS_KBD20

WS_KBD22TRUE

TRUE PP5V_S3_CAMERA_F

TRUE WS_KBD7

TRUE WS_KBD8

TRUE WS_KBD17

WS_KBD21TRUE

TRUE WS_KBD23TRUE WS_KBD_ONOFF_L

TRUE WS_LEFT_SHIFT_KBD

TRUE WS_LEFT_OPTION_KBDWS_CONTROL_KBDTRUE

PP3V3_S5_AVREF_SMCTRUETRUE PP18V5_S3

PP3V3_S3_LDOTRUE

PM_SLP_S3_LTRUE

PP1V8_S0TRUEPP5VLT_S0TRUE

TRUE LVDS_IG_A_DATA_N<0>TRUE LVDS_IG_DDC_DATA

BI_MIC_HITRUE

SPKRAMP_R_P_OUTTRUE

SMC_LID_RTRUE

7 OF 109

B.0.0

051-8568

7 OF 77

30

30 71

30 71

30 71

30 72

30

44 45

44

44

44

44

44

7 8

7 8

39 74

39 74

44 45

44 45

44 45

64 67

7 64

64 72

44 45

44 45

44 45

44 45

44 45

45

44 45

44 45

44 45

7 47 64 67

7 45

7 45

30

44 45

64

7 64

44 45

44

44

44

44

34 71

34 71

34

34 71

7 34

34 71

34 71

43

52

52

52

52

52

30 71

7 30

64 67

64 67

64 67

64 71

30 71

17 30

34 71

39 74

39 74

7 8

54 55

54

30 72 52 53

43

52 53

64 72

30 71

8

8

8

7 34 47

7 64

64 67

36 56 62

21 36 37 62

49

7 47 64 67

21 22 25

7 30

7 34

8

8

8

7 8

8

8

8

7 8

8

8

7 8

8

64 67

34 71

34 36

44

54

18 64 71

18 64

64 71

34 71

7 34 47

44

18 64 71

18 64 71

54

44

8

44

44

7 8

18 64 71

18 64 71

44

44

44

44

7 64

44

44

44

44

44

44

44

44

44

36 37

7 45

7 45

21 32 36 62 66

8

8

18 64 71

18 64

52 53

52

54




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

"S3" RAILS"S0,S0M" RAILS

DIGITAL GROUND

& CPU VTT SENSING RES.)

(BEFORE HIGH SIDE SENSING RES.)

(MCP VCORE AFTER SENSE RES)

(AFTER HIGH SIDE CPU VCORE

43 mA (A01)

127 mA (A01)

127 mA (A01)

127 mA (A01)

206 mA (A01)

57 mA (A01)

206 mA (A01)

206 mA (A01)

(CPU VCORE PWR)

"ENET" RAILS

"S5" RAILS

PEX & SATA AVDD/DVDD aliases

"G3H" RAILS

=PP3V3_S3_TPAD_LDO

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP5V_S3

=PP3V3_S3_BT

=PP3V3_S3_SMS

=PP3V3_S3_WLAN

=PP3V3_S3_MCP_GPIO

=PP3V3_S3_TPAD

VOLTAGE=5V

=PP3V3_S3_VREFMRGN

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_PDCISENS

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_FET

=PP5V_S3_EXTUSB

=PP1V05_S0_VMON

=PP1V05_S0_MCP_PLL_UF_R

MIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

GND

VOLTAGE=0V

=PP3V42_G3H_HALL

MAKE_BASE=TRUEVOLTAGE=3.42VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPP3V42_G3H

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_TPAD

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_ONEWIRE

=PPVIN_S5_SMCVREF

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA

=PP5V_S3_TPAD

=PP5V_S3_DEBUG_ISNS

=PP3V3_S0_IMVP

=PP3V3_S0_FAN_RT

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_XDP

=PP1V5_S3_MEMRESET

=PP1V5_S3_MEM_A

=PP1V5_S3_P1V5S0FET

=PPBUS_G3H

=PP1V05_S0_MCP_HDMI_VDD

PP1V5_S0

VOLTAGE=1.5VMAKE_BASE=TRUE

MIN_LINE_WIDTH=1.5 mmMIN_NECK_WIDTH=0.25 mm

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V8_S0_AUDIO

PP1V8_S0

MAKE_BASE=TRUEVOLTAGE=1.8VMIN_NECK_WIDTH=0.10MMMIN_LINE_WIDTH=0.10MM

=PP1V5_S0_MCP_PLL_VLDO

=PP1V5_S0_MEM_MCP

=PP3V3_S0_CPUVTTISNS

=PPSPD_S0_MEM_B

=PPVCORE_S0_CPU_VSENSE

=PPVCORE_S0_CPU

=PP3V3_S0_MCPTHMSNS

=PPVTT_S0_VTTCLAMP

=PP0V75_S0_MEM_VTT_A

=PP0V75_S0_MEM_VTT_B

=PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_SATA_DVDD0

=PPCPUVTT_S0_REG

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0_MCP_PLL_UF


MIN_LINE_WIDTH=0.6 mm

=PP3V3_ENET_PHY

PP1V2R1V05_ENET


MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM

=PP1V05_ENET_FET

=PP1V5_S0_FET

=PP5V_S0_FAN_RT

=PPMCPCORE_S0_REG

=PP1V8R1V5_S0_MCP_MEM

=PPVCORE_S0_CPU_REG

=PP3V3_S5_MCP_GPIO

=PPVTT_S3_DDR_BUF

=PP1V05_ENET_MCP_PLL_MAC

=PP1V5_S0_CPU

=PP1V5_S0_VMON

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_LCD

=PP3V3_S5_MEMRESET

=PP3V3_S5_P1V05ENETFET

=PP3V3_S5_P1V05S5


=PP3V3_S5_P3V3S0FET

=PP3V3_S5_P3V3S3FET

=PP3V3_S5_REG PP3V3_S5

MAKE_BASE=TRUEVOLTAGE=3.3V


=PP3V42_G3H_REG

=PP3V3_ENET_FET

PP1V05_S0_MCP_SATA_AVDDMAKE_BASE=TRUE

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_SATA_AVDD0

MAKE_BASE=TRUE

PP1V05_S0_MCP_PEX_AVDD

=PP0V75_S0_REG

=PP1V05_S5_REG

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_ENET_P1V05ENETFET

=PP18V5_G3H_CHGR

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.3 MMVOLTAGE=12.6V

PPBUS_G3H_CPU_ISNS

=PP3V3_S0_MCP

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm

VOLTAGE=0.75V

PP0V75_S0

MAKE_BASE=TRUE

=PPCPUVCORE_VTT_ISNS

=PPVIN_S0_CPUVTTS0

=PPVIN_S5_CPU_IMVP

VOLTAGE=0.75VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

PPVTT_S3_DDR_BUF

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_DPCONN

=PP3V3_S0_VMON

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_P1V8S0


=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_MCP_DAC_UF

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_SATA_DVDD

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB


PP1V05_S0


=PP1V05_S0_CPU

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.3 MMVOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

=PPBUS_G3HRS5

=PPVIN_S3_5VS3

=PPBUS_S0_LCDBKLT

=PPVIN_S0_MCPCORE

=PPVIN_S5_3V3S5

=PPCPUVCORE_VTT_ISNS_R

=PP18V5_DCIN_CONN

=PPVIN_S5_1V5S30V75S0


MAKE_BASE=TRUE

PPBUS_G3H

MIN_NECK_WIDTH=0.25 mmVOLTAGE=12.6V

=PP5VRT_S0_FET

=PP5V_S0_HDD

=PP5V_S0_DP_AUX_MUX

=PP5V_S0_VMON

=PP5V_S0_MCPREG

=PP5VLT_S0_FET

=PP5V_S0_CPU_IMVP

PP5VRT_S0

MIN_NECK_WIDTH=0.20 MMVOLTAGE=5VMAKE_BASE=TRUE


=PPVCORE_S0_MCP_VSENSE

=PP3V3_S0_PWRCTL

=PP3V3_S0_ODD


PP3V3_S0MIN_LINE_WIDTH=0.30MMMIN_NECK_WIDTH=0.20MM

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_AUDIO

=PP3V3_S0_LCD

PP5VLT_S0

MAKE_BASE=TRUEVOLTAGE=5VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MM

=PPSPD_S0_MEM_A

PPVCORE_S0_MCP

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE


VOLTAGE=1.05V


=PP5V_S3_P5VLTS0FET

=PP3V3_S0_FET

=PP5V_S0_LPCPLUS


=PP3V3_S0_MCPDDRISNS

=PP5V_S3_SYSLED


MIN_NECK_WIDTH=0.3 MMMIN_LINE_WIDTH=0.6 MMPP18V5_G3H

=PP3V42_G3H_CHGR

=PP3V3_S5_SMC

=PP3V42_G3H_RTC_D

=PP3V3_S0_SMC

=PP5V_S3_1V5S30V75S0

=PP5V_S3_AUDIO

=PP5V_S3_MCPDDRFET

=PP5V_S3_AUDIO_AMP

=PP5V_S3_CAMERA

=PP5V_S3_DEBUG_ADC_DVDD

=PP5V_S3_ODD

=PP5V_S3_DEBUG_ADC_AVDD

=PP5V_S3_VTTCLAMP

=PP5V_S3_REG

=PP1V05_ENET_PHY

=PP1V05_ENET_MCP_RMGT

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MMPP3V3_ENET_PHY

MAKE_BASE=TRUE


MAKE_BASE=TRUE

PP1V1R1V05_S5



=PP1V8_S0_REG

=PP3V3_S5_ROM

=PP3V3_S5_MCP

=PP3V3_S5_MCPPWRGD

=PP3V3_S5_PWRCTL

=PP1V05_S0_MCP_PEX_DVDD0


=PP5V_S0_CPUVTTS0

=PP1V5_S3_REG

VOLTAGE=1.5VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1.5 mmPP1V5_S3

MAKE_BASE=TRUE

=PP1V5_S3_MEM_B

MIN_LINE_WIDTH=0.5 mmPP3V3_S3


MAKE_BASE=TRUEVOLTAGE=3.3V

SYNC_MASTER=K24_MLB

Power AliasesSYNC_DATE=02/04/2009

=PP1V05_S0_MCP_SATA_DVDD1



=PP5V_S3_P5VRTS0FET

8 OF 109

B.0.0

051-8568

8 OF 77

30

28

27

30

39

54

7

38

44

35

54

37

62

39

45

47

58

43

39

13

29

27

63

55

61

62

24 18

7

24 18

49

7

61

28

41

40

12 11

42

63

27

28

23 8 17

61 23

23 8 20

60

31

23 18

7 32

63

43

59

23 16

63

58

20 18

57 26

23

12 11

62

39

66

64

29

32

61

32

63

63

56 7

54

32

23

17

20

23

57

61

23 22

32

55 23 22 21

7

41

60

58

42

66

62

39

61

23

23 21

21 19 18

24

23 8

23

23 8

23 22

23 22 14

7

13 12 11 10

7

46

40

56

68

59

56

41

54

57

7

63

34

65

62

59

63

58

7

40

62

34

7

24

53 52 49

64

7

7 39

63

63

38

61

41

37

55

37 36

25

37

57

51 49

63

35

64

47

34

63

47

63

56

31

23 18

7

7

61

48 38

23 22

25

62

20

20

17

17

60

57 7

28

7

44

26

7

21

30

39

57

52

OUTIN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

BELOW CPU

LVDS ALIASES

UNUSED EXPRESS CARD LANE

UNUSED FIREWIRE LANE

FSB MHZ

ETHERNET ALIASES

CPU FSB FREQUENCY STRAPS

USB ALIASES

SMC ALIASES

ABOVE CPU

PCI-E ALIASES DACS ALIASES SO-DIMM ALIASESUNUSED ADDRESS PINS

UNUSED GPU LANESUNUSED CRT & TV-OUT INTERFACE

BSEL<2..0>

(400)

(166)200

333

133

100

(RSVD)

266

1 1 01 0 11 0 00 1 1

0 0 0

0 1 0

1 1 1

0 0 1

UNUSED USB PORTS

DP HOTPLUG PULL-DOWN

LEFT OF CPU

(870-1794 )

BELOW MCP

LVDS CONNECTOR HOLE

HEATSINK STANDOFFS

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

FAN STANDOFF

EMI IO MEDIUM POGO PINS

(870-1698 )EMI TALL POGO PINS

EMI THINBC POGO PINS (870-1820 )

MLB MOUNTING (TO TOPCASE) SCREW HOLES

LAN ALIASES

MISC MCP79 ALIASES

CPU VCORE ALIASES

Z0911OMIT

3P2R2P7

Z0901STDOFF-4.5OD.98H-1.1-3.48-TH

Z0904STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902STDOFF-4.5OD.98H-1.1-3.48-TH

Z0903STDOFF-4.5OD.98H-1.1-3.48-TH

14 10 69

R0940

402

20K1/16W5%

MF-LF

Z0910OMIT

3P2R2P7

ZS09052.0DIA-TALL-EMI-MLB-M97-M98

OMIT

SM


OMIT

SM

ZS0904OMIT

2.0DIA-TALL-EMI-MLB-M97-M98SM

ZS0907OMIT

2.0DIA-TALL-EMI-MLB-M97-M98SM

Z09073P2R2P7

OMIT

Z0906OMIT

3P2R2P7

R0931

402MF-LF

5%1/16W

22

ZS0910OMIT

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0900OMIT

2.0DIA-MED-EMI-MLB-K84SM

ZS0901OMIT


ZS09022.0DIA-MED-EMI-MLB-K84

OMIT

SM

ZS0903OMIT

SM2.0DIA-MED-EMI-MLB-K84

ZS0908OMIT


ZS0909OMIT

SM2.0DIA-MED-EMI-MLB-K84

ZS09112.0DIA-MED-EMI-MLB-K84

OMIT

SM

Z0913OMIT

3P2R2P7

Z0905OMIT

3P2R2P7

ZS0916

OMIT

2.0DIA-MLB-THIN-BC-K84SM

ZS0915

OMIT

SM

2.0DIA-TALL-EMI-MLB-M97-M98ZS0914


OMIT

SM


OMIT

SM


SM

OMIT

ZS0917

OMIT


ZS0918

OMIT


ZS0919OMIT

SM


ZS0920NOSTUFF

SM

2.0DIA-MLB-THIN-BC-K84

SYNC_DATE=02/04/2009

SIGNAL ALIASSYNC_MASTER=K24_MLB

USB_MINI_N

USB_CARDREADER_P

USB_EXTC_N

USB_EXCARD_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_FW_P

MAKE_BASE=TRUE

FW_PME_L

MAKE_BASE=TRUE

PCIE_FW_R2D_C_P

GMUX_JTAG_TCK_L

CPU_PECI_MCP

MAKE_BASE=TRUENO_TEST=TRUE

NC_LVDS_IG_A_DATA_N3

PM_SLP_RMGT_L

MAKE_BASE=TRUE

RTL8211_VDDREGMAKE_BASE=TRUE

=P3V3ENET_EN

=PP3V3_ENET_PHY_VDDREG

TP_RTL8211_CLK125

LVDS_IG_A_DATA_P<3>

RTL8211_CLK125

MAKE_BASE=TRUE

MEM_B_A<15>

=P1V05ENET_EN

=RTL8211_REGOUT

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

MAKE_BASE=TRUECPU_BSEL<0:2>

USB_EXTD_P

USB_EXCARD_P

USB_MINI_P

USB_EXTD_N

TP_USB_CARDREADER_PMAKE_BASE=TRUE

TP_USB_IR_PMAKE_BASE=TRUE

TP_USB_CARDREADER_NMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_USB_EXTC_N

CRT_IG_VSYNC

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_CLK_P

NO_TEST=TRUE

NC_LVDS_IG_B_CLK_NMAKE_BASE=TRUE

CARDREADER_RESET

GMUX_JTAG_TMS

MCP_GPIO_4MAKE_BASE=TRUE

MIKEY_MIC_LOAD_DET

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<3:0>

TP_USB_EXTC_PMAKE_BASE=TRUE

TP_USB_EXTD_NMAKE_BASE=TRUE

NC_CRT_IG_VSYNCMAKE_BASE=TRUENO_TEST=TRUE

LVDS_IG_B_DATA_N<3:0>

TP_USB_EXCARD_PMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_USB_EXCARD_N

TP_USB_MINI_NMAKE_BASE=TRUE

TP_PEG_CLK100M_PMAKE_BASE=TRUE

=PEG_D2R_P<15:0>

=PEG_D2R_N<15:0>

=PEG_R2D_C_N<15:0>

=PEG_R2D_C_P<15:0>

MAKE_BASE=TRUE

TP_FW_PME_L

IMVP6_NTC TP_IMVP6_NTCMAKE_BASE=TRUE


NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_YNO_TEST=TRUE


NC_CRT_IG_B_COMP_PB

IMVP6_VR_TT

TP_SMC_SYS_KBDLEDMAKE_BASE=TRUE

SMC_SYS_KBDLED

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_P

USB_EXTC_P

NC_LVDS_IG_A_DATA_P3NO_TEST=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15:0>NO_TEST=TRUE

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

TP_PCIE_EXCARD_D2R_PMAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_CLK_PMAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNCNO_TEST=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15:0>

PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_C_N

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_FW_R2D_C_N

MAKE_BASE=TRUE

TP_PCIE_FW_PRSNT_L

MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_P

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

PCIE_EXCARD_R2D_C_P

PEG_CLK100M_N

=MCP_MII_RXER

NC_LVDS_IG_B_DATA_P<3:0>NO_TEST=TRUE MAKE_BASE=TRUE

=MCP_MII_COL

PEG_CLK100M_P


NC_PEG_D2R_P<15:0>TP_MEM_A_A15

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_MEM_B_A15MCP_TV_DAC_VREF

MCP_CLK27M_XTALOUT

MEM_A_A<15>


NC_MCP_CLK27M_XTALIN


NC_MCP_TV_DAC_VREF

MCP_TV_DAC_RSETMAKE_BASE=TRUENO_TEST=TRUE

NC_MCP_TV_DAC_RSET

TP_PEG_PRSNT_LMAKE_BASE=TRUE

MCP_CLK27M_XTALIN

=MCP_MII_CRS

NC_PEG_D2R_N<15:0>NO_TEST=TRUE MAKE_BASE=TRUE

PEG_PRSNT_L

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDI

MAKE_BASE=TRUE

TP_GMUX_JTAG_TCK_L

=DVI_HPD_GMUX_INT

PCIE_CLK100M_FW_N

HPLUG_DET2MAKE_BASE=TRUE

=MCP_BSEL<0:2>

CRT_IG_G_Y_Y

CRT_IG_R_C_PR

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_P

PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_N

MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_N

TP_PCIE_EXCARD_D2R_NMAKE_BASE=TRUE

PCIE_FW_PRSNT_L

TP_IMVP6_VR_TTMAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_N<3:0>NO_TEST=TRUE MAKE_BASE=TRUE

TP_GMUX_JTAG_TDOMAKE_BASE=TRUE

TP_GMUX_JTAG_TMSMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_USB_MINI_P

=RTL8211_ENSWREG

FW_CLKREQ_L

TP_PEG_CLK100M_NMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_P

TP_FW_CLKREQ_LMAKE_BASE=TRUE

TP_USB_IR_NMAKE_BASE=TRUE

USB_IR_N

USB_CARDREADER_N

USB_IR_P

MAKE_BASE=TRUE

TP_USB_EXTD_P

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_N

GMUX_JTAG_TDI

GMUX_JTAG_TDO

MAKE_BASE=TRUE

TP_PCIE_CLK100M_EXCARD_P

TP_EXCARD_CLKREQ_L

TP_PCIE_EXCARD_PRSNT_L

TP_PCIE_EXCARD_R2D_C_N

TP_PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

MCP_MII_PD

MF-LF

47K

402

5%1/16W

MAKE_BASE=TRUE

K84_DYN_CARDREADER_RESET

R0930

MF-LF

5%1/16W

402

R0950470

9 OF 109

B.0.0

051-8568

9 OF 77

1

1

1

1

1

1

2

1

2

1

1 11 1

11

1

2

1

1 1 1 1

1 1 1

1

1

1

1111

11

1

1

1

2

20

20 72

20

20

17

19

17 71

17

17

14

21 32

31

31

18

28

32

31

18

18

20

20

20

20

18

18

18

17

19

21

18

18

19

18

17

17

17

17

58 20

17

17

17

17

17 71

17 71

17 71

17

17

17

18

18

17

18

18

27 18

18

18

17

18

17

18

18

17

17

17

31

17

20 72

20 72

20 72

58

36

53

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

OUT

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

BI

BI

BI

BI

TEST7

TEST6

DSTBP1*

DINV1*

D31*

D30*

D25*

D11*

D12*

D13*

D14*

DSTBP0*

DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0* D32*

D1*

D2*

D5*

D16*

D20*

D21*

D22*

D23*

D24*

D26*

D27*

D28*

D29*

DSTBN1*

GTLREF

TEST3

TEST4

TEST5

BSEL0

BSEL1

BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*

DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*

DSTBP3*

DINV3*

COMP0

COMP1

COMP2

COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3

DATA GRP 2

MISC

DATA GRP 0

DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3*

A4*

A14*

A16*

REQ0*

REQ1*

REQ2*

REQ3*

REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*

A21*

A22*

A23*

A24*

A26*

A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5

RSVD6

RSVD7

RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (all 4 resistors):

CPU JTAG Support

SYNC FROM T18

CHANGE CPU FROM SOCKET TO BGA SYMBOL

R1000

1%

1/16W

54.9

MF-LF402

R1002685%

1/16W

MF-LF402

R1005

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.

402

1K

MF-LF

1%

1/16W

R1006

PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.

1%

MF-LF

2.0K

1/16W

402 R1023

Place within 12.7mm of CPU

54.91%

1/16W

MF-LF

402

R1022


27.41%

1/16W

MF-LF

402

R1021


402

MF-LF

1/16W

1%

54.9

R1020


27.41%

1/16W

MF-LF

402

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 58 69

14 69

14 69

14 69

58

13 14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

9 69

9 69

9 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

13 69

13 69

13 69

13 69

13 69

13 69

10 13 69

13 25

14 37 69

42 75

14 37 69

14 69

13 14 69

14 69

14 69

14 69

14 69

10 13 69

10 13 69

10 13 69

10 13 69

42 75

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

R1010

NO STUFF

5%

MF-LF

1/16W

0

402R1011

NO STUFF

1/16W5%

MF-LF

1K

402

R100154.9

402MF-LF

1%1/16W

R109054.9

1/16W

MF-LF

1%

402

R1091

1%

MF-LF

1/16W

54.9

402

R1093

1%

MF-LF

1/16W

54.9

402

14 69

14 69

14 69

14 69

R1094

1%

MF-LF

1/16W

649

402

R1012

402

MF-LF

1K5%1/16W

NO STUFF

C1014

PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

NO STUFF

X5R

0.1uF10%

16V

402

U1000

FCBGA

PENRYN

OMIT

R1092

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

54.9

1/16W

MF-LF

1%

402

U1000

FCBGA

OMIT

PENRYN


CPU FSB

XDP_TDI

XDP_TDO

XDP_TMS

FSB_D_L<0>

FSB_D_L<1>

FSB_D_L<2>

FSB_D_L<3>

FSB_D_L<4>

FSB_D_L<5>

FSB_D_L<6>

FSB_D_L<7>

FSB_D_L<8>

FSB_D_L<9>

FSB_D_L<10>

FSB_D_L<11>

FSB_D_L<12>

FSB_D_L<13>

FSB_D_L<14>

FSB_D_L<15>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

FSB_DINV_L<0>

FSB_D_L<16>

FSB_D_L<17>

FSB_D_L<18>

FSB_D_L<19>

FSB_D_L<20>

FSB_D_L<21>

FSB_D_L<22>

FSB_D_L<23>

FSB_D_L<24>

FSB_D_L<25>

FSB_D_L<26>

FSB_D_L<27>

FSB_D_L<28>

FSB_D_L<29>

FSB_D_L<30>

FSB_D_L<31>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DINV_L<1>

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

TP_CPU_TEST5

TP_CPU_TEST3

TP_CPU_TEST6

TP_CPU_TEST7

FSB_CPUSLP_L

CPU_PSI_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_DINV_L<3>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

XDP_TRST_L

XDP_TCK

CPU_GTLREF

CPU_TEST1

CPU_TEST2

CPU_TEST4

CPU_COMP<1>

CPU_COMP<0>

CPU_COMP<2>

CPU_COMP<3>

=PP1V05_S0_CPU

FSB_LOCK_L

CPU_INIT_L

FSB_A_L<3>

FSB_A_L<4>

FSB_A_L<14>

FSB_A_L<16>

FSB_REQ_L<0>

FSB_REQ_L<1>

FSB_REQ_L<2>

FSB_REQ_L<3>

FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD_B2

TP_CPU_RSVD_V3

TP_CPU_RSVD_T2

TP_CPU_RSVD_N5

TP_CPU_RSVD_M4

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

CPU_THERMD_N

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

TP_CPU_RSVD_F6

TP_CPU_RSVD_D2

TP_CPU_RSVD_D22

TP_CPU_RSVD_D3

FSB_A_L<17>

FSB_A_L<18>

FSB_A_L<19>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<22>

FSB_A_L<23>

FSB_A_L<24>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<27>

FSB_A_L<28>

FSB_A_L<29>

FSB_A_L<30>

FSB_A_L<31>

FSB_A_L<32>

FSB_A_L<33>

FSB_A_L<34>

FSB_A_L<35>

FSB_ADSTB_L<1>

CPU_A20M_L

CPU_FERR_L

CPU_IGNNE_L

CPU_STPCLK_L

CPU_SMI_L

CPU_NMI

CPU_INTR

FSB_A_L<6>

10 OF 109

B.0.0

051-8568

10 OF 77

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1

2

1

2

1 2

1 2

1 2

1 2

1

2

2

1

C3

A26

M26

N24

N25

T25

P23

J23

H22

F26

K22

H26

H25

G24

K24

E23

E25

R23

P26

E22 Y22

F24

E26

G25

N22

L23

M24

L22

M23

P25

P22

T24

R24

L25

L26

AD26

C24

AF26

AF1

B22

B23

C21

AB24

V24

V26

V23

T22

U25

U23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

Y26

AA26

U22

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

AC22

AD23

AF22

AC23

AE25

AF24

AC20

R26

U26

AA1

Y1

E5

B5

D24

D6

D7

AE6

K25

F23

G22

J26

H23

J24

D25

C23

1 2

H4

B3

A6

K5

J4

L5

P4

R1

K3

H2

K2

J3

L1

A21

A22

C7

A24

D21

C20

AB6

AB5

AB3

AA6

AC5

AC1

AC2

AC4

AD1

AD3

AD4

E4

G6

G2

G3

F4

F3

C1

D20

F1

E1

F21

H5

E2

B2

V3

T2

N5

M4

A3

B4

C6

D5

A5

V1

AA3

AB2

AA4

W3

V4

U2

Y4

W5

R3

U5

Y2

M1

L2

P2

G5

W6

U4

Y5

U1

R4

T3

W2

J1

N2

M3

P5

T5

B25

C4

H1

N3

P1

L4

F6

D2

D22

D3

10 13 69

10 13 69

10 13 69

10 13 69

10 13 69

26 69

69

69

69

69

8 11 12 13

69

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VCC

VCCP

VCCA

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4




36

BRANCH

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

30.4 A (SV LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

SYNC FROM T18

CHANGE CPU FROM SOCKET TO BGA SYMBOL

(BR1#)

44 A (SV Design Target)

23 A (LV Design Target)

(CPU IO POWER 1.05V)

(CPU INTERNAL PLL POWER 1.5V)

(CPU CORE POWER)

130 mA

41 A (SV HFM)

(Socket-P KEY)

4500 mA (before VCC stable)

2500 mA (after VCC stable)

58 69

58 69

58 69

58 69

58 69

58 69

R1101

PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.

1/16W1%

100

402MF-LF

58 69

58 69

58 69

U1000

PENRYN

OMIT

FCBGA

U1000

OMIT

PENRYN

FCBGA

R1100

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.

1/16W1%

100

402

MF-LF


CPU Power & Ground

=PPVCORE_S0_CPU

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PPVCORE_S0_CPU

CPU_VCCSENSE_P

CPU_VCCSENSE_N

11 OF 109

B.0.0

051-8568

11 OF 77

1

2

AD15

AD17

AD18

C15

A7

A10

A13

A17

B15

B17

B20

C17

C18

D9

D12

D14

D18

E7

E9

E10

E12

E13

E15

E17

E18

E20

F7

F9

F10

F12

F14

F15

F18

F20

AA7

AA9

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB9

AC10

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AB7

AC7

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

AD14

AE9

AE10

AE12

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

G21

V6

J6

K6

M6

J21

K21

M21

N21

N6

R21

R6

T21

T6

V21

W21

B26

C26

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AF7

AE7

A9

A12

A15

B14

B18

C9

C10

C12

C13

D10

D15

D17

B12

B10

B7

A18

F17

B9

A20

N23

N26

B1

P3

E19

B19

A23

D16

D11

D4

D1

C25

C22

C2

T4

B8

A4

A8

A11

A14

A16

A19

AF2

B11

B13

B16

B21

B24

C5

C8

C11

C14

C16

C19

D8

D13

D26

E3

E6

E11

E14

E16

E24

F5

F8

F11

F13

F16

F19

F2

F22

F25

G4

G1

G23

G26

H3

H6

H21

H24

J2

J5

J22

J25

K1

K4

K23

K26

L3

L21

L24

M2

M5

M22

M25

N1

N4

P6

P21

P24

R2

R5

R22

R25

T1

T23

T26

U3

U6

U21

U24

V2

V5

V22

V25

W1

W4

W23

W26

Y3

Y6

Y21

Y24

AA2

AA5

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

AE19

AE23

AE26

A2

AF6

AF8

AF11

AF13

AF16

AF19

AF21

A25

AF25

E8

E21

L6

D23

D19

B6

1

2

8 11 12

8 12

8 10 12 13

8 11 12




36

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PAGE TITLE

C

A

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Apple Inc.

PAGE


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C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (C1240-C1243):

VCCA (CPU AVdd) DECOUPLING

VCCP (CPU I/O) DECOUPLING

4X 330UF. 20X 22UF 0805

CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)REMOVE C1244 & C1245

CPU VCore HF and Bulk Decoupling

REMOVE NO STUFF CAPS C1220 TO C1231SYNC FROM T18

1x 330uF, 6x 0.1uF 0402

1x 10uF, 1x 0.01uF

PLACEMENT_NOTE (C1200-C1219):

C1206

CRITICAL

CERM-X5R

6.3V20%22UF

Place inside socket cavity on secondary side.

805

C1260330UF20%2.5VTANTCASE-B2-SM

CRITICAL

C1204

CRITICAL


CERM-X5R

6.3V20%22UF

805

C1216

CRITICAL


CERM-X5R6.3V20%22UF

805

C1214

CRITICAL


CERM-X5R6.3V20%

805

22UF

C1208

CRITICAL


CERM-X5R

6.3V20%22UF

805

C1203

CRITICAL


805

22UF20%6.3V

CERM-X5R

C1207

CRITICAL


805

22UF20%6.3V

CERM-X5R

C1202

CRITICAL


CERM-X5R

6.3V20%

805

22UF

C1201

CRITICAL


805

22UF20%6.3V

CERM-X5R

C1213

CRITICAL


22UF

805

20%6.3VCERM-X5R

C1212

CRITICAL


CERM-X5R6.3V20%

805

22UF

C1211

CERM-X5R6.3V20%

805

22UF

CRITICAL


C1219

CRITICAL


805

22UF20%6.3VCERM-X5R

C1200

CRITICAL


CERM-X5R

6.3V20%22UF

805

C1210

CRITICAL

6.3V


CERM-X5R

20%

805

22UF

C1261

10V

402

0.1UF20%

CERM

C1205

CRITICAL


805

22UF20%6.3V

CERM-X5R

C1209

CRITICAL


805

22UF20%6.3V

CERM-X5R

C1215

CRITICAL


805

22UF20%6.3VCERM-X5R

C1217

CRITICAL


805

22UF20%6.3VCERM-X5R

C1262

10V

402

0.1UF

CERM

20%

C1263

402CERM

10V

0.1UF20%

C1264

10V

402

0.1UF

CERM

20%

C12650.1UF

CERM

10V

402

20%

C1266

10V

402

0.1UF

CERM

20%

C1218

CRITICAL


CERM-X5R6.3V20%22UF

805

C1251

16V

PLACEMENT_NOTE=Place C1281 near CPU pin B26.

10%

402CERM

0.01UF

C1250

6.3V

10uF

603X5R

20%

C1240

Place on secondary side.

470UF-4MOHM

CRITICALNOSTUFF

20%

D2T-SM

POLY-TANT

2.0V

C1241470UF-4MOHM

CRITICAL


D2T-SM

20%

2.0V

POLY-TANT

C1242

CRITICAL

470UF-4MOHM


D2T-SM

POLY-TANT

20%

2.0V

C1243


CRITICAL

D2T-SM

470UF-4MOHM

2.0V

20%

POLY-TANT

CPU DecouplingSYNC_DATE=03/30/2009SYNC_MASTER=K24_MLB

=PPVCORE_S0_CPU

=PP1V5_S0_CPU

=PP1V05_S0_CPU

12 OF 109

B.0.0

051-8568

12 OF 77

2

1

1

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

3 2

1

3 2

1

3 2

1

3 2

1

8 11

8 11

8 10 11 13

IN

BI

BI

BI

BI

OUT

IN

BI

IN

IN

IN

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

OUT

IN

IN

OUT

OUT

OUT

OUT

NC

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

ON ODD-NUMBERED SIDE OF J1300

OBSFN_A0

OBSDATA_B0

OBSFN_B0

OBSDATA_A3

OBSDATA_C0

TDI

OBSDATA_C1

PWRGD/HOOK0

TCK0

OBSFN_C0

Please avoid any obstructions

OBSFN_D0

SCL

HOOK1

TMS

OBSFN_D1

XDP_PRESENT#

ITPCLK/HOOK4

OBSDATA_D1

OBSFN_B1

OBSDATA_A0

OBSFN_A1

OBSDATA_A2

Direction of XDP module

VCC_OBS_CD

OBSDATA_D0

HOOK2

TDO

DBR#/HOOK7

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

TRSTn

OBSDATA_C2

NOTE: This is not the standard XDP pinout.

Mini-XDP Connector

USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.

OBSDATA_D3

OBSDATA_D2

OBSDATA_C3

MCP79-specific pinout

RESET#/HOOK6

ITPCLK#/HOOK5

HOOK3

VCC_OBS_AB

OBSDATA_B2

OBSDATA_B1

OBSDATA_A1

OBSFN_C1

OBSDATA_B3

TCK1

SDA

518S0774(998-2515)

10 14 69

R1399

1/16W

5%

XDP

MF-LF

402

1K

21 39 72

21 39 72

R1315

402

1/16W

54.9

MF-LF

1%

XDP

C1300

X5R

10%

16V

0.1uF

402

XDP

C1301

402

16V

XDP

0.1uF10%

X5R

10 69

10 69

10 69

10 14 69

R1303

1/16W

5%

1K

XDP

MF-LF

402

PLACEMENT_NOTE=Place close to CPU to minimize stub.

10 69

10 69

10 69

10 69

21

21

21

19 72

19 72

19 72

19 72

19 72

19 72

19 72

19 72

21

14 69

14 69

10 69

10 69

10 69

10 25

19

10 69

21

J1300

OMITCRITICAL

F-ST-SMDF40C-60DS-0.4V

eXtended Debug Port(MiniXDP)SYNC_MASTER=K24_MLB SYNC_DATE=02/25/2009

CPU_PWRGD

FSB_CPURST_L

XDP_DBRESET_L

XDP_TDO

XDP_TRST_L

XDP_TMS

XDP_TDI

JTAG_MCP_TDO

MCP_DEBUG<0>

MCP_DEBUG<3>

JTAG_MCP_TDI

MCP_DEBUG<4>

JTAG_MCP_TCK

PM_LATRIGGER_L

XDP_PWRGD

TP_XDP_OBSDATA_B3

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B0

XDP_BPM_L<1>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<4>

XDP_BPM_L<5>

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<5>

FSB_CLK_ITP_P

XDP_CPURST_L

FSB_CLK_ITP_N

JTAG_MCP_TMS

TP_XDP_OBSFN_B0

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

XDP_TCK

TP_XDP_OBSFN_B1

XDP_BPM_L<0>

=PP1V05_S0_CPU

JTAG_MCP_TRST_L

=PP3V3_S0_XDP

MCP_DEBUG<1>

MCP_DEBUG<2>

TP_XDP_OBSDATA_B2

XDP_OBS20

13 OF 109

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051-8568

13 OF 77

1 2

1

2

2

1

2

1

1 2

3

1

7

5

11

9

13

17

15

23

19

21

25

27

29

33

31

35

39

37

41

43

45

47

49

51

53

59

57

55

38

40

36

32

34

30

28

26

24

22

16

18

20

10

14

12

6

8

2

4

56

58

60

54

52

50

48

46

44

42

69

8 10 11 12

8

IN

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28#

CPU_A29#

CPU_A30#

CPU_A31#

CPU_A32#

CPU_A22#

CPU_A23#

CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2#

CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6#

CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15#

CPU_A16#

CPU_A19#

CPU_A17#

CPU_A18#

CPU_A20#

CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT#

CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0#

CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4#

CPU_D5#

CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17#

CPU_D18#

CPU_D16#

CPU_D19#

CPU_D20#

CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24#

CPU_D25#

CPU_D26#

CPU_D27#

CPU_D28#

CPU_D29#

CPU_D30#

CPU_D31#

CPU_D32#

CPU_D33#

CPU_D34#

CPU_D35#

CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39#

CPU_D40#

CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44#

CPU_D45#

CPU_D46#

CPU_D47#

CPU_D52#

CPU_D53#

CPU_D54#

CPU_D55#

CPU_D56#

CPU_D57#

CPU_D58#

CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P

BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK#

CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD

+V_PLL_MCLK

+V_PLL_FSB

+V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY#

CPU_DRDY#

CPU_REQ1#

FSB




36

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C

A

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Apple Inc.

PAGE


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C

345678

D

B

8 7 5 4 2 1Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

270 mA (A01) 206 mA

15 mA

29 mA

20 mA

(MCP_BSEL<0>)

(MCP_BSEL<1>)

(MCP_BSEL<2>)

Loop-back clock for delay matching.

9

9

9

10 69

10 13 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

13 69

13 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 69

10 13 69

10 69

10 69

10 69

10 69

10 58 69

9

10 37 69

10 37 69

10 69

10 69

R1436

MF-LF

402

1%

1/16W

49.9

R143149.9

MF-LF

402

1%

1/16W

R1430

1/16W

1%

402

MF-LF

49.9

R1435

MF-LF

402

1%

1/16W

49.9

R1422

MF-LF

1/16W

5%

402

1K

NO STUFF

R1421

1/16W

5%

MF-LF

402

NO STUFF

1K

R1420

1/16W

NO STUFF

MF-LF

402

5%

1K

R1415

5%

62

MF-LF

402

1/16W

R1410

1%

54.9

MF-LF

402

1/16W

R1440

5%

MF-LF

402

1/16W

150

NO STUFF

U1400

BGA

(1 OF 11)

MCP79-TOPO-B

OMIT

R1416

5%

62

MF-LF

402

1/16W

SYNC_MASTER=K24_MLB

MCP CPU InterfaceSYNC_DATE=04/06/2009

PM_THRMTRIP_L

FSB_D_L<13>

MCP_BCLK_VML_COMP_GND

FSB_DPWR_L

CPU_DPSLP_L

FSB_D_L<38>

FSB_D_L<43>

FSB_D_L<45>

CPU_DPRSTP_L

CPU_STPCLK_L

FSB_CPUSLP_L

FSB_CPURST_L

CPU_PWRGD

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_A20M_L

FSB_CLK_MCP_P

FSB_CLK_MCP_N

FSB_CLK_ITP_N

FSB_CLK_ITP_P

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_DEFER_L

FSB_BPRI_L

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<44>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<15>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

MCP_CPU_COMP_GND

MCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_VDD

FSB_RS_L<2>

FSB_RS_L<1>

CPU_PROCHOT_L

CPU_PECI_MCP

FSB_TRDY_L

FSB_LOCK_L

FSB_HITM_L

FSB_HIT_L

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_ADSTB_L<1>

FSB_ADSTB_L<0>

FSB_A_L<35>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_DINV_L<3>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<2>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<1>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

=PP1V05_S0_MCP_FSBPP1V05_S0_MCP_PLL_FSB

FSB_D_L<14>

FSB_D_L<7>

FSB_A_L<10>

FSB_A_L<25>

FSB_A_L<34>

FSB_A_L<33>

FSB_DBSY_L

FSB_DRDY_L

FSB_BNR_L

FSB_RS_L<0>

CPU_FERR_L

FSB_BREQ0_L

FSB_ADS_L

FSB_BREQ1_L

=PP1V05_S0_MCP_FSB

=MCP_BSEL<2>

=MCP_BSEL<0>

=MCP_BSEL<1>

14 OF 109

B.0.0

051-8568

14 OF 77

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

AE40

AD43

AK42

AL32

AC35

AD42

AL37

AJ38

AJ36

AR39

H39

J40

K41

AL34

AN37

AJ34

AL38

AL35

AN36

AJ35

AJ37

AC33

AC39

J41

R41

T41

T42

T39

R42

AM32

AB41

AM40

AM43

AE41

AJ41

F41

AC42

D42

AJ40

G41

AH43

T40

W39

V35

V41

W37

U40

N35

N37

L36

M39

AE38

M41

AC34

AE34

AB35

AE35

AC37

AE37

AG39

AG37

AE33

AG35

AG38

AG34

AG33

AN38

AL39

AL33

AJ33

AN35

AN34

AE36

AC38

AC43

AB42

AD40

AH40

AG43

E41

AM42

Y43

W42

W41

Y40

Y39

V42

Y41

P42

Y42

U41

T43

AA37

W33

W35

W34

AA36

AA34

AA35

AA38

U38

U36

U35

U33

U34

W38

R33

U37

N34

N33

R34

R35

P35

R37

R39

R38

L37

L39

N36

L38

N38

J39

J38

J37

N40

M40

H40

K42

H41

L41

H43

H42

M43

AA41

AA40

G42

AL43

AL42

AL41

AK41

AF41

AG41

AF42

AH41

H38

AM33

AN33

AG42

AN32

N41

P41

M42

L42

AK35

AH39

AH42

AM39

AC41

AG27

AH27

AG28

AH28

AF35

F42

AD39

AD41

AA33

1

2

69

69

69

69

69

69

8 14 22 23 23

69

8 14 22 23

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1

MCKE0A_0

MODT0A_1

MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8

MA0_7

MA0_9

MA0_10

MA0_11

MA0_13

MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P

MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2

MDQM0_1

MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4

MDQ0_3

MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9

MDQ0_8

MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15

MDQ0_14

MDQ0_13

MDQ0_12

MDQ0_16

MDQ0_21

MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25

MDQ0_24

MDQ0_23

MDQ0_22

MDQ0_26

MDQ0_29

MDQ0_28

MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35

MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40

MDQ0_39

MDQ0_42

MDQ0_47

MDQ0_46

MDQ0_43

MDQ0_45

MDQ0_44

MDQ0_51

MDQ0_50

MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55

MDQ0_54

MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61

MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

MEMORYCONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60

MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56

MDQ1_55

MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51

MDQ1_50

MDQ1_48

MDQ1_47

MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42

MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36

MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31

MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26

MDQ1_25

MDQ1_24

MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11

MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6

MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4

MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N

MDQS1_0_P

MDQS1_0_N

MRAS1#

MCAS1#

MWE1#

MBA1_2

MBA1_1

MBA1_0

MA1_14

MA1_13

MA1_12

MA1_11

MA1_10

MA1_9

MA1_8

MA1_7

MA1_6

MA1_5

MA1_4

MA1_3

MA1_2

MA1_1

MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1#

MCS1A_0#

MCLK1A_0_N

MODT1A_1

MODT1A_0

MCKE1A_0

MCKE1A_1

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

U1400

(2 OF 11)

OMIT

MCP79-TOPO-B

BGA

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

27 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

U1400

(3 OF 11)

OMIT

MCP79-TOPO-B

BGA

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

28 70

MCP Memory InterfaceSYNC_DATE=04/06/2009SYNC_MASTER=K24_MLB

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

TP_MEM_B_CLK2N

TP_MEM_B_CLK2P

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

15 OF 109

B.0.0

051-8568

15 OF 77

AU23

AT23

AP15

AV15

AR18

AT15

BC20

BB20

AY24

AV33

BA24

AW33

AR19

AT19

AU19

AV19

AN21

AR21

AP21

AR22

AU21

AV21

AN19

AW21

AU15

AN23

AR23

AP23

AW17

AP19

AR17

AP17

AV17

AU39

AT39

AT35

AU29

AU35

AU30

AW25

AP13

AV25

AR13

AW8

AW7

AR9

AR8

AL11

AL10

AW29

AV35

AR34

AN27

AN13

AP35

AN5

AR10

AU5

AR35

AR38

AV38

AW38

AR37

AV39

AT37

AU37

AW39

AV31

AT31

AU31

AR33

AV37

AW37

AN31

AP31

AR31

AN29

AV27

AV29

AP27

AR27

AP29

AR29

AR25

AT27

AU27

AP25

AU25

AR26

AR11

AT11

AU13

AW13

AR14

AU9

AV13

AV11

AV9

AU11

AY5

AU7

AU8

AW6

AW9

AP11

AN10

AR5

AU6

AW5

AV5

AR6

AR7

AV6

AN7

AN6

AP9

AN9

AL7

AL6

AL9

AL8 AT4

AV3

AR4

AT3

AR3

AV2

AU2

BB3

AU3

AY4

AY3

BC3

BA3

AW4

AW3

BB2

BB5

BA5

BB4

BC8

BA8

BC4

BA7

BB12

BB10

BA9

AW12

BB8

BA12

AY12

BB9

BC32

AW32

BA32

AY36

BA35

AW36

BB32

BA34

AY35

BC36

BA38

BA36

AY40

BB36

BA39

AY39

AV41

AV42

AW40

BB40

BA40

BC40

AT40

AW41

AW42

AU40

AT41

AU41

AN40

AP41

AR41

BA2

AY7

AP42

AT5

BA11

BB34

AR42

AY43

BB38

AY8

AT2

AY1

AY2

AT1

BA6

BB6

BA10

BB33

AY11

BB37

BA33

BA43

BA37

AY42

AT42

AT43

AW16

BA15

BA16

BB29

BB18

BB17

BA29

BA14

AW28

BC28

BA17

BB28

AY28

BA28

AY27

BA27

BA26

BB26

BA25

BB25

BA18

BA42

BB22

BB42

BA19

BA22

BB14

BB16

AY19

BB13

AY15

BB30

AY31

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55

GND56

GND57

GND58

GND60

GND59

GND61

GND62

GND63

GND64

GND52

GND53

GND54

GND51

GND49

GND50

GND48

GND47

GND46

GND44

GND45

GND43

GND42

GND41

GND39

GND40

GND38

GND37

GND36

GND35

GND33

GND34

GND32

GND31

GND30

GND28

GND29

GND27

GND26

GND25

GND24

GND18

GND19

GND17

GND16

GND15

GND13

GND14

GND10

GND12

GND11

GND8

GND9

GND7

GND6

GND5

GND2

GND3

GND4

GND1

MEM_COMP_VDD

MEM_COMP_GND

MODT0B_0

MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0#

MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE

+V_VPLL

+VDD_MEM1

+VDD_MEM2

+VDD_MEM3

+VDD_MEM4

+VDD_MEM5

+VDD_MEM6

+VDD_MEM7

+VDD_MEM8

+VDD_MEM9

+VDD_MEM10

+VDD_MEM11

+VDD_MEM14

+VDD_MEM15

+VDD_MEM16

+VDD_MEM17

+VDD_MEM18

+VDD_MEM19

+VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23

+VDD_MEM24

+VDD_MEM25

+VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31

+VDD_MEM32

+VDD_MEM33

+VDD_MEM34

+VDD_MEM38

+VDD_MEM39

+VDD_MEM40

+VDD_MEM41

+VDD_MEM43

+VDD_MEM44

+VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22

GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

87 mA (A01)

39 mATP or NC for DDR2.

19 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

12 mA

17 mA

4771 mA (A01, DDR3)

R1610

MF-LF

402

1/16W

40.21%

R161140.2

1/16W

1%

402

MF-LF

U1400

BGA

OMIT

MCP79-TOPO-B

(4 OF 11)

29

SYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009

MCP Memory Misc

TP_MEM_B_CKE<3>

TP_MEM_B_CKE<2>

TP_MEM_B_CS_L<2>

MCP_MEM_RESET_L

=PP1V8R1V5_S0_MCP_MEMMCP_MEM_COMP_GND

TP_MEM_A_CLK4N

TP_MEM_A_CLK3P

TP_MEM_A_ODT<2>

TP_MEM_A_ODT<3>

TP_MEM_A_CKE<2>

TP_MEM_A_CKE<3>

TP_MEM_A_CLK5P

TP_MEM_A_CLK5N

TP_MEM_A_CLK4P

TP_MEM_A_CLK3N

TP_MEM_A_CS_L<2>

TP_MEM_A_CS_L<3>

PP1V05_S0_MCP_PLL_CORE

TP_MEM_B_CLK5P

TP_MEM_B_CLK5N

TP_MEM_B_CLK4P

TP_MEM_B_CLK4N

TP_MEM_B_CLK3P

TP_MEM_B_CLK3N

TP_MEM_B_CS_L<3>

TP_MEM_B_ODT<2>

TP_MEM_B_ODT<3>


MCP_MEM_COMP_VDD

16 OF 109

B.0.0

051-8568

16 OF 77

1

2

1

2

BA41

BA23

BA20

AY23

BB41

BA13

BC16

AY20

AY16

BA31

BA30

BC13

AY32

T33

T34

T35

T37

T7

T38

T9

U18

U20

U22

AK11

T24

T26

T20

R5

T18

R43

R40

R36

P40

P7

P4

P37

P34

N8

P33

N39

M9

M7

M6

M38

M5

K7

H31

G32

D34

F24

BC9

AY9

BC21

F28

AK7

AM28

AH35

AG24

AF24

AD22

AE20

AA39

AB7

AB22

V34

W5

V10

T6

T10

AP12

G30

P10

AA22

AN41

AM41

AN17

AN15

AN25

AV23

BB21

AU17

AR15

AU34

BB24

BA21

BC24

AU33

T27

U27

T28

AM17

AM19

AM21

AM23

AM25

AM27

AM29

AN16

BC29

AN20

AN24

AN22

AP20

AP24

AV16

AR16

AR20

AR24

AP22

AW15

AP18

AU16

AN18

AU24

AU20

AT21

AV24

AU22

AW27

BC17

AV20

AU18

AY25

AY26

AW19

BC25

AL30

AM31

AW24

U28

AP16

AT17

AY29

AM15

AY18

AY17

AP30

AT25

AR36

AU10

8 16 23 70

23 8 16 23

70

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7

+AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N

PE0_TX15_P

PE0_TX13_N

PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N

PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N

PE0_TX6_P

PE0_TX4_N

PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N

PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P

PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_PPED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16

PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17

PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18

PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

57 mA (A01, DVDD0 & 1)

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

84 mA (A01)

Int PU

206 mA (A01, AVDD0 & 1)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

Int PU (S5)

U1400

BGA

OMIT

(5 OF 11)

MCP79-TOPO-B

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

30 71

30 71

9

9

7 30

9 71

9 71

9

9

30

30

9

9

30 71

30 71

9 71

9 71

9

9

9

9

30 71

30 71

9

9

9

R1710

PLACEMENT_NOTE=Place within 12.7mm of U1400

NO STUFF

1/16W

1%

MF-LF

402

2.37K

25

9

9

9


MCP PCIe InterfacesSYNC_MASTER=K24_MLB

PCIE_MINI_PRSNT_L

FW_CLKREQ_L

TP_PE4_CLKREQ_L

TP_PE4_PRSNT_L

PCIE_FW_PRSNT_L

CARDREADER_RESET

GMUX_JTAG_TDO

PCIE_WAKE_L

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

TP_PCIE_PE4_D2RP

TP_PCIE_PE4_D2RN

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R_N


GMUX_JTAG_TCK_L

AUD_IP_PERIPHERAL_DET

EXCARD_CLKREQ_L PCIE_CLK100M_EXCARD_P

=PEG_D2R_N<1>

=PEG_D2R_P<1>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_P<5>

=PEG_D2R_P<3>

=PEG_D2R_N<7>

=PEG_D2R_N<6>

=PEG_D2R_P<7>

=PEG_D2R_N<5>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

=PEG_D2R_P<10>

=PEG_D2R_P<9>

=PEG_D2R_P<8>

=PEG_D2R_N<10>

=PEG_D2R_N<12>

=PEG_D2R_N<11>

=PEG_D2R_P<13>

=PEG_D2R_P<11>

=PEG_D2R_P<12>

=PEG_D2R_N<15>

=PEG_D2R_N<14>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_N<13>

PEG_PRSNT_L

MCP_PEX_CLK_COMP

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_N<1>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<2>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<6>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<6>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<10>

=PEG_R2D_C_N<10>

=PEG_R2D_C_P<12>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<14>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_N<15>

PCIE_CLK100M_MINI_P

PEG_CLK100M_P

PEG_CLK100M_N

PCIE_CLK100M_FW_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE4N




PCIE_MINI_R2D_C_P

PCIE_RESET_L


PCIE_FW_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_R2D_CP

TP_PCIE_PE4_R2D_CN

=PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2>

=PEG_D2R_N<0>

PP1V05_S0_MCP_PLL_PEX

=PEG_D2R_N<2>

=PEG_D2R_P<0>




MINI_CLKREQ_L

PCIE_EXCARD_PRSNT_L

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<8>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<11>

17 OF 109

B.0.0

051-8568

17 OF 77

F7

F6

AD12

N12

T12

P13

N13

M13

W12

V12

AC12

U12

R12

P12

M12

AB12

AA12

Y12

T16

U19

T19

U16

W18

W17

W16

V19

U17

W19

T17

E7

E6

E4

G5

D9

C6

B6

B7

A8

A7

C8

B8

M14

K11

D8

K14

L14

N14

H13

J13

F13

J10

F11

J11

D11

E11

G11

M1

M3

M2

L3

M4

K3

K2

L4

J3

J2

J1

H2

H1

H4

G3

H3

F4

F3

F2

E1

E2

D1

D2

B2

B3

C1

A3

A4

D4

B4

C4

C5

A11

G7

H7

E9

J9

H9

F9

G9

F17

K9

C9

P9

N7

N5

N6

N4

N11

L7

N9

L6

N10

L8

J5

L11

L9

J4

L10

D3

J7

H5

J6

E5

C3

F5

E3

D7

C7

C10

E8

G13M15

B10

D5

L16

L18

M16

M18

M17

M19

1

2

8

53

71

23

8

8

8

IN

BI

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P

HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P

HDMI_TXD0_N/ML0_LANE2_N





HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET

RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P

DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET

HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC

RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P

IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P

IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P

IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P

IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N

IFPB_TXD7_P

IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36

MII_COL/GPIO_20/MSMB_DATA

MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44

TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1

+3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)

103 mA

103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable:

Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1

0MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This

avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort

DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

DP_IG_DDC_CLK

TP_DP_IG_AUX_CHP/N

TMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N

=MCP_HDMI_TXD_P/N<0>

MCP Signal

=MCP_HDMI_DDC_CLK



=MCP_HDMI_DDC_DATA

TMDS_IG_HPD=MCP_HDMI_HPD

DP_IG_AUX_CH_P/N

8 mA

8 mA

16 mA (A01)

95 mA (A01)

LVDS: Power +VDD_IFPx at 1.8V


TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

DP_IG_AUX_CH_P/N

DP_IG_HPD

DP_IG_DDC_DATA

DP_IG_ML_P/N<0>

Interface Mode

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting. IFP interface can

level-shifters.

NOTE: 20K pull-down required on DP_HPD_DET.

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

(See below)

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are low

by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal

23

31 73

32 73

31 73

31 73

31 73

31 73

31 73

31 73

31 73

9

9

67 68

64

68

65

65

65

65

65

65

65

65

65 71

65 71

9

65

24 71

24 71

9

9

9

9

9

R181049.9

402

MF-LF

1/16W

1%

R1811

1%

402

49.9

MF-LF

1/16W

65

9

9

9

9

9

U1400

OMIT

MCP79-TOPO-B

BGA

(6 OF 11)

R1850

MF-LF

5%

1/16W

402

10K

R1861

MF-LF

1/16W

100K5%

402

R1860100K

1/16W

5%

MF-LF

402

38

R1820

1/16W

MF-LF

402

47K5%

31 73

64 71

64 71

7 64 71

7 64 71

7 64 71

31 73

7 64 71

7 64 71

7 64 71

9

9

9

9

9

9

9

31 73

9

9

9

9

9

7 64

7 64

65

65

24 71

31 73

24 71

31 73

31 73

31 73

MCP Ethernet & GraphicsSYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009

=DVI_HPD_GMUX_INT

LVDS_IG_BKL_PWM

MCP_CLK27M_XTALOUT

TP_MCP_RGB_DAC_RSET

TP_MCP_RGB_DAC_VREF

LPCPLUS_GPIO


=PP3V3_S5_MCP_GPIO


=PP3V3_S0_MCP_GPIO


ENET_TXD<0>

ENET_TXD<1>

ENET_TXD<2>

ENET_TXD<3>

ENET_CLK125M_TXCLK

ENET_TX_CTRL

MCP_MII_VREF

CRT_IG_VSYNC

CRT_IG_HSYNC

CRT_IG_B_COMP_PB

=MCP_MII_CRS

=MCP_MII_COL

=MCP_MII_RXER

TP_ENET_PWRDWN_L

ENET_MDC

ENET_RESET_L

ENET_RXD<1>

ENET_RXD<2>

ENET_CLK125M_RXCLK

ENET_RX_CTRL

ENET_RXD<3>

TP_ENET_INTR_L

ENET_RXD<0>

MCP_TV_DAC_RSET

MCP_IFPAB_VPROBE

MCP_IFPAB_RSET

=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_CLK_N

LVDS_IG_B_CLK_P

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_CLK_P

CRT_IG_G_Y_Y

CRT_IG_R_C_PR

TP_MCP_RGB_VSYNC

TP_MCP_RGB_HSYNC

TP_MCP_RGB_BLUE

TP_MCP_RGB_GREEN

TP_MCP_RGB_RED

MCP_DDC_CLK0

MCP_DDC_DATA0

MCP_CLK25M_BUF0_R

ENET_MDIO

=MCP_HDMI_HPD

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

MCP_TV_DAC_VREF

LVDS_IG_DDC_CLK

LVDS_IG_DDC_DATA

MCP_CLK27M_XTALIN

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXC_P

LVDS_IG_BKL_ON

LVDS_IG_PANEL_PWR

MCP_MII_COMP_VDD

MCP_MII_COMP_GND

PP3V3_S0_MCP_DAC


PP3V3_S0_MCP_VPLL


PP1V05_ENET_MCP_PLL_MAC

DP_IG_CA_DET

MCP_HDMI_VPROBE

MCP_HDMI_RSET

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_CLK_N

=MCP_HDMI_TXD_P<2>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_N<0>

18 OF 109

B.0.0

051-8568

18 OF 77

1

2

1

2

B15

T23

T25

M29

M28

M26

M27

K32

J32

V23

B27

C27

F40

E37

G39

D38

E16

D35

E35

G35

F35

F33

G33

J33

H33

C31

C35

C38

B30

C30

C39

B38

A35

D43

C43

F31

J31

J30

C21

E23

A31

B31

B39

A39

B40

A40

A41

A36

B36

B35

B32

A32

D33

D32

C32

B34

C33

L31

K31

L29

J29

H29

L30

K29

K30

N30

M30

E31

D31

E32

G31

E36

C23

J22

A24

C22

A23

E24

B23

J23

D21

G23

F23

B26

B22

C36

D36

C37

U23

E28

C26

D24

D25

C25

C24

B24

J24

K24

C34

1

2

1

2

1

2

1

2

8 23

8 20

8 18 23

8 19 21

8 18 23

73

73

24

8 24

24

8 24

23

OUT

OUT

BI

BI

BI

BILPC

PCI

GND

PCI_INTW#

PCI_INTX#

PCI_INTY#

PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0#

LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5

PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10

PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15

PCI_AD16

PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21

PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66

GND67

GND69

GND68

GND70

GND71

GND72

GND74

GND73

GND75

GND76

GND77

GND79

GND78

GND80

GND81

GND84

GND83

GND82

GND85

GND86

GND87

GND89

GND88

GND90

GND91

GND92

GND94

GND93

GND95

GND96

GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR#

PCI_STOP#

PCI_RESET0#

PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105

GND106

GND107

GND109

GND108

GND110

GND111

GND112

GND115

GND114

GND113

GND116

GND117

GND120

GND119

GND118

GND121

GND122

GND123

GND125

GND124

GND126

GND127

GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR#

PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS#

PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0#

PCI_REQ1#/FANRPM2

IN

BI OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Int PU (S5)

Int PU

Int PU

Int PU

Strap for Boot ROM Selection (See HDA_SDOUT)

36 38 72

25 72

36 38 72

36 38 72

36 38 72

36 38 72

U1400

OMIT

MCP79-TOPO-B

(7 OF 11)

BGA

36 38

36 38 25 72

36 38

R1910225%

1/16W

402

MF-LF

PLACEMENT_NOTE=Place close to pin R8

R1989 8.2K

5% 1/16W MF-LF 402

R1991 8.2K

5% 1/16W MF-LF 402

R1990 8.2K

5% 1/16W MF-LF 402

R1994 8.2K

5% 1/16W MF-LF 402

R1992402MF-LF1/16W5%

8.2K

19

R196110K5%

1/16W

402

MF-LF

R19605%

22

402MF-LF1/16W

R1950402

22

MF-LF1/16W5%R1951402

22

MF-LF1/16W5%R1952402MF-LF1/16W5%

22

R1953 22

5% 1/16W MF-LF 402

25

9

19

19

13

13 72

13 72

13 72

13 72

13 72

13 72

13 72

13 72

53

9

9


MCP PCI & LPC

FW_PWR_EN

PCI_REQ1_L

PCI_REQ0_L

MCP_RS232_SOUT_L

LPC_AD<1>

LPC_AD<3>

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

TP_PCI_GNT0_L

TP_PCI_GNT1_L

MCP_RS232_SOUT_L

TP_PCI_C_BE_L<0>

TP_PCI_C_BE_L<1>

TP_PCI_C_BE_L<2>

TP_PCI_C_BE_L<3>

TP_PCI_DEVSEL_L

TP_PCI_FRAME_L

TP_PCI_IRDY_L

TP_PCI_PAR

TP_PCI_SERR_L

TP_PCI_STOP_L

TP_PCI_RESET1_L

TP_PCI_CLK0

LPC_AD_R<0>

LPC_AD_R<1>

LPC_AD_R<2>

LPC_AD_R<3>

LPC_CLK33M_SMC_R

LPC_FRAME_R_L

LPC_RESET_L

LPC_PWRDWN_L

PCI_CLK33M_MCP_R

TP_PCI_CLK1

PCI_CLK33M_MCP

MEM_VTT_EN_R

TP_PCI_PERR_L

TP_PCI_AD<10>

TP_PCI_AD<8>

PCI_REQ1_L

PCI_REQ0_L

TP_PCI_INTY_L

TP_PCI_INTW_L

TP_PCI_AD<31>

TP_PCI_AD<30>

TP_PCI_AD<29>

TP_PCI_AD<28>

TP_PCI_AD<27>

TP_PCI_AD<25>

TP_PCI_AD<22>

TP_PCI_AD<19>

TP_PCI_AD<18>

TP_PCI_AD<17>

TP_PCI_AD<16>

TP_PCI_AD<12>

FW_PWR_EN

AUD_IPHS_SWITCH_EN

MCP_RS232_SIN_L

MCP_DEBUG<0>

MCP_DEBUG<1>

MCP_DEBUG<2>

MCP_DEBUG<3>

MCP_DEBUG<6>

MCP_DEBUG<7>

MCP_RS232_SIN_L

=PP3V3_S0_MCP_GPIO

PM_CLKRUN_L

TP_LPC_DRQ0_L

FW_PME_L

TP_PCI_INTZ_L

GMUX_JTAG_TMS

GMUX_JTAG_TDI

TP_PCI_AD<13>

TP_PCI_AD<11>

PM_LATRIGGER_L

TP_PCI_AD<26>

TP_PCI_AD<24>

TP_PCI_AD<23>

MCP_DEBUG<4>

MCP_DEBUG<5>

TP_PCI_AD<9>

TP_PCI_AD<15>

TP_PCI_AD<20>

LPC_SERIRQ

TP_PCI_TRDY_L

TP_PCI_INTX_L

TP_PCI_AD<21>

TP_PCI_AD<14>

19 OF 109

B.0.0

051-8568

19 OF 77

P2

N3

N2

N1

U24

AE2

AE12

Y3

AE1

AE6

AB3

AC3

AE11

AC4

AE10

AC6

AB2

AA2

AC8

AC7

AC9

AC10

AA5

AA1

AC11

Y5

W3

W6

V3

W7

W4

W8

V2

W11

W9

U2

U6

U7

U26

U39

U8

U4

V16

V17

V18

V22

V20

V24

V26

V27

V33

V28

V37

V4

W20

V7

V40

W22

W24

W36

W43

W40

Y16

Y17

Y18

Y20

Y19

Y22

Y24

Y25

R3

AA11

AA3

W10

AA10

Y4

AA9

Y1

AA7

Y2

R10

R11

R8

R7

R6

R9

AD4

AD2

AD3

AE5

AE9

AD5

AD1

Y27

Y26

AB18

AB20

H34

AB23

AB21

AB24

AB25

AB26

AB28

AB27

AB34

AB37

AB4

AC36

AC22

AB40

AC40

AB33

AD17

AD16

AC5

AD18

AD19

AD20

AD25

AD24

AD26

AD27

AD28

AD34

AD33

T5

U5

U3

AD11

U1

R4

U11

P3

U10

AA6

AB9

U9

T4

T1

T3

T2

V9

1

2

1 2

1 2

1 2

1 2

1 2

1

2

1 2

1 2

1 2

1 2

1 2

19

19 72

19 72

19

72

72

19 72

19 72

19

8 18 21

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158

GND159

GND157

GND156

GND155

GND153

GND154

GND152

GND151

GND150

GND148

GND149

GND147

GND146

GND145

GND143

GND144

GND142

GND141

GND140

GND139

GND136

GND133

GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N

SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N

SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N

SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P

USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26

USB_OC2#/GPIO_27/MGPIO

USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1

+DVDD0_SATA2

+DVDD0_SATA3

+DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1

+AVDD0_SATA2

+AVDD0_SATA3

+AVDD0_SATA4

+AVDD0_SATA5

+AVDD0_SATA6

+AVDD0_SATA7

+AVDD0_SATA8

+AVDD0_SATA9

+AVDD1_SATA1

+AVDD1_SATA2

+AVDD1_SATA3

+AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT

OUT

IN

IN

OUT

OUT

IN

IN

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Geyser Trackpad/Keyboard

AirPort (PCIe Mini-Card)

19 mA (A01)

84 mA (A01)

IR

Camera

External A

External D


43 mA (A01, DVDD0 & 1)

127 mA (A01, AVDD0 & 1)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

External C

External B

Bluetooth

ExpressCard

35 72

35 72

9

9

9

9

64 72

64 72

9 72

9 72

44 72

44 72

30 72

30 72

35 72

35 72

9

9

9

9

35

35

37

R2010

MF-LF

1%

1/16W

402

2.49K

R2060806

MF-LF

1%

1/16W

402

R2053

5%

8.2K

MF-LF

1/16W

402

R2052

402

1/16W

MF-LF

5%

8.2K

R2051

5%

8.2K

1/16W

402

MF-LF

R2050

402

1/16W

MF-LF

5%

8.2K

U1400

OMIT

(8 OF 11)

BGA

MCP79-TOPO-B

34 71

34 71

34 71

34 71

34 71

34 71

34 71

34 71

9 72

9 72

SYNC_MASTER=K24_MLB

MCP SATA & USBSYNC_DATE=04/06/2009

TP_USB_10N

USB_BT_N

USB_IR_P

USB_CAMERA_N

USB_CAMERA_P

USB_EXTD_P

USB_MINI_N

USB_MINI_P

USB_EXTA_N

USB_EXTA_P

TP_SATA_D_D2RP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN

TP_SATA_E_D2RP

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

TP_MCP_SATALED_L

TP_SATA_C_R2D_CP

TP_SATA_C_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CP

TP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_SATA_F_D2RP

MCP_SATA_TERMP

USB_EXTD_N

USB_IR_N

USB_TPAD_P

PP1V05_S0_MCP_PLL_SATA

TP_SATA_C_D2RN

TP_SATA_C_D2RP

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_N

SATA_ODD_D2R_P





=PP3V3_S5_MCP_GPIO

USB_TPAD_N

USB_BT_P

USB_EXTC_OC_L

EXCARD_OC_L

USB_EXTB_OC_L

USB_EXTA_OC_L

USB_EXTB_N

USB_EXTB_P

USB_EXCARD_P

USB_EXCARD_N

TP_USB_10P

USB_EXTC_N

USB_EXTC_P

USB_CARDREADER_P

USB_CARDREADER_N

20 OF 109

B.0.0

051-8568

20 OF 77

1

2

1

2

1

2

1

2

1

2

1

2

AJ2

AJ4

AJ11

AH24

AH20

AH22

AH18

AG40

AG36

AG22

AG26

AG20

AG18

AF40

AF34

AF37

AF33

AF28

AF27

AF22

AF26

AF20

AF18

AF17

AF16

AE39

AD38

AE22

AD37

AD35

A27

L23

K23

G25

F25

J25

H25

E27

L25

K25

D27

G27

F27

J27

L27

K27

J26

B28

A28

D29

D28

C28

C29

AE3

E12

AN3

AN2

AN1

AL4

AK3

AL3

AM4

AJ3

AJ1

AK2

AJ9

AK9

AJ10

AJ7

AD6

AE4

AE24

F29

G29

L21

K21

J21

H21

AJ5

AJ6

AP2

AP3

AM3

AM2

AM1

L28

AE16

AF19

AG16

AG17

AG19

AH19

AJ12

AN11

AK12

AK13

AL12

AM11

AM12

AN12

AL13

AN14

AL14

AM13

AM14

AH17

23

72

71

23

8

8

8

8

8 18

OUT

OUT

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

SLP_S3*

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

SLP_RMGT*

HDA_BITCLK

HDA_SDATA_OUT

THERM_DIODE_N

THERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMP

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_SYNC

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI

JTAG_TDO

RTC_RST*

PS_PWRGD

PWRGD_SB

INTRUDER*

LID*

LLB*

PWRBTN*

RSTBTN*

CPU_DPRSLPVR

SLP_S5*

HDA_SDATA_IN0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

SPI_CS0/GPIO_10

SPI_CLK/GPIO_11

SPI_DI/GPIO_8

SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1

+V_DUAL_HDA2

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

GPIO_1/PWRDN_OK/SPI_CS1

A20GATE

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

+V_PLL_SP_SPREF

+V_PLL_NV_H

MISC

HDA

OUT

IN

IN OUT

IN

IN

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Int PU

automatic recovery.

Connects to SMC for

USER mode: Normal

recovery

SAFE mode: For ROMSIP

(MXM_OK for MXM systems)

Int PU (S5)

Int PU

SPI1 option. Rev B01 will.

NOTE: MCP79 rev A01 does not support

Int PU (S5)

Int PD

Int PD

Int PD

Int PU

1

0

1

0

LPC_FRAME#

0

0

1

1

default, LPC+ debug card pulls

R1961 and R2160 selects SPI0 ROM by

BIOS Boot Select

HDA_SDOUTI/F

SPI1

SPI0

LPC

NOTE: MCP79 does not support FWH, only

Frequency

SPI Frequency Select

1 MHz

NOTE: Straps not provided on this page.

31 MHz

Frequency

BUF_SIO_CLK Frequency

14.31818 MHz

1

1

0

SPI_DO SPI_CLK

0

1

1

0

24 MHz

HDA_SYNC

1

0

LPC ROMs. So Apple designs will

042 MHz

25 MHz

Int PU

Int PU

Int PU (S5)

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

LPC_FRAME# high for SPI1 ROM override.

not use LPC for BootROM override.

PCI

For EMI Reduction on HDA interface

HDA Output Caps


7 mA (A01)

37 mA (A01) 20 mA

17 mA

Int PU (S5)

Int PU (S5)

(MGPIO3)

(MGPIO2)

38 48 72

7 32 36 62 66

7 36 37 62

13 39 72

39 72

13 39 72

39 72

21 59

42 75

21 59

21 59

21 30 32

42 75

9

58 69

36

49 72

49 72

49 72

49 72

49 72

R212149.9K

402

1%

1/16W

MF-LF

R2120

1/16W

402

MF-LF

49.9K1%

R2190

402

1/16W

1%

MF-LF

1K

25 72

36

36

R2170

1/16W

22

5%

402

MF-LFR217122

402

1/16W

5%

MF-LF

R2173

402

1/16W

MF-LF

22

5%

R2163

1/16W

MF-LF

10K5%

402

R2160

402

1/16W

5%

8.2K

MF-LF

R2180

1/16W

402

BOOT_MODE_SAFE

MF-LF

10K5%

R2181

1/16W

BOOT_MODE_USER

MF-LF

402

10K5%

R2172

MF-LF

1/16W

22

5%

402

38

R2110

402

1%

1/16W

MF-LF

49.9

R215010K

5%

MF-LF

1/16W

402

13

13

13

13

13

C2171

CERM

402

5%

50V

10PF

C2173

CERM

402

5%

10PF

50V

C2170

CERM

402

5%

10PF

50V

C2172

CERM

402

5%

10PF

50V

U1400

OMIT

MCP79-TOPO-B

(9 OF 11)

BGA

34

21 53

25 25

32 36 37

21 27 28 36

R2147100K5%

MF-LF

1/16W

402

R2142

MF-LF

402

1/16W

5%

10K

R214110K5%

MF-LF

1/16W

402

R2157

402

1/16W

MF-LF

5%

22K

R2156

402

1/16W

MF-LF

5%

22K

R2155

MF-LF

5%

22K

1/16W

402

R2151100K

1/16W

5%

MF-LF

402

R2154

402

100K5%

MF-LF

1/16W

R2143

5%

MF-LF

10K

1/16W

402

R2140

402

1/16W

MF-LF

5%

10K

37

21 37

25

25

25

25

25

36

36

25

38 48 72

38 48 72

38 72


MCP HDA & MISC

=PP3V3_S0_MCP_GPIO

MCP_GPIO_4

AUD_I2C_INT_L

MEM_EVENT_L

SMC_IG_THROTTLE_L

ARB_DETECT

SPI_CLK_R

RTC_CLK32K_XTALOUT

HDA_SDIN0

SPI_CS0_R_L

SPI_MISO

MCP_HDA_PULLDN_COMP

RTC_RST_L


MCP_SPKR

=PP3V3_S0_MCP

PM_SLP_S4_L

PM_SLP_S3_L

AUD_I2C_INT_L

HDA_SYNC_R

TP_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

SMC_ADAPTER_EN

SMC_WAKE_SCI_L

MEM_EVENT_L

ODD_PWR_EN_L

HDA_RST_R_L

HDA_SYNC

SM_INTRUDER_L

PM_RSMRST_L

JTAG_MCP_TRST_L

MCP_TEST_MODE_EN

JTAG_MCP_TMS

MCP_VID<1>

MCP_VID<2>

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SDOUT_R

HDA_SYNC_R

PP3V3_G3_RTC

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

TP_MCP_KBDRSTIN_L

PM_SYSRST_DEBOUNCE_L

MCP_THMDIODE_N

SMBUS_MCP_0_CLK

SPI_MOSI_R

PM_CLK32K_SUSCLK_R

JTAG_MCP_TCK

MCP_CLK25M_XTALIN

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

PP1V05_S0_MCP_PLL_NV

TP_SB_A20GATE

PM_SLP_RMGT_L

MCP_VID<1>

SMC_RUNTIME_SCI_L

=SPI_CS1_R_L_USE_MLB

HDA_BIT_CLK_R

HDA_SDOUT_R

PM_BATLOW_L

SMBUS_MCP_0_DATA

MCP_VID<2>

AP_PWR_EN

SMBUS_MCP_1_DATA

JTAG_MCP_TDO

JTAG_MCP_TDI

MCP_PS_PWRGD

PM_PWRBTN_L

TP_MCP_LID_L

SMBUS_MCP_1_CLK

MCP_THMDIODE_P

MCP_VID<0>

MCP_CPUVDD_EN

PM_DPRSLPVR

MCP_VID<0>

MCP_CPU_VLD

=PP3V3_S3_MCP_GPIO

AP_PWR_EN

MCP_GPIO_4


ARB_DETECT

TP_MCP_BUF_SIO_CLK

SMC_IG_THROTTLE_L

21 OF 109

B.0.0

051-8568

21 OF 77

1

2

1

2

1

2

1 2

1 2

1 2

1

2

1

2

1

2

1

2

1 2

1

2

1

2

2

1

2

1

2

1

2

1

J15

G17

K17

J17

E15

F15

C11

B11

K15

A15

J14

M21

M20

L20

C18

C12

D12

A12

B12

C19

L13

L22

K22

AE7

D17

K19

L19

C13

L15

A19

B16

B19

J18

A16

G19

J19

C17

E19

F19

C20

E20

D20

B20

M25

M24

C16

D16

M22

H17

G15

G21

F21

M23

C14

D13

C15

B14

B18

J16

K16

L17

L24

K13

L26

AE17

AE18

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

8 18 19

9 21

21 53

21 27 28 36

21 37

21

72

8 21 23

8 22 23

21 72

21 72

21 59

21 59

21 72

21 72

21 72

21 72

7 22 25

23

21 72

21 72

21 59

8

21 30 32

9 21

8 21 23

21

GND

GND161

GND165

GND166

GND164

GND163

GND162

GND167

GND168

GND171

GND170

GND169

GND172

GND173

GND176

GND175

GND174

GND177

GND178

GND181

GND180

GND179

GND182

GND183

GND184

GND187

GND186

GND185

GND188

GND189

GND192

GND191

GND190

GND193

GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206

GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213

GND214

GND217

GND216

GND215

GND218

GND219

GND222

GND221

GND220

GND223

GND224

GND225

GND228

GND227

GND226

GND229

GND230

GND233

GND232

GND231

GND234

GND235

GND238

GND237

GND236

GND239

GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331

GND332

GND330

GND329

GND328

GND326

GND327

GND325

GND324

GND323

GND321

GND322

GND320

GND319

GND318

GND316

GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305

GND306

GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285

GND286

GND284

GND283

GND282

GND280

GND281

GND279

GND278

GND277

GND275

GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264

GND265

GND266

GND263

GND262

GND259

GND260

GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1

+VDD_CORE2

+VDD_CORE3

+VDD_CORE4

+VDD_CORE5

+VDD_CORE6

+VDD_CORE13

+VDD_CORE14

+VDD_CORE15

+VDD_CORE16

+VDD_CORE17

+VDD_CORE18

+VDD_CORE19

+VDD_CORE21

+VDD_CORE22

+VDD_CORE23

+VDD_CORE24

+VDD_CORE25

+VDD_CORE26

+VDD_CORE27

+VDD_CORE28

+VDD_CORE29

+VDD_CORE30

+VDD_CORE32

+VDD_CORE33

+VDD_CORE34

+VDD_CORE35

+VDD_CORE36

+VDD_CORE37

+VDD_CORE39

+VDD_CORE40

+VDD_CORE41

+VDD_CORE47

+VDD_CORE48

+VDD_CORE49

+VDD_CORE50

+VDD_CORE51

+VDD_CORE52

+VDD_CORE53

+VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55

+VDD_CORE56

+VDD_CORE57

+VDD_CORE58

+VDD_CORE59

+VDD_CORE60

+VDD_CORE61

+VDD_CORE62

+VDD_CORE63

+VDD_CORE64

+VDD_CORE65

+VDD_CORE66

+VDD_CORE67

+VDD_CORE68

+VDD_CORE69

+VDD_CORE70

+VDD_CORE71

+VDD_CORE72

+VDD_CORE73

+VDD_CORE74

+VDD_CORE75

+VDD_CORE76

+VDD_CORE77

+VDD_CORE78

+VDD_CORE79

+VDD_CORE80

+VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1

+3.3V_DUAL2

+3.3V_DUAL3

+3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3

+3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

1182 mA (A01)

450 mA (A01)

266 mA (A01)16 mA

10 uA (G3)


80 uA (S0)

23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)

250 mA

1139 mA

43 mA

105 mA (A01)

U1400

BGA

OMIT

MCP79-TOPO-B

(11 OF 11)

U1400

(10 OF 11)

BGA

MCP79-TOPO-B

OMIT


MCP Power & Ground

=PP3V3_S5_MCP


=PP3V3_S0_MCP

PP3V3_G3_RTC

=PPVCORE_S0_MCP =PP1V05_S0_MCP_FSB

22 OF 109

B.0.0

051-8568

22 OF 77

AH26

AH38

AJ39

AH37

AH34

AH33

AJ8

AK10

AK37

AK34

AK33

AK4

AK40

AL5

AL40

AL36

AM10

AM16

AM22

AM20

AM18

AM24

AM26

AM30

AM37

AM35

AM34

AM38

AM5

AM9

AM7

AM6

AP26

AN28

AN4

AN39

AN30

Y7

AU14

AP14

AU26

AP10

AP28

AP36

AP37

AP34

AP32

AP4

AR28

AW23

AP7

AP40

AR32

AR40

AT13

AR12

AT10

AT29

AT33

AT9

AT7

AT6

AY21

AY22

L12

AP33

AU28

AU12

AU32

AR30

AU4

AU38

AU36

G28

F20

AV36

AV32

AV28

AV4

AV7

AR43

G20

AW11

AW43

AY33

AY30

AV12

AY10

AY34

AY41

AY38

AY37 AH16

Y11

T22

V11

T11

Y6

P11

AY13

AB19

AA4

M11

AN26

AD7

AB16

AB17

Y38

Y35

Y37

Y34

Y33

Y28

M35

M37

M34

M10

L5

L40

L43

AU1

K8

K40

K37

K26

K4

K18

K12

J12

J8

K10

G40

AN8

AW35

H15

H23

H11

G8

G43

G4

G6

G34

AW20

G24

G22

BC12

G16

G14

G12

F8

G10

F32

F16

F12

E29

E33

E25

E21

E17

D6

E13

D37

D30

D26

D22

D19

D23

D18

D15

C2

D10

D14

BC5

AY14

BC33

BC37

BC41

L35

AY6

BA4

BA1

AW31

AV40

AG32

AF23

H27

AD32

AK32

AK31

AJ32

AH32

AE32

AF32

P31

R32

Y21

AA25

AC23

U25

AH12

AG10

AG5

AC16

AC17

AC18

AC19

AC20

AC21

AA17

AC25

AC26

AC27

AC28

AD21

AD23

W27

V25

AA18

AE19

AE23

AE25

AE26

AE27

AE28

AF10

AA19

AF2

AF21

AH23

AF9

AA20

AG11

AG12

AG21

AG23

AG25

Y32

P32

M32

M31

L34

L32

K35

K34

K33

J35

J34

H37

H35

G38

G37

F39

F38

F37

E39

E38

D40

D39

C42

C41

C40

B42

B41

AB32

AL31

W32

V32

U32

T32

N32

J36

E40

AF11

G36

D41

AG3

AG4

AA21

AG6

AG7

AG8

AG9

AH1

AH10

AH11

W26

AH2

AA23

W28

AH25

AH21

AH3

AH4

AH5

AH6

AH7

AH9

AA24

W21

W23

W25

AF12

A20

AD10

Y9

G18

H19

J20

K20

G26

J28

K28

T21

V21

U21

AF25

AC32

AF7

AF4

AF3

AA32

AE21

N31

M33

L33

AA8

AB11

Y10

AD9

AB10

AE8

AC24

AA28

AA27

AA26

AA16

Y23

8 23

8 23

8 21 23

7 21 25

8 23 8 14 23

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)

MCP 1.05V RMGT Power

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

5 mA (A01)

562 mA (A01)

57 mA (A01)

16996 mA (A01, 1.0V)

Apple: 4x 2.2uF 0402 (8.8 uF)

Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

MCP SATA (DVDD) Power

1182 mA (A01)

7 mA (A01)

19 mA (A01)

333 mA (A01)

4771 mA (A01, DDR3)

MCP Core Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Power

MCP Memory Power

MCP FSB (VTT) Power

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

Apple: 5x 2.2uF 0402 (11 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 1.05V AUX Power

5 mA (A01)

MCP 3.3V/1.5V HDA Power

266 mA (A01)

MCP 3.3V AUX/USB Power

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP79 Ethernet VRef

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) MCP 3.3V Ethernet Power

270 mA (A01)

(No IG vs. EG data)

23065 mA (A01, 1.2V)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)


MCP PCIE (DVDD) Power

105 mA (A01) 131 mA (A01)

83 mA (A01)

84 mA (A01)

84 mA (A01)

87 mA (A01)

37 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

206 mA (A01)

127 mA (A01)

43 mA (A01)

450 mA (A01) 19 mA (A01)

C2582

402

20%4.7UF

4V

X5R-1

C2588

402

4V

4.7UF20%

X5R-1

C2584

402

4V20%

4.7UF

X5R-1

C2586

402

20%4.7UF

4V

X5R-1

C2555

CERM402-LF

20%

2.2UF

6.3V

C2502

402

20%4V

4.7UF

X5R-1

C2507

X5R402-1

1UF10%10V

C2506

X5R402-1

1UF10%10V

C2505

X5R402-1

1UF10%10V

C2504

X5R402-1

1UF10%10V

C25110.1UF

CERM

20%

402

10V

C25100.1UF

CERM

20%

402

10V

C25090.1UF

CERM

20%

402

10V

C25080.1UF

CERM

20%

402

10V

C25130.1UF

CERM

20%

402

10V

C25120.1UF

CERM

20%

402

10V

C25362.2UF20%

402-LFCERM

6.3V

C2535

6.3V

2.2UF20%

402-LFCERM

C25342.2UF

6.3V20%

402-LFCERM

C2533

6.3V

2.2UF20%

CERM402-LF

C2532

6.3V20%

402-LFCERM

2.2UF

C2531

20%2.2UF

6.3V

402-LFCERM

C2530

6.3V

2.2UF20%

402-LFCERM

C2517

X5R402-1

1UF10%10V

C2516

X5R402-1

1UF10%10V

C2515

402

20%4V

4.7UF

X5R-1

C2572

CERM

6.3V

2.2UF20%

402-LF

C2571

6.3V

2.2UF20%

402-LFCERM

C2520

402

20%4.7UF

4V

X5R-1

C2570

6.3V

2.2UF20%

402-LFCERM

C2574

6.3V

2.2UF20%

402-LFCERM

C2573

6.3V

2.2UF20%

402-LFCERM

C2576

CERM402-LF

20%2.2UF

6.3V

C2575

6.3V

2.2UF20%

CERM402-LF

C25532.2UF

6.3V20%

402-LFCERM

C2552

6.3V

2.2UF20%

402-LFCERM

C25512.2UF

6.3V20%

402-LFCERM

C2550

6.3V

2.2UF20%

402-LFCERM

C25490.1UF20%

CERM402

10V

C25480.1UF20%

CERM402

10V

C25470.1UF20%

CERM402

10V

C25460.1UF20%

CERM402

10V

C25450.1UF20%

CERM402

10V

C2544

20%

CERM402

10V

0.1UF

C25430.1UF20%

CERM402

10V

C2542

20%

CERM402

10V

0.1UF

C2541

CERM

20%

402

10V

0.1UF

C2540

402

4V

4.7UF20%

X5R-1

C2562

6.3V

2.2UF20%

402-LFCERM

C2564

CERM402-LF

20%2.2UF

6.3V

C2580

402

4V20%

4.7UF

X5R-1

L2570

0603

30-OHM-5A

L257530-OHM-5A

0603

L258230-OHM-1.7A

0402

L258430-OHM-1.7A

0402

L258830-OHM-1.7A

0402

L2586

0402

30-OHM-1.7A

L255530-OHM-1.7A

0402

C25004.7UF

402

20%4V

X5R-1

C2501

20%

402

4V

4.7UF

X5R-1

L258030-OHM-1.7A

0402

C25260.1uF

402

10V20%

CERM

C2525

CERM

20%0.1uF

402

10V

C2560

6.3V

2.2UF20%

402-LFCERM

C2589

CERM

20%

402

10V

0.1UF

C2590

CERM

0.1UF20%

402

10V

C2595

402

4V

4.7UF20%

X5R-1

L259530-OHM-1.7A

0402

R25901.47K

1/16W1%

MF-LF402

C25910.1UF

CERM

20%

402

10V

R2591

MF-LF

1%1/16W

1.47K

402

18

C2521

CERM

20%0.1uF

402

10V

C25180.1uF20%

CERM402

10V

C25190.1uF

CERM

20%

402

10V

C2581

10V

402

0.1UF

CERM

20%

C2583

CERM

20%

402

10V

0.1UF

C2585

20%

CERM

0.1UF

402

10V

C2587

20%

CERM

0.1UF

402

10V

C2596

CERM

20%

0.1UF

402

10V

C2529

CERM

20%0.1uF

402

10V

C2528

402

4V20%

X5R-1

4.7UF

C259210UF

20%

6.3V

X5R

603

C2503

402

20%4V

4.7UF

X5R-1

MCP Standard DecouplingSYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009

=PP1V05_S0_MCP_PEX_DVDD

=PPVCORE_S0_MCP


=PP1V05_S0_MCP_PLL_UFMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_FSB

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM


PP1V05_S0_MCP_PLL_NV

VOLTAGE=1.05V


VOLTAGE=1.05V


PP1V05_S0_MCP_PLL_CORE

VOLTAGE=1.05V

PP1V05_S0_MCP_SATA_AVDD


VOLTAGE=1.05V

PP1V05_S0_MCP_PEX_AVDD


PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MM


VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_SATA


PP1V05_ENET_MCP_PLL_MACMIN_LINE_WIDTH=0.4 MM


=PP1V05_ENET_MCP_PLL_MAC


MCP_MII_VREF

=PP3V3_S0_MCP


=PP3V3_S5_MCP

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_FSB





=PP1V05_S0_MCP_SATA_DVDD

25 OF 109

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051-8568

23 OF 77

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2

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2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

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1

2

1

21

21

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21

21

21

2

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2

1

21

2

1

2

1

2

1

2

1

2

1

2

1

21

1

2

2

1

1

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

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2

1

2

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8

8 22

8 22

8 61 14

17

21

16

8

8

20 20

18 8

8 18 23

8 21 22

8 21

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8

8 14 22

8 16

8 18

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8 18 23

8




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672

REMOVE HDCP ROMSCHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC

SYNC FROM T18REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT

NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)


206 mA (A01) 206 mA (A01)

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)Apple: 1x 2.2uF 0402 (2.2 uF)

16 mA (A01)

95 mA (A01)

190 mA (A01, 1.8V)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: ???

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

C2650

6.3V

2.2UF20%

402-LFCERM

NO STUFF

L265030-OHM-1.7A

0402

NO STUFF

C2620

CERM

10V

20%

0.1UF

NO STUFF

402

R2630

MF-LF

1/16W

1%

1K

402

NO STUFF

C2630

20%

402

CERM

NO STUFF

10V

0.1UF

C2615

X5R-1

402

4V

4.7UF20%

C2640

CERM

4.7UF

6.3V20%

603

L264030-OHM-1.7A

0402

C2641

10V20%

402CERM

0.1uF

C2616

402

20%

CERM

0.1UF

10V

R2651

402

05%

1/16W

MF-LF

R2620

402

1/16W

1%

1K

MF-LF

C2610

CERM

402-LF

20%2.2UF

6.3V

MCP Graphics SupportSYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009


MCP_IFPAB_RSETMCP_HDMI_RSET

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP_VPLL_UF


MCP_HDMI_VPROBE

PP3V3_S0_MCP_VPLL


VOLTAGE=3.3V


MCP_IFPAB_VPROBE

VOLTAGE=3.3V

PP3V3_S0_MCP_DACMIN_LINE_WIDTH=0.4 MM


26 OF 109

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051-8568

24 OF 77

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1

21

2

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1

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1

2

1

2

2

1

8 18

18 71 18 71

8

8

8 18

18 71

18

18 71

18

IN OUT

OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUTIN

NCNC

OUT

OUTIN

OUT

OUT

OUT

IN

IN

OUT

Y

B

A

IN

IN

IN

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACE C2819 CLOSE TO MCP79

RTC Crystal

MCP 25MHz Crystal

Platform Reset Connections

CHANGE RTC COIN CELL TO LDO & SUPERCAP

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before

results in earlier ROMSIP and MCP FSB I/O interface initialization.

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,

SYNC FROM T18CHANGE RESET BUTTOM TO RESET PADS

ALIAS MEM_VTT_EN TO =DDRVTT_EN

REMOVE UNUSED PCIE RESET SIGNALS

CHANGE Y2810 AND U2850 TO SMALLER PARTS

REMOVE R2824 AND NET PCI_CLK33M_SLOT_A

LPC Reset (Unbuffered)

but results in MCP79 ROMSIP sequence happening after CPU powers up.

Reset Button

10K pull-up to 3.3V S0 inside MCP

MCP S0 PWRGD & CPU_VLD

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for

MCPSEQ_MIX is cross between MLB and internal power sequencing, which

PCIE Reset (Unbuffered)

C2810

402

5%50V

CERM

12pF

C2811

402

12pF

5%

50VCERM

R2811

NO STUFF

10M

402

MF-LF

5%1/16W

19 72

R288333

MF-LF

5%

1/16W

402

PLACEMENT_NOTE=Place close to U1400

R2881PLACEMENT_NOTE=Place close to U1400 33

5%

1/16WMF-LF402

R28910

MF-LF402

5%

1/16W

38

36

30

21

21

17

R2826


402

5%1/16W

MF-LF

33

R2825PLACEMENT_NOTE=Place close to U1400

MF-LF

5%1/16W

33

402

19 72

C2815

402CERM50V

12pF

5%

C281612pF

5%50VCERM

402

Y281525.0000M

CRITICAL

SM-3.2X2.5MM

R2816

402

1M

NO STUFF

1/16W

5%

MF-LF

21

21

36 72

R2829


402MF-LF

5%

1/16W

2221 72

68

R2892

5%1/16W

MF-LF

0

402

57 63

R287033

402

5%

1/16WMF-LF

19

38 72

36 72

21

C2899

X5R

10%

1UF

10V

402

NO STUFF

R289933

402

MF-LF

1/16W

5%

R2890NO STUFF

0

MF-LF1/16W

5%

402SILK_PART=SYS RST

R2898

402

5%1/16W

MF-LF

XDP

0

36

10 13

26

R2871

1/16W

5%

0

MF-LF402

Y2810

CRITICAL

7X1.5X1.4-SM

32.768K

R2815

1/16WMF-LF402

5%0

R281005%

1/16WMF-LF402

U2850

SOT665TC7SZ08AFEAPE

21

58

36 62

R2851

402

0

1/16W5%

MF-LF

MCPSEQ_MIX

C2850

402

20%

CERM

0.1UF

MCPSEQ_SMC

10V

R2850

402

0

1/16W

5%

MF-LF


MCPSEQ_SMC

21

R2852

MF-LF

5%1/16W

0

402

MCPSEQ_MIX

R2853

MF-LF

5%1/16W

0

402

MCPSEQ_SMC

21

C2819

6.3V

CERM402

1UF

10%

PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79

R2820

5%

MF-LF1/16W

0

402

SB MiscSYNC_MASTER=K24_MLB SYNC_DATE=02/15/2009

PCIE_RESET_L

MINI_RESET_L

=PP3V42_G3H_RTC_D


PP3V3_G3_RTCMIN_LINE_WIDTH=0.3 mm

RTC_CLK32K_XTALOUT

MAKE_BASE=TRUEMEM_VTT_EN

PCA9557D_RESET_L

LPC_CLK33M_SMC_R

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

MCP_CLK25M_XTALIN

MCP_CLK25M_XTALOUT

SMC_LRESET_L

=PP3V3_S5_MCPPWRGD

VR_PWRGOOD_DELAY

S0_AND_IMVP_PGOOD

ALL_SYS_PWRGD

MCP_CPUVDD_EN

MCP_CPU_VLD

MCP_PS_PWRGD XDP_DBRESET_L PM_SYSRST_DEBOUNCE_L

PM_SYSRST_L

DEBUG_RESET_L

RTC_CLK32K_XTALIN

=DDRVTT_EN

LPC_CLK33M_LPCPLUS

LPC_CLK33M_SMC

PM_CLK32K_SUSCLK

MEM_VTT_EN_R

PM_CLK32K_SUSCLK_R

LPC_RESET_L

BKLT_PLT_RST_L

28 OF 109

B.0.0

051-8568

25 OF 77

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1 2

1

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31

24

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2

1 2

1 2

1 2

2

1

1 2

1

2

1 2

1 2

41

1

2

1

2

3

5

1

4

2

1 2

2

1

1 2

1 2

1 2

2

1

1 28 7 21 22

8

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0

A1

A2

SCL

SDA

P0

P1

P2

P5

P6

P7

P3

P4

THRM

VCC

GNDPAD

NCNC

NC

IN

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI

NC

NC

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1


DAC channel A B A B C

Max DAC code 0x87 0x87 0x87 0x87 0x55

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

Signal aliases required by this page:

- =PPVTT_S3_DDR_BUF

- =PP3V3_S5_VREFMRGN

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SDA

Min DAC code 0x00 0x00 0x00 0x00 0x00

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SCL

(per DAC LSB)

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

Place close to U1000.AD26

Place close to J3100.1

MEM A VREF CAMEM A VREF DQ

Page Notes

10mA max load

- =PP3V3_S3_VREFMRGN

Power aliases required by this page:



VREFMRGN

MEM B VREF DQ

ADDR=0x30(WR)/0x31(RD)

Required zero ohm resistors when no VREF margining circuit stuffed

ADDR=0x98(WR)/0x99(RD)

NO_VREFMRGN

BOM options provided by this page:

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.


MEM B VREF CA CPU FSB VREF

B4

B1 U2903UCSP

MAX4253

VREFMRGN

R2904

402

100

1%1/16WMF-LF

VREFMRGN

R2906

MF-LF

VREFMRGN

402

1%1/16W

100

R2910

402MF-LF1/16W1%

100

VREFMRGN

R2914100

402

1%

VREFMRGN

1/16WMF-LF

R2912

402

100

MF-LF

1%

VREFMRGN

1/16W

B4

B1 U2904UCSP

MAX4253

VREFMRGN

B4

B1 U2904UCSP

MAX4253

VREFMRGN

C2902

CERM402

10V20%0.1UF

VREFMRGN

B4

B1 U2903UCSP

VREFMRGN

MAX4253

B4

B1 U2902UCSP

MAX4253

VREFMRGN

B4

B1 U2902UCSP

VREFMRGN

MAX4253

R2911 VREFMRGN

1%

200

1/16WMF-LF402

R2909 VREFMRGN

1%

200

1/16WMF-LF402

R2905 VREFMRGN

1%

200

1/16WMF-LF402

R2903 VREFMRGN

1%

200

1/16WMF-LF402

R2902

VREFMRGN5%

402

100K

1/16WMF-LF

R2901

402MF-LF

VREFMRGN100K5%

1/16W

R2907100K VREFMRGN

402

5%

MF-LF1/16W

U2901PCA9557

VREFMRGN

QFN

C2904

20%10V

VREFMRGN

402CERM

0.1UF

R2908

VREFMRGN

402

1/16W5%

MF-LF

100K

25

39

39

U2900

MSOP

DAC5574

VREFMRGN

39

39

C2901

CERM

20%0.1UF

VREFMRGN

402

10V

C2900

20%6.3VCERM402-LF

2.2UF

VREFMRGN

C2905

CERM

VREFMRGN

0.1UF

10V20%

402

R2913

VREFMRGN

1/16W

100K5%

402MF-LF

C2903VREFMRGN

CERM10V

402

20%0.1UF

10 69


FSB/DDR3 Vref Margining

CRITICAL1 NO_VREFMRGN116S0004 RES,MTL FILM,0,5%,0402,SM,LF R2905

CRITICAL1 NO_VREFMRGN116S0004 RES,MTL FILM,0,5%,0402,SM,LF R2911

1 CRITICAL NO_VREFMRGN116S0004 R2909RES,MTL FILM,0,5%,0402,SM,LF

CRITICALR2903 NO_VREFMRGN1116S0004 RES,MTL FILM,0,5%,0402,SM,LF

=PPVTT_S3_DDR_BUF

PP0V75_S3_MEM_VREFCA_B



PP0V75_S3_MEM_VREFCA_A


PP0V75_S3_MEM_VREFDQ_B


PP0V75_S3_MEM_VREFDQ_A


VREFMRGN_DQ_SODIMMB_BUF

=PP3V3_S3_VREFMRGN

CPU_GTLREF

VREFMRGN_CA_SODIMM

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMA_EN

PCA9557D_RESET_L

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB

29 OF 109

B.0.0

051-8568

26 OF 77

C4

C1

C3

C2

1 2

1 2

1 2

1 2

1 2

C4

C1

C3

C2

A4

A1

A3

A2

2

1

A4

A1

A3

A2

C4

C1

C3

C2

A4

A1

A3

A2

1 2

1 2

1 2

1 2

12

12

12

15

3

4

5

1

2

6

7

9

12

13

14

16

10

11

17 8

2

1

12

8

3

5

4

2

16

7

9

10

2

1

2

1

12

2

1

8 57

28

27

28

27

8

26

26

26

26

26

26

26

26

26

26

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4*

DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS

DQ58

DQ59

DM7

VSS

DQ57

DQ56

DQ50

DQ51

VSS

DQS6*

DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS

DQ42

SDA

SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60

DQ61

VSS

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS

DQ40

DQ34

VSS

DQ32

TEST

VDD

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD

CK0

A1

A3

VDD

VDD

A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS

DQ44

DQ45

DQ39

DQ38

VSS

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD

ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

VDD

A0

CK1

A2

VDD

A4

VDD

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI

BIBI

BI

IN

BI

BI

BI

BI

BI

IN

IN

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

DQ16

DM3

DQ26

DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24

DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8

DQ9

DM0

DQ0

DQ1

VREFDQ

DQ3

DQ2

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

KEY

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

(SYMBOL 1 OF 2)

IN

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

BI

BI

IN

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

NC

NC

NC

BI

BI

BI

BI

BI

BI

BI

BI

BIBI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)


- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP1V5_S0_MEM_A

Page Notes

- =PP1V5_S3_MEM_A


516-0201

516-0201

- =I2C_SODIMMA_SDA

"Factory" (top) slot

- =I2C_SODIMMA_SCL

(NONE)


SPD ADDR=0xA0(WR)/0xA1(RD)

- =PP0V75_S0_MEM_VTT_A

C3100

603

X5R

6.3V

10UF20%

C3101

6.3V

X5R

603

10UF20%

J3100

OMIT

F-RT-THB

DDR3-SODIMM-DUAL-M97-3

15 70

15 70

C31310.1UF

CERM

402

20%

10V

C3130

CERM

6.3V

20%

2.2UF

402-LF

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

28 29

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

J3100

OMIT

F-RT-THB

CRITICAL

DDR3-SODIMM-DUAL-M97-3

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

9

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

C3136

10V

20%

402

CERM

0.1UF

C3135

402-LF

20%

6.3V

2.2UF

CERM

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

21 28 36

C3151

20%

2.2UF

6.3V

402-LF

CERM

39

39

C3150

CERM

402-LF

20%

2.2UF

6.3V

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

R314110K5%

402

1/16W

MF-LF

R314010K

MF-LF

1/16W

5%

402

C31402.2UF20%

CERM

402-LF

6.3V

C3110

402

10V

CERM

0.1UF20%

C3117

402

CERM

0.1UF20%10V

C3116

402

0.1UF20%10V

CERM

C3115

402

20%

CERM

10V

0.1UF

C3114

402

0.1UF20%

CERM

10V

C3113

402

0.1UF20%

CERM

10V

C3112

402

10V

0.1UF20%

CERM

C3111

402

20%10V

CERM

0.1UF

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70 15 70

15 70


DDR3 SO-DIMM Connector A

MEM_A_DQ<14>

MEM_A_DQ<11> MEM_A_DQ<8>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_DQ<10>

MEM_A_DQS_N<0>

MEM_A_DQ<3>

MEM_A_DQ<24>

MEM_A_DQ<29>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<38>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<19>

MEM_A_DQ<22>

=PP1V5_S3_MEM_A

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQ<28>

MEM_A_DQ<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<31>

MEM_A_DQ<27>

MEM_A_DM<3>

MEM_RESET_L

MEM_A_DM<1>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<16>

MEM_A_DQ<23>

MEM_A_DQ<9>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<2>

MEM_A_A<5>

MEM_A_DM<0>

MEM_A_DQ<6>

MEM_A_CKE<1>

MEM_A_A<11>

MEM_A_DQ<26>

MEM_A_DM<2>

MEM_A_A<10>

MEM_A_SA<1>

=PP0V75_S0_MEM_VTT_A

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_CLK_N<0>

MEM_A_SA<0>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DM<7>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<54>

MEM_A_DQ<51>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQ<52>

MEM_A_DQ<49>

MEM_A_DQ<46>

MEM_A_DM<5>

MEM_A_DQ<47>

=I2C_SODIMMA_SDA

=I2C_SODIMMA_SCL

MEM_EVENT_L

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<50>

MEM_A_DQ<55>

MEM_A_DM<6>

MEM_A_DQ<48>

MEM_A_DQ<53>

MEM_A_DQS_P<5>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_CS_L<1>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_BA<0>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_DQS_N<5>

MEM_A_DQ<39>

MEM_A_DM<4>

MEM_A_DQ<36>

MEM_A_DQ<37>

PP0V75_S3_MEM_VREFCA_A

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_BA<1>

MEM_A_RAS_L

MEM_A_CLK_N<1>

MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_A_A<4>

MEM_A_A<14>

MEM_A_A<15>

=PPSPD_S0_MEM_A

MEM_A_DQ<25>

MEM_A_DQ<4>

MEM_A_DQ<2>

MEM_A_DQS_P<0>

MEM_A_DQ<5>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<30>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQ<0>

MEM_A_DQ<7>

MEM_A_ODT<1>

31 OF 109

B.0.0

051-8568

27 OF 77

2

1

2

1

90

86

84

91

131

105

107

124

195

201

203

127

135

137

139

143

151

103

197

189

191

193

187

179

183

181

175

177

173

169

171

167

165

163

159

161

153

155

157

200

202

204

196

198

192

190

194

186

188

180

182

184

178

176

174

170

172

166

168

164

160

162

154

156

158

149

145

147

141

133

129

125

123

117

121

119

115

113

109

111

99

101

97

95

93

87

89

85

83

81

79

77

75

73

150

152

144

146

148

142

140

138

134

136

128

132

130

126

118

120

122

114

116

108

110

112

104

106

100

98

102

96

94

92

88

82

80

78

74

76

185

199

2

1

2

1

37

39

61

63

65

67

69

71

4

72

70

68

66

64

62

60

58

56

52

54

50

48

46

42

44

40

38

36

32

34

30

28

26

24

22

20

18

16

14

12

10

8

6

2

57

59

55

53

51

47

49

45

41

43

35

31

33

29

27

25

21

23

19

13

11

9

5

7

1

3

17

15

2

1

2

1

2

1

2

1

1

2

1

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

8

26

8

26

8

IN

BI

BI

BI

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42

DQ43

DQ48

DQ49

VSS

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15

A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36

DQ37

VSS

DM4

VSS

VSS

DQ38

DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD

NC

BA2

CK0

VDD

BA0

WE*

A13

S1*

VDD

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54

DQ55

VSS

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS

DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PINMTG PIN

MTG PIN MTG PIN

MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PINMTG PINS

KEY

(2 OF 2) DQ2

DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1*

DQS1

DQ10

DQ11

DQ17

DQS2*

DQS2

DQ18

DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6

DQ7

DQ12

DQ13

DM1

RESET*

DQ14

DQ15

DQ20

DQ21

DM2

DQ22

DQ23

DQ28

DQ29

DQS3*

DQS3

DQ30

DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

KEY

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BI BI

BI

BI

BI

BI

BI

BIBI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

IN

BI

IN

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

- =PPSPD_S0_MEM_B (2.5 - 3.3V)


- =PP1V5_S3_MEM_B


- =PP1V5_S0_MEM_B

DDR3 GROUND RETURN CAPS (MCP SIDE)

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

(NONE)

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)

SPD ADDR=0xA2(WR)/0xA3(RD)

516S0706

516S0706

"Expansion" (bottom) slot

Page Notes


- =PP0V75_S0_MEM_VTT_B

15 70

C3214

10V

CERM

20%

0.1UF

402

15 70

15 70

15 70

21 27 36

C32512.2UF

CERM

402-LF

6.3V

20%

39

39

C32502.2UF

6.3V

20%

402-LF

CERM

C32100.1UF

CERM

10V20%

402

C3201

20%

X5R

6.3V

603

10UF

C3231

10V

20%

402

CERM

0.1UF

C3200

X5R

6.3V

10UF20%

603

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

C3213

10V20%

0.1UF

402

CERM

15 70

15 70

15 70

15 70

15 70

15 70

C3212

CERM

10V20%

0.1UF

402

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

C3230

CERM

402-LF

6.3V

20%

2.2UF

R324110K

1/16W

MF-LF

5%

402

R3240

MF-LF

1/16W

402

5%

10K

C3240

20%

CERM

402-LF

6.3V

2.2UF

C3229

10V

CERM

20%

0.1UF

402

C3228

10V

CERM

20%

0.1UF

402

C3227

10V

CERM

0.1UF20%

402

C3226

10V

CERM

20%

0.1UF

402

C3225

10V

CERM

20%

0.1UF

402

15 70

C3224

10V

CERM

20%

0.1UF

402

C3223

10V

CERM

20%

0.1UF

402

C32220.1UF20%10V

CERM

402

J3200F-RT-BGA3

DDR3-SODIMM

OMIT

J3200F-RT-BGA3

CRITICAL

DDR3-SODIMM

OMIT

15 70 15 70

15 70

15 70

15 70

15 70

15 70

15 70 15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

C3211

10V

CERM

0.1UF20%

402

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

27 29

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

9

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70

C3217

10V

CERM

0.1UF20%

402

15 70

15 70

15 70

15 70

15 70

15 70

C3216

10V

CERM

20%

0.1UF

402

15 70

15 70

15 70

15 70

15 70

15 70

15 70

C3236

CERM

402

20%

10V

0.1UF

C32352.2UF

6.3V

CERM

20%

402-LF

C3215

10V

CERM

20%

0.1UF

402

15 70

15 70

15 70

15 70

15 70

15 70

15 70

15 70


DDR3 SO-DIMM Connector B

=PP1V5_S3_MEM_B

MEM_B_DM<4>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

MEM_EVENT_L

MEM_B_DQ<53>

MEM_B_DQ<39>

MEM_B_DQ<32>

MEM_B_DQ<37>

MEM_B_DQ<52>

MEM_B_DQ<38>

MEM_B_DQ<33>

MEM_B_DQ<36>

MEM_B_DQS_P<5>

MEM_B_DM<6>

MEM_B_DQ<47>

MEM_B_DQ<27> MEM_B_DQ<31>

MEM_B_DQ<26>MEM_B_DQ<30>

MEM_B_DQ<18>

MEM_B_DQ<21>

MEM_B_DQ<16>

MEM_B_DQ<22>

MEM_B_DQ<3>MEM_B_DQ<7>

MEM_B_DQ<19>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQ<6>

MEM_B_DQ<8>

MEM_B_DQ<20>

MEM_B_DQ<23>

MEM_B_DQ<63>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_CKE<0>

MEM_B_DQS_N<7>

MEM_B_SA<0>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<12>

MEM_B_DQ<46>

MEM_B_DQ<49>

MEM_B_DQ<41>

MEM_B_DQS_N<4>

MEM_B_DM<5>

MEM_B_CKE<1>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_DQ<34>

MEM_B_DQ<44>

MEM_B_DQ<40>

MEM_B_BA<2>

MEM_B_CLK_P<0>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_A<13>

MEM_B_CS_L<1>

MEM_B_DQ<35>

MEM_B_DQ<45>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<48>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<59>

MEM_B_DQS_P<7>

MEM_B_DQ<57>

MEM_B_DQ<62>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_CLK_N<0>

MEM_B_DQS_P<4>

MEM_B_CAS_L

MEM_B_DQ<56>

MEM_B_DQ<58>

MEM_B_SA<1>

MEM_B_DQ<61>

MEM_B_DQ<60>

=PPSPD_S0_MEM_B

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DM<0>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<15>

MEM_B_DQ<10>

MEM_B_DQ<17>

MEM_B_DQS_P<2>

MEM_B_DQ<5>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQ<2>

MEM_B_DQ<12>

MEM_B_DQ<9>

MEM_B_DM<1>

MEM_RESET_L

MEM_B_DQ<11>

MEM_B_DM<2>

MEM_B_DQ<29>

MEM_B_DQ<25>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQ<4>

MEM_B_DM<3>

MEM_B_DQS_N<2>

=PP0V75_S0_MEM_VTT_B

MEM_B_DM<7>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQS_N<5>

PP0V75_S3_MEM_VREFCA_B

MEM_B_DQ<28>

MEM_B_DQ<24>

=PP1V5_S0_MEM_MCP

MEM_B_RAS_L

MEM_B_A<3>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_A<9>

MEM_B_A<11>

MEM_B_A<14>

MEM_B_A<15>

32 OF 109

B.0.0

051-8568

28 OF 77

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1

2

1

2

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

99

97

95

93

91

89

87

85

81

83

161

157

159

163

165

167

151

149

135

153

76

74

78

80

82

84

86

90

88

92

96

102

98

100

106

104

112

110

108

116

114

122

120

118

126

124

130

132

128

136

134

138

140

142

148

146

144

152

150

73

75

77

79

101

111

109

113

119

121

117

123

125

131

129

133

141

147

145

158

156

154

162

160

164

168

166

172

170

174

176

178

184

182

180

188

186

194

190

192

198

196

204

202

200

155

171

169

173

177

175

107

105

103

143

139

137

127

115

94

187

185

181

208207

209 210

211 212

206

179

183

203

201

197

191

189

193

195

199

205

15

17

3

1

7

5

9

11

13

19

23

21

25

27

29

33

31

35

43

41

45

49

47

51

53

55

59

57

2

6

8

10

12

14

16

18

20

22

24

26

28

30

34

32

36

38

40

44

42

46

48

50

54

52

56

58

60

62

64

66

68

70

72

4

71

69

67

65

63

61

39

37

2

1

2

1

2

1

2

1

2

1

2

1

8

8

8

26

26

8

IN OUT

D

Q2

SG

Q1

B

CE




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.

DDR3 RESET Support

rise to avoid glitch on MEM_RESET_L.

3.3V S5 is used because MEM_RESET

must be high before 1.5V starts to

16

R3305100K

402MF-LF1/16W

5%

27 28

R33101K

402MF-LF1/16W

5%

12

R3309

5%

MF-LF1/16W

0

402

R330010K

1/16WMF-LF402

5%

Q3305

SOT-363

DMB53D0UDW

C3300

402CERM

20%0.1UF

10V

R3301

5%20K

1/16W

402MF-LF


DDR3 Support

MCP_MEM_RESET_L

=PP1V5_S3_MEMRESET

MEM_RESET_RC_L

MEM_RESET_L

MEM_RESET

=PP3V3_S5_MEMRESET

33 OF 109

B.0.0

051-8568

29 OF 77

1

2

1

21

2

64

5

32

1

2

11

2

8

8

OUT

IN

IN

IN

IN

IN

BI

BI

Y

B

A

IN

SYM_VER-1

SYM_VER-1

D

S G

D

S G

OUT

OUT

IN

D

GS

NC

NC

NCNC

SYM_VER-1

SYM_VER-1

OUT

OUT

OUT

OUT

SG

D




36

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REVISION

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET

516S0582

155S0367

727 MA PEAK

CHANNEL

RDS(ON)

LOADING

MOSFET TPCP8102

3V S3 WLAN FET

0.727 A (EDP)

P-TYPE

20-30 MOHM @2.5V

AIRPORT

BLUETOOTH

RC VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN

606 MA NOMINAL MAX

7 17

30 32

C3430

0.1uF

16V10% X5R 402

PLACEMENT_NOTE=Place close to J3401.

17 71

17 71

C34310.1uF

40216V X5R10%


17 71

17 71

C34210.1uF

402CERM

10V20%

PLACEMENT_NOTE=Place close to Q3450.

20 72

20 72

U3401

TC7SZ08AFEAPESOT665

25

C3420

X5R

10UF

805

20%

PLACEMENT_NOTE=Place close to Q3450.

10V

R3453110K

1/16W

402

MF-LF

5%

R3454

NOSTUFF62K

1/16W

MF-LF

5%

402

C3453

402

CERM

1UF

6.3V10%

L3401

CRITICAL

90-OHM-100MADLP11S


L340390-OHMDLP0NS

CRITICAL


Q3401

SOT563

SSM6N15FEAPE

Q3401

SOT563

SSM6N15FEAPE

17

17

21 32

Q3455

SOD-VESM-HF

SSM3K15FV

R34551

MF-LF402

1/16W5%

U340274LVC1G17

SOT353-1

L3402CRITICAL

90-OHM-100MADLP11S


L3405


90-OHM-100MADLP11S

CRITICAL

17 71

17 71

R34521%1/4WMF1206

0.002

CRITICAL

47 75

47 75

L3404

0603

FERR-120-OHM-3A

C3432

CERM16V10%

402

PLACEMENT_NOTE=PLACE C3432 NEAR J3401

0.01UF

L3406

FERR-120-OHM-1.5A0402-LF

PLACEMENT_NOTE=PLACE L3406 NEAR J3401.

J3401F-ST-SM

CRITICAL

500913-0302

Q3450CRITICAL

23V1K-SM

TPCP8102

C3450

402

10%16V

0.1UF

X5R

C3451

402

10%

X5R

16V

0.033UF

R3450

1/16W5%

402MF-LF

100K

R3451

1/16W

10K

MF-LF

5%

402

C3422

10V20%

CERM402

0.1uF



X16 WIRELESS CONNECTORSYNC_MASTER=K24_MLB

PM_WLAN_EN_L

CONN_PCIE_MINI_R2D_N

CONN_PCIE_MINI_D2R_P

CONN_PCIE_MINI_D2R_N

PP3V3_WLAN

VOLTAGE=3.3VMIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

CONN_PCIE_MINI_R2D_P

PCIE_CLK100M_MINI_CONN_P

CONN_USB2_BT_P

PP3V3_S3_BT_F

MINI_RESET_CONN_L

PCIE_WAKE_L

CONN_USB2_BT_N

PCIE_CLK100M_MINI_CONN_N

PCIE_MINI_R2D_C_N

PP3V3_WLAN_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=1 mm

ISNS_AIRPORT_N

AP_PWR_EN

PCIE_MINI_PRSNT_L

PCIE_CLK100M_MINI_P

PCIE_MINI_D2R_N

WLAN_SMIT_RC

WLAN_SMIT_BUF

MINI_RESET_L

PP3V3_WLAN_F

WLAN_SMIT_DISCHRG

PCIE_CLK100M_MINI_N

PCIE_MINI_R2D_C_P

PCIE_MINI_D2R_P

MINI_CLKREQ_L

PM_WLAN_EN_L

VOLTAGE=3.3V

PP3V3_WLAN_R

MIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=1 mm

P3V3WLAN_SS

PCIE_MINI_R2D_P

ISNS_AIRPORT_P

PCIE_MINI_R2D_N

USB_BT_P

USB_BT_N

=PP3V3_S3_WLAN

=PP3V3_S3_BT

MINI_CLKREQ_Q_L

=PP3V3_S3_WLANMIN_LINE_WIDTH=0.5 mm


34 OF 109

B.0.0

051-8568

30 OF 77

1 2

1 2

2

1

3

5

1

4

2

2

1

1

2

1

2

2

1

4 3

1 2

4 3

1 2

6

12

3

45

12

3

1 2

4

1

5

3

2

4 3

1 2

4 3

1 2

43

2121

2

1

2 1

4

6

8

10

12

7

5

1

3

11

9

22

24

26

28 27

25

23

21

29

14

16

18

20

17

15

19

13

30

2

3132

3334

78

56

4

31

2

1 2

2

1

1 2

1

2

2

1

30 32

7 71

7 71

7 71

7 7 71

7 71

7 72

7

7

7 72

7 71

30 47

30 47

71

71

8 30

8

7

8 30

IN

IN

IN

IN

IN

IN

BI

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

DVDD33

VDDREG

REGOUT

MDI-[0]

RXD[2]/AN0

LED0/PHYAD0

LED2/RXDLY

LED1/PHYAD1

MDI-[3]

RXD[1]/TXDLY

RXD[3]/AN1

MDI-[1]

MDI+[1]

MDI+[3]

MDI+[2]

MDI-[2]

RXCTL

MDC

PHYRSTB*

RSET

CLK125

CKXTAL2

CKXTAL1

MDI+[0]

RXD[0]

GND

MDIO

RXC

TXCTL

AVDD10

DVDD10

ENSWREG

TXD[3]

TXD[2]

TXD[1]

TXD[0]

TXC

AVDD33

FB10

LED

RESET

CLOCK

MANAGEMENT

MEDIA DEPENDENT

RGMII/MII

REFERENCE




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

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A

D

2 1


Apple Inc.

PAGE


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B

C

345678

D

B

8 7 5 4 2 1

WF: Marvell numbers, update for Realtek

PHYAD = 01 (PHY Address 00001)

AN[1:0] = 11 (Full auto-negotiation)

(19mA typ - Energy Detect)

ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.

HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.

Alias to =PP3V3_ENET_PHY for internal switcher.

Reserved for EMI

per RealTek request.

PLACE R3796 CLOSE TO U1400, PIN D24

Alias to GND for external 1.05V supply.

If internal switcher is used, must place inductor within 5mm

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

If internal switcher is used, must place 1x 22uF &

Configuration Settings:

TXDLY = 0 (No TXCLK Delay)

RXDLY = 0 (RXCLK transitions with data)

WF: Marvell numbers, update for Realtek

(221mA typ - 1000base-T)

( 7mA typ - Energy Detect)

(43mA typ - 1000base-T)

If internal switcher is not used, VDDREG and REGOUT can float.

R37240

MF-LF

5%

1/16W

402C3725

20%

CERM402

10V

NO STUFF

0.1UF

R37302.49K

1%1/16W

402MF-LF

R3725

5%

4.7K

1/16W

NO STUFF

402MF-LF

R372010K5%

MF-LF1/16W

402

L3705

CRITICAL


C37050.1UF

16V

X5R402

10%

C37060.1UF

16V

X5R402

10%

C37000.1UF

16V

X5R402

10%

C3701

16V

0.1UF

X5R402

10%

C37020.1UF

16V

X5R402

10%

18 73

18 73

18 73

18 73

18 73

18 73

18 73

18 73

32 73

33 73

33 73

33 73

33 73

33 73

33 73

33 73

33 73

R3790MF-LF5% 1/16W

22

402

R3791402MF-LF1/16W5%

22

R3792402MF-LF1/16W5%

22

R3793402

22

MF-LF1/16W5%R3794402

22

MF-LF1/16W5%

R3795402

22

MF-LF1/16W5%

18 73

18 73

18 73

18 73

18 73

18 73

R3755

402

4.7K

MF-LF

5%1/16W

R3756

402

4.7K

MF-LF

5%1/16W

9

R3752

402

MF-LF

5%

4.7K

1/16W

R3757

402

4.7K

MF-LF

5%1/16W

R3750

1/16W5%

4.7K

MF-LF

402

R3751

MF-LF

4.7K5%1/16W

402

C3715

6.3V

402X5R

2.2UF10%

C3716

402

0.1UF

16VX5R

10%

L3715FERR-120-OHM-1.5A

0402-LF

CRITICAL

C37110.1UF

16VX5R

10%

402

C37100.1UF

16VX5R

402

10%

C3714

402

2.2UF

6.3VX5R

10%

C3790

402

5%

CERM

50V

10PF

NO STUFF

R3796

MF-LF

4021/16W5%

018 73

U3700RTL8251CA-VB-GR

CRITICAL

TQFP


Ethernet PHY (RTL8211CL)SYNC_MASTER=K24_MLB

=RTL8211_REGOUT

ENET_MDI_N<0>

ENET_RXD_R<2>

RTL8211_PHYAD0

RTL8211_RXDLY

RTL8211_PHYAD1

ENET_MDI_N<3>

ENET_RXD_R<1>

ENET_RXD_R<3>

PP3V3_ENET_PHYAVDDMIN_LINE_WIDTH=0.6 MM


ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_P<3>

ENET_MDI_P<2>

ENET_MDI_N<2>

ENET_RXCTL_R

ENET_MDC

RTL8211_PHYRST_L

RTL8211_RSET

TP_RTL8211_CLK125

TP_RTL8211_CKXTAL2

RTL8211_CLK25M_CKXTAL1

ENET_MDI_P<0>

ENET_RXD_R<0>

ENET_MDIO

ENET_CLK125M_RXCLK_R

ENET_TX_CTRL

=RTL8211_ENSWREG

ENET_TXD<3>

ENET_TXD<2>

ENET_TXD<1>

ENET_TXD<0>

ENET_CLK125M_TXCLK_R

ENET_RESET_L

ENET_CLK125M_TXCLK

ENET_RX_CTRL

ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<1>

ENET_RXD<0>

ENET_CLK125M_RXCLK

=PP3V3_ENET_PHY

VOLTAGE=1.05V

PP1V05_ENET_PHYAVDDMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

=PP3V3_ENET_PHY_VDDREG

=PP1V05_ENET_PHY

37 OF 109

B.0.0

051-8568

31 OF 77

1 2

2

1

1

2

1

2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1

2

1

2

1

2

1

2

1

2

2

1

2

1

1

2

2

1

2

1

2

1

2

1

1 2

15

21

37

44

45

48

2

17

34

38

35

12

16

18

41

5

4

11

8

9

13

30

29

46

32

43

42

1

14

20

33

477

31

19

27

40

10

36

28

39

26

25

24

23

22

6 3 9

73

73

73

73

9

73

73 73

8

9

8

G

DS

IN OUT

OUT

D

SG

IN

D

S G

IN

IN

D

SG

D

SG

D

S

G

D

SG

IN

D

SG

IN




36

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PAGE


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B

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345678

D

B

8 7 5 4 2 1

Pull-up is with power FET.

ARB for alternate power options.

Recommend aliasing PM_SLP_RMGT_L and

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

=P3V3ENET_EN. Nets separated on

Non-ARB:

ARB for alternate power options.

Recommend aliasing PM_SLP_RMGT_L and

=P1V05ENET_EN. Nets separated on

1.8V Vgs

RTL8211 25MHz Clock

MOBILE:

1.05V ENET FET

3.3V ENET FET@ 2.5V Vgs:

Rds(on) = 90mOhm max

I(max) = 1.7A (85C)

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

WLAN Enable Generation

Q3810

CRITICAL

NTR4101P

SOT-23-HF

C3810

10%

402

0.01UF

16V

CERM

C38110.033UF10%

402

X5R16V

R3810

MF-LF402

100K

5%1/16W

18 73

R3895

402

22

MF-LF

5%1/16W


31 73

C3841

16V

0.01UF

CERM

402

10%

C38400.1UF

20%

CERM

10V

402

30

Q3805SSM6N15FEAPE

SOT563

21 36 37

Q3801

SOT563

SSM6N15FEAPE

21 30

7 21 36 62 66

Q3805SSM6N15FEAPE

SOT563

Q3841

SOT563

SSM6N15FEAPER384269.8K

1/16W

1%

402

MF-LF

Q3840

SI2312BDS

SOT23

CRITICAL

R380010K

5%

402

MF-LF

1/16W

Q3801

SOT563

SSM6N15FEAPE

9

Q3841SSM6N15FEAPE

SOT563

9

R384110K

402

1/16W

1%

MF-LF

R3840

5%1/16W

100K

402

MF-LF

Ethernet & AirPort SupportSYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009

AP_PWR_EN

P1V05ENET_SS

P1V05ENET_EN_L_RC

=P3V3ENET_EN

SMC_ADAPTER_EN

PM_WLAN_EN_L

AC_OR_S0_L

=P1V05ENET_EN

=PP1V05_ENET_FET

P3V3ENET_EN_L

MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1

P3V3ENET_SS

=PP3V3_ENET_FET

PM_SLP_S3_L

=PP1V05_ENET_P1V05ENETFET

P1V05ENET_EN_L



38 OF 109

B.0.0

051-8568

32 OF 77

32

1

12

2

1

1 2

1 2

2

1

2

1

3

45

6

12

6

12

6

12

1

2

2

1

3

1

2

3

45

3

45

1 2

1 2

8

8

8

8

8

BI

BI

BI

BI

BI

BI

BI

BI

PINSSHIELD

TRAN_N0

TRAN_N3

TRAN_P3

TRAN_N1

TRAN_N2

TRAN_P2

TRAN_P1

TRAN_P0ENET_MDI

RX

TX

RX

TX




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902

- COPY THIS PAGE FROM K36 CSA.39

ETHERNET CONNECTOR

514-0692

31 73

31 73

31 73

31 73

31 73

31 73

31 73

31 73

C3911

CRITICAL

402-1

10PF

50VCERM

5%

C3912CRITICAL

402-1

5%10PF

50VCERM

C3913

CRITICAL402-1

50V

10PF5%

CERM

C3914

CRITICAL

402-1

50VCERM

10PF5%

C391510PF

CRITICAL

402-1

5%

CERM50V

C3916

CRITICAL

402-1

10PF

50V5%

CERM

C3917

CRITICAL

402-1

50VCERM

10PF5%

C3918

CRITICAL

402-1

5%10PF

CERM50V

J3900CRITICAL

F-R-THRJ45-10/100TX-K83

OMIT

C3902

X5R16V

402

10%0.1UF

C3900

X5R

10%

402

16V

0.1UFC3901

10%16VX5R

0.1UF

402

C3903

10%

X5R16V

402

0.1UF

R390075

MF-LF1/16W1% 402

R3901

1% 1/16W MF-LF 402

75

R3902

1% 1/16W 402MF-LF

75

R3903

4021/16W

751% MF-LF

C39101000PF

CRITICAL

CERM1206

10%2KV

T3902

CRITICAL

SM

TLA-6T213HF

T3901SM

TLA-6T213HF

CRITICAL


ETHERNET CONNECTOR

ENET_MDI_N<0>

ENET_MDI_N<3>

ENET_MDI_P<0>

ENET_MDI_N<2>

PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS

ENET_CENTER_TAP<2>

ENET_CENTER_TAP<1>

ENET_CENTER_TAP<3>

ENET_CENTER_TAP<0>

ENET_MDI_P<1>

ENET_MDI_P<3>

ENET_MDI_P<2>

ENET_CONN_CTAP

MIN_NECK_WIDTH=0.25MM

ENET_BOB_SMITH_CAPMIN_LINE_WIDTH=0.6MM

ENET_MDI_TRAN_N<3>

ENET_MDI_TRAN_N<0>

ENET_MDI_TRAN_P<2>

ENET_MDI_TRAN_P<1>

ENET_MDI_TRAN_P<3>

ENET_MDI_TRAN_P<0>

ENET_MDI_TRAN_N<1>

ENET_MDI_TRAN_N<2>

ENET_MDI_N<1>

39 OF 109

B.0.0

051-8568

33 OF 77

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1

2

3

5

6

8

4

7

10

9

11

12

2

1

2

1

2

1

2

1

1 2

1 2

1 2

1 2

2

1

1

3

2

12

11

9

8

7

4

5

6

10

1

3

2

12

11

9

8

7

4

5

6

10

73

73

73

73

73

73

73

73

OUT

OUT

OUT

OUT

SG

D

NC

OUT

IN

SYM_VER-1

SYM_VER-1

OUT

OUT

IN

IN

D

SG

D

SG

SYM_VER-1

SYM_VER-1

OUT

OUT

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

SIL

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

ensure the drive is unpowered in S3/S5.

518S0519

SATA ODD

516S0616

ODD Power Control

Indicates disc presence

SATA HDD

516S0616

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6mm

J4501CRITICAL

54722-0164F-ST-SM

R4598

CRITICAL

MF1/4W

1%0.002

1206

R4599CRITICAL

1206MF1/4W

0.0021%

47 75

47 75

47 75

47 75

Q4590CRITICAL

TPCP8102

7 36

R4590

402

33K

MF-LF

5%1/16W

FL4520

PLACEMENT_NOTE=Place FL4520 close to J4500

CRITICAL

DLP11S90-OHM-100MA

FL4525DLP11S

CRITICAL

90-OHM-100MA


20 71

20

20 71

20 71

Q4596

SOT563SSM6N15FEAPE

R4597

1/16W5%

402MF-LF

100K

Q4596

SOT563SSM6N15FEAPE

R4596

1/16W5%

402MF-LF

100K

R4595100K

1/16W5%

MF-LF402

C4595

10V

0.068UF10%

CERM402

C4596

10%

402

0.01UF

16V

C452116V10% 402CERM

PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

C452016V10% 402CERM0.01UF

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

C452616V10% 402CERM0.01UF

C452510% 402CERM

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

16V0.01UF

L4500

0603

CRITICAL

FERR-70-OHM-4A

C4501

CERM402

10V20%0.1UF

FL4501CRITICAL

90-OHM-100MADLP11S

C45020.1UF

CERM402

20%10V

FL4502CRITICAL

DLP11S90-OHM-100MA

20 71

20 71

20 71

C451610% 402CERM0.01UF 16V

C4510

0.01UF CERM 40210% 16V

C451140216V10% CERM0.01UF

C451510% 402CERM0.01UF 16V

J450054722-0164

CRITICAL

F-ST-SM


SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_N

SATA_ODD_R2D_UF_P=PP3V3_S0_ODD

VOLTAGE=5VMIN_NECK_WIDTH=0.4mmMIN_LINE_WIDTH=0.6mm

PP5V_S0_HDD_R

ISNS_HDD_P

ISNS_HDD_N

ODD_PWR_EN_L

ODD_PWR_EN_LS5V_L

SATA_ODD_R2D_C_P

SATA_ODD_D2R_P

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_UF_P

SATA_ODD_D2R_UF_N

SATA_HDD_R2D_C_P

SATA_HDD_D2R_N

SATA_HDD_D2R_P

SATA_HDD_D2R_UF_N

SATA_HDD_D2R_UF_P

SATA_ODD_R2D_C_N

ISNS_ODD_P

=PP5V_S0_HDD

SATA_ODD_D2R_N

ISNS_ODD_N

SATA_HDD_R2D_C_NSATA_HDD_R2D_UF_N

ODD_PWR_EN

PP5V_SW_ODD_R

VOLTAGE=5VMIN_NECK_WIDTH=0.4mmMIN_LINE_WIDTH=0.6mm

ODD_PWR_SS

=PP5V_S3_ODD

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

SATA_ODD_R2D_P

SATA_ODD_R2D_N

SMC_ODD_DETECT

SATA_HDD_R2D_P SATA_HDD_R2D_UF_P

VOLTAGE=5V

PP5V_S0_HDD_FLT

VOLTAGE=5VMIN_NECK_WIDTH=0.4mmMIN_LINE_WIDTH=0.6mmPP5V_SW_ODD

SATA Connectors

21

23V1K-SM

SYS_LED_ANODE SYS_LED_ANODE_R

SYS_LED_RETURN_UF

R45314.7

MF-LF

402

5% 1/16W

C4531

10%

50V

0.001UF

402

CERM

FERR-1000-OHML4531

0402

FERR-1000-OHML4530

0402

M-RT-SM78171-0002J4502

SYS_LED_ANODE_UF

CRITICAL

=PP3V3_S0_ODD

0.01UF

71

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500

CERM

45 OF 109

B.0.0

051-8568

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501




PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

PLACEMENT_NOTE=Place C4516 close to J4501

PLACEMENT_NOTE=Place C4510 close to MCP79PLACEMENT_NOTE=Place C4511 next to C4510

PLACEMENT_NOTE=Place C4515 next to C4516

34 OF 77

15

13

11

9

7

5

3

1

16

14

12

10

8

6

4

2

2

1 3

4

43

21

78

56

4

31

2

4

2

1

3

21

21

2

1

12

1

2

43

12

4 3

1 2

3

45

6

12

1 2

2

1

1 2

1 2

1 2

1 2

1 2

21

2

1

43

12

2

1

4 3

1 21 2

1 2

1 2

1 2

15

13

11

9

7

5

3

1

16

14

12

10

8

6

4

2

7 71

7 71

7 71

71 8 34

34

71

71

71

71

8

71

8

7 71

7 71

7 71 71

7

7 47

7 36

8

71

OUT

BI

BI

SYM_VER-1

IN

OUT

IN

SYM_VER-1

BI

BI

OUT

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

IN

OUT2

TPADGND

OUT1

OC1*

EN2

EN1

OC2*

IN

IO

IO

NC

GND

VBUS

NC

IO

IO

NC

GND

VBUS

NC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Port Power Switch

514-0689

POR IS PLASTIC USB CONNECTOR PARTS BUT METAL PART’S SCHEMATIC AND CAD SYMBOLS

HAVE BEEN USED AS ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES

USB PORT A (FRONT PORT)

USB/SMC Debug Mux

USB PORT B (BACK PORT)

SEL=0 Choose SMCSEL=1 Choose USB

We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.

CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION

514-0689

Place L4600 and L4605 at connector pin

We can add protection to 5V if we want, but leaving NC for now


CRITICAL

PLACEMENT_NOTE=NEAR J4600

0603

C4696

POLY-TANT

100UF

CRITICAL

6.3V20%

CASE-B2-SM

C4695

20%

10UF

6.3VX5R603

C4691

10V

0.1UF20%

CERM402

20

20 72

20 72

C4650

402

10V20%

SMC_DEBUG_YES

0.1UF

CERM

R4650

MF-LF

402

1/16W

10K5%

L4600


90-OHM

CRITICAL

DLP0NS

36 37 38

36 37 38

36

R4651

402

5%

0

MF-LF

1/16W

SMC_DEBUG_NO

R4652

MF-LF

1/16W

5%

402

0

SMC_DEBUG_NO

C4605

20%

402

0.01uF

16V

CERM

C46150.01uF

CERM

20%16V

402


CRITICALPLACEMENT_NOTE=NEAR J4610

0603

L4610


DLP0NS90-OHM

CRITICAL

C4617

6.3VX5R

10UF

603

20%

C4616

6.3V

CASE-B2-SM

POLY-TANT

20%

CRITICAL

100UF

20 72

20 72

20

C4690

6.3V

603

10UF

X5R

20%

NOSTUFF

U4650

SMC_DEBUG_YES

PI3USB102ZLE

CRITICAL

TQFN

62

U4690

MSOP

CRITICAL

TPS2064DGN

J4600

OMIT

F-RT-TH

CRITICAL

USB-K83

J4610

OMIT

F-RT-THUSB-K83

CRITICAL

6

1

D4600RCLAMP0502N

NOSTUFFCRITICALSLP1210N6

6

1

D4610RCLAMP0502N

SLP1210N6CRITICAL NOSTUFF


External USB Connectors

PP5V_S3_RTUSB_B_ILIM



VOLTAGE=5V


VOLTAGE=5VMIN_NECK_WIDTH=0.5 mm

PP5V_S3_RTUSB_A_ILIM

CONN_USB_EXTA_N

PP5V_S3_RTUSB_A_FMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.5 mmVOLTAGE=5V

CONN_USB_EXTA_PUSB_EXTA_MUXED_P

USB_EXTA_MUXED_N

USB_EXTB_P


VOLTAGE=5V

PP5V_S3_RTUSB_B_F


=USB_PWR_EN

=PP3V42_G3H_SMCUSBMUX

USB_EXTB_N

USB_DEBUGPRT_EN_L

SMC_TX_L

SMC_RX_L

USB_EXTA_P

USB_EXTA_N

=PP5V_S3_EXTUSB

USB_EXTB_OC_L

USB_EXTA_OC_L

CONN_USB_EXTB_P

CONN_USB_EXTB_N

46 OF 109

B.0.0

051-8568

35 OF 77

21

1

22

1

2

1

2

11

2

4 3

1 2

1 2

1 2

2

1

2

1

21

4 3

1 2

2

1 1

2

2

1

93

108

7

6

1

2

5

4

6

91

7

8

4

3

5

2

1

2

4

3

5

6

7

8

1

2

4

3

5

6

7

8

2 5 3 4

2 5 3 4

72

72 72

72

8

8

72

72

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

OUT

BI

IN

IN

OUT

BI

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

IN

IN

OUT

ININ

BI

BI

OUT

IN

OUT

OUT

NC

OUT

OUT

OUTNC

NCNCNC

NC

NC

NC

NCNC

NCNCNC

NC

NC

NC

NC

NC

NCNC

NCNC

NC

NCNC

IN

OUT

OUT

OUT

OUT

P13

P14

P15

P16 P66

P10

P11

P12

P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P36

P37

P40

P41

P42

P43

P44

P45

P46

P47

P50

P51

P52

P60

P61

P62

P63

P64

P65

P67

P70

P71

P72

P73

P74

P75

P76

P77

P80

P81

P84

P85

P86

P90

P91

P92

P93

P94

P95

P96

P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0

PA1

PA2

PA3

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE0

PE1

PE2

PE3

PE4

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PH0

PH1

PH2

PH3

PH4

PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREFAVCC

EXTAL

XTAL

(3 OF 3)

BI

BI

BI

BI

IN

IN

IN

OUT

BI

IN

IN

IN

IN

BI

BI

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

pins designed as outputs can be left floating,

NOTE: Unused pins have "SMC_Pxx" names. Unused

those designated as inputs require pull-ups.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

SMC_PB3:

SMC_IG_THROTTLE_L for MG systems.

.

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(DEBUG_SW_1)

(DEBUG_SW_2)

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(See below)

NOTE: P94 and P95 are shorted, P95 could be spare.

If SMS interrupt is not used, pull up to SMC rail.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

C4902

6.3V20%

CERM805

22UF

19 38

37 38

37 44

C4907

6.3V

0.47UF

CERM-X5R402

10%

PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1

C4903

20%

0.1UF

10V

402CERM

C4920

PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PIN M12

20%

CERM

0.1UF

402

10V

R4999

PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PIN M12

5%

4.7

1/16W

MF-LF402

C4904

20%

CERM

0.1UF

402

10V

XW4900SM

21

58

C4905

20%

CERM

0.1UF

402

10V

21

62

25 62

37

C4906

20%

CERM

0.1UF

402

10V

41

40

37

37

41

40

41

37

37

37 54

35 36 37 38

35 36 37 38

7 56 62

39

R490910K

MF-LF

5%

1/16W

402

38

38

R4901

MF-LF

10K5%

1/16W

402

R4902

1/16W5%

MF-LF

10K

402

R4903

NO STUFF

0

MF-LF

5%1/16W

402

R499810K

MF-LF

5%1/16W

402

35

54

21

7 34

37

21

37

43

37

37

37

37

37

37

43

46

46

37

46

37

37

37

37 38

37

37 38

37 38

37 38

37 44 54

39

39

39

39

39

39

37

37

37

37

35 36 37 38

35 36 37 38

37 37

19 38

21 27 28

25

38

21

19 38

37

46

21 32 37

37

37

37

37

37

U4900H8S2117

OMIT

LGA-HF

U4900

OMIT

H8S2117LGA-HF

U4900H8S2117

OMIT

LGA-HF

C4950

402

0.033UF

X5R

16V

PLACEMENT_NOTE=PLACE C4950 CLOSE TO U4900 PIN M10

10%C4951

402

0.033UF

X5R

16VPLACEMENT_NOTE=PLACE C4951 CLOSE TO U4900 PIN N9

10%

C4952

402

0.033UF

X5R

16V

PLACEMENT_NOTE=PLACE C4952 CLOSE TO U4900 PIN K10

10%

19 38 72

19 38 72

19 38 72

19 38 72

19 38 72

25

25 72

9

39

7 21 32 62 66

7 21 37 62

37

25 72

39

39

37

SMCSYNC_MASTER=K24_MLB SYNC_DATE=04/02/2009ALS_LEFT

SMC_NB_DDR_ISENSE

SMC_FAN_3_CTL

SMC_RUNTIME_SCI_L

ALL_SYS_PWRGD

RSMRST_PWRGD

SMC_PH2

PM_SLP_S5_L

PM_PWRBTN_L

SMC_FAN_2_CTL

SMC_EXCARD_CP

SMC_EXCARD_OC_L

GND_SMC_AVSS

SMC_PA5

MEM_EVENT_L

SMC_FAN_1_CTL

SMC_FAN_0_TACH

SMC_TMS

SMC_TDO

SMC_TCK

SMB_0_S0_DATA

PM_SLP_S3_L

SMC_BC_ACOK

SMC_RX_L

SMC_RSTGATE_L

=PP3V3_S5_SMC

SMC_BS_ALRT_L

SMC_ONOFF_L

SMC_BATT_ISENSE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_CPU_VSENSE

SMC_CPU_ISENSE

SMB_0_S0_CLK

SMC_RX_L

SMC_TX_L

SMC_SYS_KBDLED

SMC_GFX_THROTTLE_L

SMS_ONOFF_L

SMB_MGMT_DATA

SMC_P41

LPC_SERIRQ

LPC_FRAME_L

LPC_AD<2>

ALS_GAIN

SMC_PROCHOT

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_A_S3_CLK

SMB_A_S3_DATA

SMB_BSA_CLK

SMB_BSA_DATA

=SMC_SMS_INT

SMC_MCP_SAFE_MODE

SMC_LID

SMC_SYS_LED

SMC_FAN_0_CTL

SMC_GFX_OVERTEMP_L

SMC_PB3

SMC_ODD_DETECT

PM_BATLOW_L

SYS_ONEWIRE

USB_DEBUGPRT_EN_L

PM_SYSRST_L

SMC_PA1

SMC_PA0

SMC_XTAL

SMC_EXTAL


VOLTAGE=3.3V

PP3V3_S5_SMC_AVCC

PP3V3_S5_AVREF_SMC

SMC_TRST_L

SMC_MD1

SMC_KBC_MDE

SMC_VCL

SMC_NMI

SMC_RESET_L

PM_CLK32K_SUSCLK

SMC_WAKE_SCI_L

SMC_EXCARD_PWR_EN

PM_RSMRST_L

SMC_TDI

SMC_CASE_OPEN

LPC_AD<3>

SMC_LRESET_L

LPC_AD<1>

LPC_AD<0>

SMC_P26

SMC_P24

ESTARLDO_EN

IMVP_VR_ON

PM_SLP_S4_L

SMC_GPU_VSENSE

SMC_THRMTRIP

SMC_ADAPTER_EN

SMC_PROCHOT_3_3_L

SMC_BIL_BUTTON_L

SMC_PM_G2_EN

SMC_GPU_ISENSE

SMC_NB_MISC_ISENSE

LPC_PWRDWN_L

SMC_TX_L

PM_CLKRUN_L

SMB_MGMT_CLKLPC_CLK33M_SMC

ALS_RIGHT

SMC_NB_CORE_ISENSE

SMC_ANALOG_ID

SMS_Y_AXIS

SMS_Z_AXIS

SMC_FAN_1_TACH

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_2_TACH

49 OF 109

B.0.0

051-8568

36 OF 77

2

1

2

1

2

1

2

1

1 2

2

1

12

2

1

2

1

1

2

1

2

1

2

1

2

1

2

B13

D11

C13

C12 J11

B12

A13

A12

D10

D13

E11

D12

F11

E13

E12

F13

E10

A9

D9

C8

B7

A8

D7

D6

D4

A5

B4

A1

C2

B2

C1

C3

G2

F3

E4

L13

K12

K11

J12

K13

J10

H12

N10

M11

L10

N11

N12

M13

N13

L12

A7

B6

A6

B5

C6

J4

G3

H2

G1

H4

G4

F4

F1

D8

D5

C7

L1

N2

N3

N1

M3

M2

K3

L2

B8

C9

B9

A10

C10

B10

C11

A11

G11

G13

F12

H13

G10

G12

H11

J13

M10

N9

K10

L8

M9

N8

K9

L7

K1

J3

K2

J1

K4

K5

N5

M6

L5

M5

N4

L4

M4

M8

N7

K8

K7

K6

N6

M7

L6

E2

F2

J2

A4

B3

C4

D3

F10

E3

C5

B11

L3

D2

E1

H10

M1

B1

E5

H1

D1

H3

L9

L11

M12

A2

A3

2

1

2

1

2

1

37

37 40 41

37

8 37

37

37

37

37

37

37

7 37

37

37

D

S G

IN

OUT

OUT IN

OUT IN

IN

OUT

GND

OUTIN

02

OUTCD

GNDNC

OUTIN

IN

OUT

G

D

S

BI

IN

D

S G

D

G S

D

G S

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_ALT_ITEM


TABLE_ALT_HEAD

MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE

System (Sleep) LED Circuit

TO CPU

SMC FSB to 3.3V Level Shifting

TO SMC

RADAR 5925345

Debug Power "Button"

PLACE R5015,R5001 ON BOTTOM SIDEPLACE R5016 ON TOP SIDE

SMC AVREF Supply

SMC Reset "Button" / Brownout Detect

NC

SMC Crystal Circuit

Q5059

SOT563

SSM6N15FEAPE

R5095

402

0

MF-LF

1/16W

5%

R5070

402MF-LF5% 1/16W

10K

R5071 100K

4021/16W5% MF-LFR5072 10K

4021/16W MF-LF5%R5073

MF-LF5% 402

10K

1/16WR5074 100K

5% MF-LF1/16W 402

R5076

4021/16W5% MF-LF

100K

R5077

5%

10K

402MF-LF1/16WR5078

1/16W

10K

5% MF-LF 402R5079

5% 402MF-LF1/16W

10K

R5080

MF-LF 4025%

10K

1/16W

R5085402MF-LF1/16W5%

10K

R5086

5% 402MF-LF1/16W

10K

R5088MF-LF5% 1/16W

10K

402

R5090

5%

100K

402MF-LF1/16W

36

10 14 69

R5015

NOSTUFF

1/10W

0

MF-LF

5%

603

SILK_PART=PWR_BTN

R5091 100K

1/16W5% MF-LF 402R5092 100K

MF-LF5% 1/16W 402

36 20

36

R50891/16W MF-LF 402

10K

5%

Y5010

CRITICAL

20.00MHZ5X3.2-SM

C5011

402

50V5%

CERM

15pF

C5010

CERM

15pF

50V

402

5%

R5087 470K

5% 1/16W 402MF-LF

R5016

NOSTUFF

603

5%

MF-LF

0

1/10W

SILK_PART=PWR_BTN

36

R5032

1%1/16W

MF-LF402

1.47K

R5031

1%

523

402

1/16WMF-LF

R5030

402

80.61%

MF-LF1/16W

C5020

10%

0.47UF

402

CERM-X5R

6.3V

34

Q5030

SOD

2SA2154MFV-YAE

VR5020

REF3333

SOT23-3

CRITICAL

C5025

6.3V

X5R

10uF

20%

603

C5026

CERM

0.01UF

402

10%

16V

R5001

603

MF-LF

5%

1/10W

0

SILK_PART=SMC_RST

NOSTUFF

U5001SN74LVC1G02

SOT553-5

C5001

10%

16V

CERM

402

0.01UF

C5000

0.1uF

402

CERM

20%

10V

R5000

402

1K

MF-LF

5%

1/16W

36 38

R5051 10K

5% 1/16W MF-LF 402R5052

5%

10K

1/16W MF-LF 402

R5050

1/16W MF-LF 4025%

10K

R5053

5% 1/16W MF-LF 402

10K

R5055 10K

5% 1/16W MF-LF 402

R5054

1/16W MF-LF 4025%

10K

U5000NCP303LSNSOT23-5-HF

CRITICAL

36

R5011

402

5%1/16W

0

MF-LF

R5010

10K

5%

1/16W

MF-LF

402

36

R5060

1/16W5%

402

10K

MF-LF

Q5060

SOT-563

DMB53D0UV

R5061

MF-LF1/16W5%100K

402

Q5060

SOT-563

DMB53D0UV

R5062

1/16W5%

3.3K

402MF-LF

10 14 69

36

Q5059SSM6N15FEAPESOT563

Q5033

SSM3K15FV

SOD-VESM-HF

Q5032

SOD-VESM-HF

SSM3K15FV

36 37 44

SMC SupportSYNC_MASTER=K24_MLB SYNC_DATE=02/04/2009

ISL60002-33, INTERSILALL353S1381 353S1912

SYS_LED_L_VDIV

SYS_LED_ILIM

SMC_SYS_LED

=PP5V_S3_SYSLED

SYS_LED_ANODE

MCP_SPKR

=PP3V3_S5_SMC

SMC_RESET_L

SMC_RSTGATE_L

ALS_GAIN

NC_ALS_RIGHTMAKE_BASE=TRUE

EXCARD_OC_L

SMC_P24

SMC_P41

ALS_LEFT

MAKE_BASE=TRUE

TP_SMC_EXCARD_PWR_EN

TP_SMC_RSTGATE_LMAKE_BASE=TRUE

NC_SMC_PB3MAKE_BASE=TRUE

SMC_EXCARD_PWR_EN

SMC_BIL_BUTTON_L

MAKE_BASE=TRUE

NC_SMC_BIL_BUTTON_L

SMC_FAN_2_CTL

SMC_GFX_THROTTLE_L

SMC_FAN_1_CTL

SMC_FAN_3_CTL

NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

TP_SMC_P41MAKE_BASE=TRUE

SMC_BC_ACOK

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

PM_THRMTRIP_L

CPU_PROCHOT_L CPU_PROCHOT_L_R

CPU_PROCHOT_BUF

=PP3V3_S0_SMC

SMC_PROCHOT_3_3_L

MAKE_BASE=TRUE

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NC_ESTARLDO_EN

SMC_EXCARD_OC_L

=PP3V3_S5_SMC

MAKE_BASE=TRUE

NC_ALS_GAIN

MAKE_BASE=TRUE

TP_SMC_P24

SMC_MCP_DDR_ISENSEMAKE_BASE=TRUE

SMC_THRMTRIP

SMC_EXTAL

SMC_ONOFF_L

=PP3V3_S0_SMC

SMC_XTAL

SMC_MANUAL_RST_L

SMC_PA0

SMC_PA1


PP3V3_S5_AVREF_SMC


VOLTAGE=3.3V

SMC_BS_ALRT_L

MAKE_BASE=TRUE

SMC_MCP_VSENSE

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

=CHGR_ACOK

TP_SMC_P26MAKE_BASE=TRUE

ESTARLDO_EN

SMC_FAN_2_TACH

SMC_ONOFF_L

SMC_LID

SMC_PH2

=PP3V3_S5_SMC

PM_SLP_S5_L

SMC_EXCARD_CP

PM_SLP_S4_L

SMC_PA5

SMC_BC_ACOK

SMC_GFX_OVERTEMP_L

SMC_FAN_1_TACH

SMC_FAN_3_TACH

SMC_CASE_OPEN

SMC_ADAPTER_EN

SMC_NB_MISC_ISENSE

SMC_GPU_ISENSE

SMC_PROCHOT

MAKE_BASE=TRUE

NC_SMC_ANALOG_IDSMC_ANALOG_ID

SMC_GPU_VSENSE

SMC_P26

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

SMC_NB_DDR_ISENSE

SMC_NB_CORE_ISENSE

ALS_RIGHT

SMC_PB3

SMC_MCP_SAFE_MODE

MAKE_BASE=TRUE

SMS_INT_L=SMC_SMS_INT

SMC_ONOFF_L


VOLTAGE=0V

GND_SMC_AVSS


=PPVIN_S5_SMCVREF

SMC_TPAD_RST_L

SMC_TPAD_RST

SYS_LED_L

SMC_TX_L

SMC_RX_L

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

=PP3V3_S5_SMC

50 OF 109

B.0.0

051-8568

37 OF 77

3

45

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1 2

1 2

1 2

2

1

1 2

1 2

1 2

1

2

1

2

1

2

1

2

2

1

3

1

2

3

21

2

1

2

1

1

2

4

2

1

3

5

2

1

2

1 1

2

1 2

1 2

1 2

1 2

1 2

1 2

1

3

5

4 2

1 2

1

2

1

2

6

2

1

1

2

4

5

3

1 2

6

12

12

3

12

3

8

21

8 36 37

36

36

36

36

36

36

36

36

36

36

36

36 37 54

21

8 37

8 36 37

41

36

8 37

36

36

36

7 36

36

40

41

55

36

36

36 37 44

36 44 54

36

8 36 37

36

36

7 21 36 62

36

36 37 54

36

36

36

36

21 32 36

36

36

36

36

36

41

36

36

36

36

36 37 44

36 40 41

8

44

35 36 38

35 36 38

36 38

36 38

36 38

36 38

8 36 37

IN

BI

IN

OUT

OUT

OUT

BI

BI

IN

OUT

IN

OUT

OUT

IN

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

BI

IN

IN

BI

IN

OUT

IN

OUT

IN

OUT

OUT

IN

BI

VCC

GND

B1

A

S

B0

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

SEL LOW OUTPUTS TO B0 (FRANKCARD ROM)

SEL HIGH OUTPUTS TO B1(ON BOARD ROM)

Pull-up on debug card

Alternate SPI ROM Support

LPC+SPI Connector

516S0573

38

19 36

19 36

36 37

36 37

36 37

J510055909-0374

CRITICAL

LPCPLUS

M-ST-SM

19 36 72

19 36 72

38 72

38 72

19 36 72

19 36

36 37

25

36 37

36

36

35 36 37

18

36

35 36 37

38

38 48 38 48

25 72

R5144

402MF-LF

20K5%

1/16W

19 36 72

C51240.1UF

402CERM10V20%

LPCPLUS

R5190

MF-LF

5%1/16W

402

10K

21 72

21 38 48 72

19 36 72

21 38 48 72

21 48 72

R5146

402

0

1/16W5%

MF-LF

LPCPLUS_NOT

PLACEMENT_NOTE=PLACE NEXT TO U5110

R5157

402

0

MF-LF1/16W

LPCPLUS

5% PLACEMENT_NOT=PLACENEXT TO WHERE IT BRANCHES INTO TWO

R51560

MF-LF

5%

1/16W

402

LPCPLUS

PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO

R5158

402

1/16W5%

MF-LF

0

LPCPLUS

PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO

21 38 48 72

R519110K

1/16W

402MF-LF

5%

38

21 38 48 72

38 72

38 72

38 72

21

R5140

1/16W5%

402

MF-LF

100K

U5110

CRITICAL

NC7SB3157P6XGSC70

LPCPLUS

38 72


LPC+SPI Debug Connector

MAKE_BASE=TRUESPIROM_USE_MLB

SPI_ALT_CS_L

SPI_ALT_MOSI

SPI_ALT_CLK SPI_CLK_R

LPCPLUS_GPIO

SMC_RX_LSMC_TX_L

SPI_MOSI_R

SPI_MLB_CS_L

SPI_MLB_CS_L=SPI_CS1_R_L_USE_MLB

=PP3V3_S5_ROM

SPI_MISO

SPI_MOSI_R

=PP3V3_S5_ROM

SPI_CLK_R

SPI_ALT_MISO

SMC_MD1

=PP5V_S0_LPCPLUS

SMC_NMI

SMC_TMS

DEBUG_RESET_L

SMC_TRST_L

SMC_TDO

LPC_AD<1>

LPC_AD<0>

SPI_ALT_MOSI

PM_CLKRUN_L

LPC_FRAME_L

SPI_ALT_MISO

=PP3V3_S5_LPCPLUS

SMC_RESET_L

LPC_AD<2>

LPC_CLK33M_LPCPLUS

LPC_AD<3>

SPIROM_USE_MLB

SPI_ALT_CLK

SPI_ALT_CS_L

LPC_SERIRQ

LPC_PWRDWN_L

SMC_TDI

SMC_TCK

SPI_CS0_R_L

=PP3V3_S5_LPCPLUS

51 OF 109

B.0.0

051-8568

38 OF 77

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

3

1

5

9

7

15

11

13

17

19

21

23

25

27

29

31 32

33 34

1

2

2

1

1

2

1 2

1 2

1 2

1 2

1

2

1

2

25

16

4 3

38

8 38 48

8 38 48

8

8 38

8 38




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Battery

Battery Manager - (Write: 0x16 Read: 0x17)

Battery Temp - (Write: 0x90 Read: 0x91)

The bus formerly known as "Battery B"

SMC "Management" SMBus Connections

ISL6258A - U7000

MCP79 SMBUS "1" CONNECTIONS

SMCU4900

SMC "B" SMBUS

U4900

(Write: 0x98 Read: 0x99)

MCP SMBUS1 ACTS AS SLAVE DEVICE FOR MCPSMC_DIGITEMP_YES STUFFED

U4900


Mikey

(WRITE: 0X72 READ: 0X73)

U6880


(Write: 0xA2 Read: 0xA3)

SO-DIMM "B"

U6880


SMC

(SLAVE: WRITE:0XE0 READ:0XE1)

MCP79

(MASTER)

(MASTER)

U1400

U4900

Mikey

SMC

SMC

(Write: 0xA0 Read: 0xA1)

(MASTER)

BATTERY

U6000


SENSOR ADC

EMC1403-5: U5535

MCP Temp TRACKPAD



(MASTER)

U4900


Margin Control

Vref DACsU2900

U2901

U4900

(MASTER)

(MASTER)

(MASTER)

J3100

J3200

SO-DIMM "A"

CPU TempEMC1403-5: U5515

SMC "B" SMBus Connections

SMCJ5800

SMC "A" SMBus ConnectionsNOTE: SMC RMT bus remains powered and may be active in S3 state

J6950

U1400

SMC "Battery A" SMBus Connections

Battery Charger

(See Table)

MCP79 SMBUS "0" CONNECTIONS

(MASTER)

SMC "B" SMBUS SIGNALS ALSO GET CONNECTED TO MCP SMBUS 1 CONNECTIONS(SEE LEFT SIDE)

MCP79

SMC "0" SMBus Connections

SMC

SENSOR ADC CAN ONLY WORK IN S0 AS IT HAS I2C BUS PULLED UP TO S0 POWER RAIL

R5200

402

2.0K5%

1/16W

MF-LF

R52012.0K

402MF-LF

1/16W5%

R5280

MF-LF

1/16W5%

1K

402

R52811K

MF-LF

1/16W5%

402

R5261

402

5%1/16W

MF-LF

2.0K

R5260

402

2.0K5%

1/16W

MF-LF

R52711K5%

402MF-LF

1/16W

R5270

MF-LF

1K

1/16W5%

402

R52514.7K

MF-LF

5%1/16W

402

R52504.7K

402MF-LF

5%1/16W

R5231MCPSMC_DIGITEMP_NO

2.0K5%1/16WMF-LF

402

R5230

MCPSMC_DIGITEMP_NO

5%

2.0K

MF-LF402

1/16W

R5290

402

5%1/16W

4.7K

MF-LF

R5291

5%

MF-LF

402

1/16W

4.7K

R5204

1/16W5%0

402MF-LF

MCPSMC_DIGITEMP_YES

R5203

MF-LF

5%1/16W

0MCPSMC_DIGITEMP_YES

402

R5232

402

1/16W

0

MF-LF

5%

MCPSMC_DIGITEMP_NO

R5233

402

5%1/16WMF-LF

MCPSMC_DIGITEMP_NO

0

R5234

402MF-LF1/16W

0MCPSMC_DIGITEMP_YES 5%

R5235

402MF-LF1/16W5%

MCPSMC_DIGITEMP_YES

0


K84 SMBUS CONNECTIONSSYNC_MASTER=K24_MLB

=SMBUS_BATT_SCL

SMBUS_SMC_0_S0_SCLMAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA=I2C_SODIMMA_SDA

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

SMB_B_S0_DATA

SMB_B_S0_CLK


MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

SMBUS_MCP_1_DATA

=I2C_MIKEY_SCL

SMBUS_MCP_1_CLK

=I2C_CPUTHMSNS_SCL

=I2C_VREFDACS_SCLMAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCLSMB_MGMT_CLK

=I2C_VREFDACS_SDASMB_MGMT_DATA

SMB_BSA_CLK

=I2C_MIKEY_SDA

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

I2C_MIKEY_SDA_R

=I2C_SODIMMA_SCL

=I2C_CPUTHMSNS_SDA

=I2C_SMC_ADCS_SCL

=I2C_MCPTHMSNS_SDA

=I2C_MCPTHMSNS_SCL

=PP3V3_S0_SMBUS_SMC_B_S0

=I2C_TPAD_SCL

=I2C_TPAD_SDA

SMB_A_S3_CLK

SMB_0_S0_DATA

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_SMBUS_SMC_A_S3

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

I2C_MIKEY_SCL_R

SMB_BSA_DATA

I2C_MIKEY_SCL_R

SMB_A_S3_DATA

SMBUS_SMC_B_S0_SCLMAKE_BASE=TRUE

=SMBUS_BATT_SDA

=PP3V42_G3H_SMBUS_SMC_BSA

SMB_B_S0_CLK

SMBUS_SMC_BSA_SDAMAKE_BASE=TRUE

=SMBUS_CHGR_SDA

=SMBUS_CHGR_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMBUS_SMC_A_S3_SCLMAKE_BASE=TRUE


MAKE_BASE=TRUE

I2C_MIKEY_SDA_R

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDASMB_B_S0_DATA

=I2C_SMC_ADCS_SDA

MAKE_BASE=TRUE

SMBUS_MCP_0_CLK

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

=PP3V3_S0_SMBUS_SMC_0_S0

SMB_0_S0_CLK

52 OF 109

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051-8568

39 OF 77

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1 2

1

2

1

2

54

74

74 27

28

28

36 39

36 39

8

74

21 72

39 53

21 72

42

26 74 36

26 36

36

39 53

39 53

39 53

39

27

42

47

42

42

8

45

45

36

36

26

26

8

8

39

36

39

36

74

54

8

36 39

55

55

8

39

74 36 39

47

13 21 72

13 21 72

8

36

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PBUS VOLTAGE SENSE ENABLE & FILTER

Enables PBUS VSense

Place RC close to SMC

RTHEVENIN = 4573 OHMS



divider when high.

CPU Voltage Sense / Filter

MCP Voltage Sense / Filter

37

C5359

402

0.22UF

6.3V

X5R

20%

R5359

1%

4.53K

1/16W

MF-LF

402

62

R5316

1%

1/16W

402

100K

MF-LF

R5315

MF-LF

100K

402

1%

1/16W

36

C5385

402

6.3V

20%

X5R

0.22UF

R5385

1%

402

MF-LF

1/16W

27.4K

R5386

1%

1/16W

MF-LF

402

5.49K

Q5315

SOT-963NTUD3169CZ

XW5359

PLACEMENT_NOTE=Place near U1400 center

SM

36

R53094.53K

1/16W

1%

402

MF-LF C5309

402

0.22UF20%

6.3V

X5R

XW5309

PLACEMENT_NOTE=Place near U1000 center

SM


VOLTAGE SENSING

PBUSVSENS_EN_L_DIV


PPBUS_G3HRS5_VSENSE

VOLTAGE=18.5V

PBUSVSENS_EN_L

=PBUSVSENS_EN

=PPBUS_G3HRS5

=PPVCORE_S0_MCP_VSENSE

GND_SMC_AVSS

SMC_PBUS_VSENSE

GND_SMC_AVSS

CPUVSENSE_IN SMC_CPU_VSENSE

GND_SMC_AVSS

=PPVCORE_S0_CPU_VSENSE

MCPVSENSE_IN SMC_MCP_VSENSE

53 OF 109

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051-8568

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2

1

1 2

1

2

1

22

1

1

2

1

2

6

2

1

3

5

4

1 2

1 2

2

1

1 2

8

8

36 37 40 41

36 37 40 41

36 37 40 41

8

OUT

IN

OUT

V+

REFIN+

IN- OUT

GND

OUTIN

OUT

OUTININ OUT

IN OUT

IN




36

BRANCH

REVISION

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE



MCP MEM VDD Current Sense

MCP VCore Current Sense Filter

PLACE R5401 AND C5490 CLOSE TO SMC

MCP MEM VDD Current Sense Filter


CPU VCore Load Side Current Sense / FilterPlace RC close to SMC

Gain: 50x

DC-IN (BMON) CURRENT SENSE DC-IN (AMON) CURRENT SENSE

37

C54720.22UF

6.3V

20%

X5R

402

63

37

C5435

MEM_SENSE

20%

6.3V

402

0.22UF

X5R

C5417

1P05_HIGH_SIDE_SENSE20%10V

402

0.1uF

CERM

U5402

1P05_HIGH_SIDE_SENSE

SC70INA213

8

R54921P05_HIGH_SIDE_SENSE

1W

0.5%

0.01

MF

0612-1

8

37

C5436

1P05_HIGH_SIDE_SENSE

6.3V

20%

402

X5R

0.22UF

36 55

R54181P05_HIGH_SIDE_SENSE

1%

402

1/16W

4.53K

MF-LF

R5416

1%

1/16W

MF-LF

402

4.53K

R5417

MEM_SENSE

4.53K

1/16W

1%

402

MF-LF

55

R5401

MF-LF

1%

1/16W

402

4.53K

C5490

X5R

20%

6.3V

402

0.22UF

36

C5470

20%

402

6.3V

0.22UF

X5R

58

R5480

1/16W

1%

402

MF-LF

17.4K

R5471

1%

MF-LF

6.19K

1/16W

402

36

R54814.53K

MF-LF

1/16W

402

1%

C5487

402

0.22UF20%

6.3V

X5R

63

Q5401

MEM_SENSE

2SA2154MFV-YAESOD

R5410MEM_SENSE

1/16W

0

MF-LF

5%

402

R5411

MF-LF

MEM_SENSE

0

402

5%1/16W

R5412

402MF-LF

1%118

1/16WMEM_SENSE

C5434MEM_SENSE

402

0.1UF

10%

X5R16V

C54000.1uF

MEM_SENSE

10VCERM

402

20%

U5400

MEM_SENSE

SC70-5OPA348

Current SensingSYNC_DATE=01/27/2009SYNC_MASTER=K24_MLB

P1V5_S0_SENSE_AMPP1V5_S0_SENSE_B

P1V5_S0_SENSE_E

P1V5_S0_SENSE

CHGR_BMON

=PP3V3_S0_MCPDDRISNS

ISNS_CPUVTT_P

ISNS_CPUVTT_N

=PPCPUVCORE_VTT_ISNS_R

MCPCORES0_IMON

P1V5_S0_KELVIN

=PP3V3_S0_CPUVTTISNS

=PPCPUVCORE_VTT_ISNS

SMC_DCIN_ISENSE

GND_SMC_AVSS

SMC_BATT_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

GND_SMC_AVSS

GND_SMC_AVSS

IMVP6_IMON SMC_CPU_ISENSE

CPUVTT_IOUT

SMC_MCP_DDR_ISENSE

GND_SMC_AVSS

P1V5_S0_SENSE_C

SMC_CPU_FSB_ISENSE

CHGR_AMON

SMC_MCP_CORE_ISENSE

54 OF 109

B.0.0

051-8568

41 OF 77

2

1

2

1

2

1

23

14

5 6

43

21

2

1

1 2

1 2

1 2

1 2

2

1

2

11

2

1 2

1 2

2

1

2

1

3

1

2

1 2

1

2

1 2

2

1

4

1

3

5

2

8

75

75

59

8

36 37 40 41 36 37 40 41

36 37 40 41

36 37 40 41

36 37 40 41

36 37 40 41

BI

BI

BI

BI

BI

BI

BI

BI

THRM_PADDN2/DP3

DP2/DN3

VDD

SMDATA

SMCLKGND

DN1

DP1 THERM*/ADDR

ALERT*

THRM_PADDN2/DP3

DP2/DN3

VDD

SMDATA

SMCLKGND

DN1

DP1 THERM*/ADDR

ALERT*




36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

APN 353S2571

MCP T-Diode Thermal SensorINTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

APN 353S2571

PLACEMENT NOTE: PLACE U5515 NEAR CPU

CPU T-Diode Thermal Sensor

DETECT FIN-STACK TEMPERATURE

DETECT MCP DIE TEMPERATURE

PLACEMENT NOTE: PLACE U5535 NEAR MCP

DETECT CPU DIE TEMPERATURE

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE

DETECT HEAT-PIPE TEMPERATURE

C5540

MCP_T_DIODE_SENSOR

50V

402

10%

CERM

SIGNAL_MODOL=EMPTY

0.0022uF

39

39

R5517

402

1/16W5%

MF-LF

10K

R5516

1/16W1%

402

MF-LF

10K

R5537

MCP_T_DIODE_SENSOR

10K

MF-LF

5%

1/16W

402

R5536

MCP_T_DIODE_SENSOR

1%

MF-LF1/16W

10K

402

39

39

C5535

MCP_T_DIODE_SENSOR

10V

CERM402

20%0.1uF

C55210.0022uF

SIGNAL_MODOL=EMPTY

10%50V

CERM402

C5522

MCP_T_DIODE_SENSOR

402

50V10%

CERM

SIGNAL_MODOL=EMPTY

0.0022uF

10 75

10 75

21 75

21 75

Q5501

SOT732-3BC846BMXXH

U5515

CRITICAL

DFNEMC1413

U5535

MCP_T_DIODE_SENSOR

DFN

CRITICAL

EMC1413

Q5502

MCP_T_DIODE_SENSOR

SOT732-3BC846BMXXH

PLACEMENT_NOTE=PLACE CLOSE TO J4501 IN A CONVENIENT LOCATION

C5515

10VCERM402

20%

0.1uF

R551547

5%1/16W

MF-LF402

C5520

SIGNAL_MODOL=EMPTY

50V

402

0.0022uF10%

CERM

R5535MCP_T_DIODE_SENSOR

5%

MF-LF

402

1/16W

47


Thermal Sensors

=PP3V3_S0_MCPTHMSNS

=I2C_MCPTHMSNS_SDA

MCP_THMDIODE_P

MCPTHMSNS_THERM_L

MCPTHMSNS_ALERT_L

PP3V3_S0_CPUTHMSNS_R



=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCL

CPU_THERMD_N

CPU_THERMD_P

CPUTHMSNS_THERM_L

CPUTHMSNS_ALERT_L

=PP3V3_S0_CPUTHMSNS

CPUTHMSNS_D2_N

CPUTHMSNS_D2_P

=I2C_MCPTHMSNS_SCL

MCPTHMSNS_D2_N

PP3V3_S0_MCPTHMSNS_RMIN_LINE_WIDTH=0.25 mm


MCP_THMDIODE_N

MCPTHMSNS_D2_P

55 OF 109

B.0.0

051-8568

42 OF 77

2

1

1

2

1

2

1

2

1

2

2

1

2

1

2

1

1

2

3

11

5

4

1

9

10

6

3

2 7

8

11

5

4

1

9

10

6

3

2 7

8

1

2

3

2

1

1 2

2

1

1 2

8

8

75

75

75

75

D

GS




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

5V DCTACH

MOTOR CONTROLGND

518S0521

NC

NC

R5665

402MF-LF

5%1/16W

47K

R566047K1/16WMF-LF

402

5%

R5661100K

402MF-LF1/16W

5% Q5660

SOD-VESM-HFSSM3K15FV

J5601M-RT-SM

78171-0004

CRITICAL


Fan

FAN_RT_PWM

=PP5V_S0_FAN_RT

=PP3V3_S0_FAN_RT

SMC_FAN_0_CTL

FAN_RT_TACHSMC_FAN_0_TACH

56 OF 109

B.0.0

051-8568

43 OF 77

1 2

1

2

1

2

12 3

5

1

2

4

6

3

7

8

8

36

7 36

D

G S

P2_4

P2_6

VDD

P0_4

P0_2

P2_0P2_2P

0_0

P2_3P2_1P4_7P4_5P4_3P4_1P3_7P3_5P3_3P3_1P5_7P5_5P5_3P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSS

D+D-VDD

P7_0

P1_0

P1_2

P1_4

P1_6 P5_0

P5_2P5_4P5_6P3_0P3_2P3_4

P4_0P4_2P4_4P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PADTHRML

(SYM-VER2)

P0_1

Y

C

B

A

IN

OUT

IN

Y

B

A

Y

B

A

Y

B

A

NC

NC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_ALT_ITEM


TABLE_ALT_HEAD

SMC_MANUAL_RESET LOGIC

PSOC USB CONTROLLER

APN 337S2983

KEYBOARD CONNECTOR

NC

ISSP SCLK/I2C SCL

ISSP SDATA/I2C SDA

60MA MAX

VDD 8MA (TYP)

0.2 OHM

0.021 V

0.0188 V4.7 OHM4MA (MAX)

96E-6 W

16.32E-6 W

0.012 V

36E-3 W

0.72E-3 W

60MA MAX

14MA (MAX)

3V3 LDO

0.0255 V

0.6 V

0.204 V

SPI HOST TO Z2

TMP102

PLACE C5704, C5705 & C5706

VDD PIN 49

TPAD BUTTONS DISABLE

ISOLATION CIRCUIT

PLACE THESE COMPONENTS CLOSE TO J5800

THE TPAD BUTTONS WILL BE DISABLE

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

WHEN THE LID IS CLOSED

LID OPEN => SMC_LID_LC ~ 3.42V

LID CLOSE => SMC_LID_LC < 0.50V

APN 518S0637

TO MLB CONNECTOR

USB INTERFACES TO MLB

75.2E-6 W

294E-6 W

0.255E-6 W

0.012 V

POWERV_SNS

1.5 OHM

10 OHM

2.55 KOHM

R_SNS

10UA

80UA

CURRENT

VIN

VOUT

V+

PIN NAMEIC

PSOC

18V BOOSTER

CLOSE TO U5701

VDD

APN 311S0406

KEYBOARD SCANNER

TRACKPAD PICK BUTTONS

VDD PIN 22

Alternate Parts

CLOSE TO U5701

PLACE C5701, C5702 & C5703

U5701 CHIP DECOUPLING

Q5701

SSM3K15FV

SOD-VESM-HF

C5758

X7R-CERM

0.1UF10%

402

16V

R5771

402

MF-LF

33K

5%

1/16W

R577033K

402

MF-LF

5%

1/16W

R5769

402

MF-LF

1/16W

5%

33K

C57064.7UF20%6.3V

X5R

603

C5705

402

0.1UF

X7R-CERM

16V10%

C5704

5%

100PF

50V

CERM

402

PLACEMENT_NOTE=PLACE C5704 CLOSE TO U5701 VDD PIN 49

C57030.1UF10%

402

X7R-CERM

16V

C5702

402

CERM

50V5%

100PF

PLACEMENT_NOTE=PLACE C5702 CLOSE TO U5701 VDD PIN 22

C5701

20%

X5R

603

6.3V

4.7UF

R570224

402

5%1/16W

MF-LF

U5701

CRITICAL

MLF

CY8C24794

OMIT

R570124

1/16W

5%

MF-LF

402

U5703

SC70

SN74LVC1G10

CRITICAL

R5704

MF-LF

5%

1.5

1/16W

402

36 37 54

C57100.1UF

CERM

402

10V

20%


R5710

402

MF-LF

1/16W

5%

1K

R5714

402

1%

1/16W

MF-LF

113

R571510K

1%

1/16W

402

MF-LF

J5713CRITICAL

FF14-30A-R11B-B-3H

F-RT-SM

U5726

CRITICALTC7SZ08AFEAPE

SOT665

U5727

CRITICAL

SOT665

TC7SZ08AFEAPE

C5727

402

CERM

10V

20%

0.1UF

C5726

402

0.1UF

20%

CERM

10V

U5725

CRITICAL

SOT665

TC7SZ08AFEAPE

C5725

402

10V

20%

CERM

0.1UF


WELLSPRING 1

311S0406 311S0447 ALL NXP PART AS ALTERNATE

WS_KBD15_C

WS_KBD16_NUM

SMC_ONOFF_L

TP_P7_7TP_ISSP_SCLK_P1_1

WS_KBD15_CAP

WS_KBD1

PSOC_MISO

WS_KBD13

WS_KBD12

WS_KBD8

WS_KBD23

Z2_RESET

WS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KEY

USB_TPAD_R_N

DIFFERENTIAL_PAIR=USB2_TPAD

WS_KBD4

TP_ISSP_SDATA_P1_0

Z2_CLKIN

WS_KBD14

PP3V3_S3_PSOC

WS_KBD11

PICKB_L

=PP3V3_S3_TPAD

WS_KBD2

WS_KBD3

WS_KBD4

WS_LEFT_SHIFT_KEY

WS_CONTROL_KEY

=PP3V42_G3H_TPAD

PSOC_F_CS_L

WS_CONTROL_KBD

WS_KBD6

SMC_LID

BUTTON_DISABLE

WS_KBD17

WS_KBD16N

WS_KBD8

WS_KBD2

WS_KBD5

WS_KBD6

WS_KBD18

WS_KBD17

WS_KBD14

WS_KBD11

WS_KBD10

WS_KBD9

WS_KBD21

WS_KBD20

WS_KBD19

WS_KBD22

WS_LEFT_SHIFT_KBD

=PP3V42_G3H_TPAD

WS_LEFT_OPTION_KBD

WS_CONTROL_KBD

WS_KBD7

TP_PSOC_SDA

PP3V3_S3_PSOC

TP_PSOC_SCL

WS_KBD22

USB_TPAD_P

WS_KBD5

=PP3V3_S3_TPAD

WS_KBD15_C

WS_KBD12

WS_KBD10

WS_KBD9

WS_KBD3

TP_PSOC_P1_3

WS_KBD13

WS_KBD23

WS_KBD21

WS_KBD19

WS_KBD7

WS_KBD18

SMC_TPAD_RST_L

USB_TPAD_R_P

DIFFERENTIAL_PAIR=USB2_TPAD

=PP3V42_G3H_TPAD

=PP3V42_G3H_TPAD

WS_KBD20

WS_LEFT_OPTION_KBD

BUTTON_DISABLE

WS_KBD1

=PP3V42_G3H_TPAD

=PP3V3_S3_TPAD

WS_LEFT_OPTION_KBD

=PP3V3_S3_TPAD

USB_TPAD_N

Z2_DEBUG3

TP_P4_5

Z2_KEY_ACT_L

PSOC_MOSI

WS_CONTROL_KBD

=PP3V3_S3_TPAD

WS_LEFT_SHIFT_KBD


MIN_LINE_WIDTH=0.50MMPP3V3_S3_PSOC

Z2_HOST_INTN

WS_LEFT_SHIFT_KEY

WS_LEFT_OPTION_KEY

Z2_CS_L

Z2_MISO

Z2_SCLK

PSOC_SCLK

Z2_MOSI

WS_CONTROL_KEY

WS_KBD16N

WS_KBD_ONOFF_L

57 OF 109

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051-8568

44 OF 77

12

3

2

1

1

2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

2

1

1 2

57

44

47

48

52

51

50

49

42

41

39

40

37

38

36

35

34

33

32

31

30

2928

26

27

25

24

23

22

21

20

19

18

17

16

15

1

2

4

3

7

5

6

8

9

10

11

12

14

13

45

46

43

53

54

55

56

1 2

6

3

1

2

5

4

1 2

2

1

1 2

1 2

1 2

21

22

32

31

1

2

5

4

3

6

7

10

9

8

20

19

17

18

16

15

14

13

12

11

23

24

25

26

27

28

29

30

3

5

1

4

2

3

5

1

4

2

12

12

3

5

1

4

2

12

44

7

36 37

7

7 44

7 45

7 44

7 44

7 44

7 44

7 45

7 44

44

72

7 44

7 45

7 44

44

7 44

7 45

7 44

7 44

7 44

44

44

8 44

7 45

7 44

7 44

44

7 44

44

7 44

7 44

7 44

7 44

7 44

7 44

7 44

7 44

7 44

7 44

7 44

7 44

7 44

7 44

7 44

8 44

7 44

7 44

7 44

44

7

44

20 72

7 44

8 44

44

7 44

7 44

7 44

7 44

7 44

7

44

7

44

7

44

7 44

7

44

37

72

8 44

8 44

7

44

7 44

44

7 44

8 44

8 44

7 44

8 44

20 72

7 45

7 45

7 45

7 44

8 44

7 44

44

7 45

44

44

7 45

7 45

7 45

7 45

7 45

44

44

7

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD GND

VDD

VOUTGND

CE




36

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REVISION

DRAWING NUMBER SIZE

DR


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PAGE TITLE

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D

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

3V3 LDO FOR IPD

APN 353S1364

NC

APN 516S0689

- POWER CONSUMPTION

- DROOP LINE REGULATION

BOOSTER DESIGN CONSIDERATION:

- R5812,R5813,C5818 MODIFIED

- STARTUP TIME LESS THAN 2MS

- 100-300 KHZ CLEAN SPECTRUM

- RIPPLE TO MEET ERS

BOOSTER +18.5VDC FOR SENSORS

APN 371S0313

APN 152S0504

APN 353S1401

IPD FLEX CONNECTOR

PP5V_S3_VR

VR5802

MM3243DRRE

C58532.2UF10%

PP3V3_S3_LDO

R5873

1%

402MF-LF1/16W

10

PP3V3_S3_LDO_R

=PP5V_S3_TPAD

BOOST_FB

0.20MM

0.50MM

0.20MM

0.50MM

INPUT_SW

Z2_DEBUG3

Z2_MISO

Z2_SCLK

Z2_HOST_INTN

Z2_CLKIN

0.20MM

PP18V5_S30.50MMPP3V3_S3_LDO 0.50MM

0.20MM

=I2C_TPAD_SDA

PICKB_L

Z2_KEY_ACT_L

Z2_MOSI

Z2_BOOST_EN

PSOC_MISO

Z2_CS_L

SWITCH_NODE=TRUE


MIN_LINE_WIDTH=0.50MM

BOOST_SW PP18V5_S3_SWMIN_LINE_WIDTH=0.50MM


Z2_BOOST_EN

PSOC_F_CS_L

=I2C_TPAD_SCL

PSOC_SCLK

PSOC_MOSI

PP18V5_S3

Z2_RESET

=PP5V_S3_TPAD


PP5V_S3_BOOSTERMIN_LINE_WIDTH=0.50MM


WELLSPRING 2


CERM

402

10V

20%

0.1UF

C5800

71.5K

1/16W

MF-LF

1%

402

R5813

MF-LF

1/16W

1%

402

1M

R5812

50V

5%

CERM

402

39PF

C5818

4.7UF

603

X5R

6.3V

20%10%16V

402

X7R-CERMMLF

CRITICAL

603

16V

X5R

100K

402

1/16W

MF-LF

1%

R5811

CRITICAL

VLF3010AT-SM-HF

3.3UH-870MA

L5801

QFN

TPS61045

CRITICAL

U5805

16V

X5R

603

10%

2.2UF

C5817

5%

1/16W

MF-LF

402

0

R5805

402

10%

X7R-CERM

16V

0.1UF

C5816

402

5%

0

MF-LF

1/16W

R5806

603-1

10%

25V

X5R

1UF

C5819

CRITICAL

SOD-323

B0520WSXG

D5802

CRITICAL

55560-0228

M-ST-SM

J5800

C5854

=PP3V3_S3_TPAD_LDO

0.1UF

C5838MF

1/6W

1%

402-HF

0.2R5836

1/16WMF-LF402

0

5%

R5888NOSTUFF

58 OF 109

B.0.0

051-8568

45 OF 77

22

20

18

16

14

12

10

8

6

4

2

3

21

19

17

15

13

11

9

7

5

1

2

1

1 2

2

1

12

2

1

5

7 69

1

2

3

4

8

1

2

2

1

2

3

4

1

12

2

1

2

1

1 2

2

1

1

2

1

2

2

1

1 2

45 7

45 8

44 7

44 7

44 7

44 7

44 7

45 7 45 7

39

44 7

44 7

44 7

45 7

44 7

44 7

45 7

44 7

39

44 7

44 7

45 7

44 7

45 8

OUT

OUT

OUT

IN

GND

SEL0

VDD

ST

SEL1

DNC

AZ

AY

AX

AMUX

NCNC




36

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DR


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PAGE TITLE

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Apple Inc.

PAGE


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345678

D

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8 7 5 4 2 1

Desired orientation when

placed on board top-side:

Circle indicates pin 1 location when placed

in correct orientation

+Y

+XFront of system

Analog SMS

+Z (up)

R5921 PULLS UP SEL PINS TO ENTER STANDBY MODE WHEN PIN IS NOT BEING DRIVEN BY SMC

C4950-C4952 CAP VALUES WILL BE USED TO GET CUT-OFF FREQUENCY OF ~146HZ

C5923

NOSTUFF

16VX5R

0.033UF

402

10%

36

36

36

C5922

16V10%

X5R402

0.1UF

36

U5920BMA141

LGA

CRITICAL

C5926

402

16V

0.01UF10%

CERM

C5924

NOSTUFF

10%

X5R16V

0.033UF

402

C5925

NOSTUFF

402

16V10%0.033UF

X5R

R5922

MF-LF

10

402

5%1/16W

R5921

MF-LF

10K

402

1/16W5%

SMS

SMS_ONOFF_LMAKE_BASE=TRUE

SMS_PWRDN

PP3V3_S3_SMS_FILT

=PP3V3_S3_SMS

SMS_Y_AXIS

SMS_X_AXIS

SMS_Z_AXIS

59 OF 109

B.0.0

051-8568

46 OF 77

2

1

2

1

4

12

1 2

3

5

6

7

8

9

10

11

2

1

2

1

2

1

1 2

1

2

8

COM

GNDTHRM

DVDDAVDD

AD0

AD1

SDA

SCL

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

VREF

REFCOMP

PAD

BI

IN

IN

IN

V+

REFIN+

IN- OUT

GND

+IN

-IN

V+

V-

+IN

-IN

V+

V-

+IN

-IN

V+

V-

+IN

-IN

V+

V-

IN

IN

IN

IN

IN

IN

IN

IN




36

BRANCH

REVISION

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DR


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PAGE TITLE

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Apple Inc.

PAGE


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8 7 5 4 2 1

DIVIDER: 1/22

GAIN: 273X

GAIN: 845X

GAIN: 561XGAIN: 1239X

DIVIDER: ~ 2/5DIVIDER: ~ 2/3

ADC RANGE: 0V TO 4.096V

I2C ADDRESS: 0X10 / 0X11

GAIN: 200X

LSB: 0.001V

U6000

QFN

DEBUG_ADC

LTC230939

R6060

DEBUG_ADC

412

MF-LF1/16W1%

402

C6074DEBUG_ADC

6.3V10%2.2UF

PLACEMENT_NOTE=PLACE RC NEAR U6000

X5R402

R6074

DEBUG_ADC

226K

1/16W1%

402MF-LF

39

67 75

67 75

C6050

402

20%0.1UF

CERM10V

DEBUG_ADC

C6082DEBUG_ADC


6.3V10%

X5R

2.2UF

402

R6082

DEBUG_ADC

226K

1%

MF-LF1/16W

402

XW6080OMIT

SM

PLACEMENT_NOTE=PLACE NEAR D9710

C6005DEBUG_ADC

6.3V20%

603X5R

10UF

R6080

DEBUG_ADC

MF-LF

1M

402

1/16W1%

R6081

MF-LF

DEBUG_ADC

47.0K1%1/16W

402

U6050

DEBUG_ADC

SC70INA210

R600133

PLACEMENT_NOTE=PLACE CLOSE TO U4900

DEBUG_ADC

402

5%1/16WMF-LF

R6002 PLACEMENT_NOTE=PLACE CLOSE TO U4900

33

5%1/16W

402MF-LF

DEBUG_ADC

U6040OPA330SC70-5

DEBUG_ADC

U6041DEBUG_ADC

SC70-5OPA330

U6030OPA330SC70-5

DEBUG_ADC

U6031DEBUG_ADC

SC70-5OPA330

C6003DEBUG_ADC

10UF

603X5R6.3V20%

C6041

402

20%10VCERM

0.1UF

DEBUG_ADC

C6031

402

DEBUG_ADC

10V20%

CERM

0.1UF

R6003DEBUG_ADC

5%

10

1/16W

402MF-LF

R6004

MF-LF402

5%1/16W

10

DEBUG_ADC

C6001DEBUG_ADC

6.3VX5R603

20%10UF

XW6010OMIT

SM

PLACEMENT_NOTE=PLACE NEAR Q3450

XW6020OMIT

SM

PLACEMENT_NOTE=PLACE NEAR Q4590

R6010

MF-LF1/16W1%634K

402

DEBUG_ADC

R60111M

402

1%1/16WMF-LF

DEBUG_ADC

R6012

DEBUG_ADC

226K

MF-LF1/16W1%

402 C6012

6.3V

DEBUG_ADC

10%2.2UF

X5R402


C6022


10%2.2UF

X5R6.3V

402

DEBUG_ADC

R6022

DEBUG_ADC

MF-LF

226K

1/16W1%

402

R6020

402

1/16WMF-LF

1M

DEBUG_ADC

1%

R6021

MF-LF

681K

402

DEBUG_ADC

1%1/16W

C6002DEBUG_ADC

0.1UF

10V20%

402CERM

30 75

C6032

402CERM

10%50V

DEBUG_ADC

470PF

R6032DEBUG_ADC

1/16W1%

402MF-LF

301K

C6033

DEBUG_ADC

402

10%

CERM

470PF

50V

R6031

1/16W

402MF-LF

1%

DEBUG_ADC

243

R6030

DEBUG_ADC

243

1%1/16WMF-LF402

R6033

1%1/16W

402

DEBUG_ADC

MF-LF

301K

C6030

CERM402

20%10V

0.1UF

DEBUG_ADC

30 75 C6034


6.3V

DEBUG_ADC

10%

X5R

2.2UF

402

R6034

DEBUG_ADC

1/16W1%

MF-LF

226K

402

C6004

10V20%

402CERM

0.1UF

DEBUG_ADC

C6044


10%

402

DEBUG_ADC

X5R

2.2UF

6.3V

R6044

MF-LF1/16W

402

1%

DEBUG_ADC

226K

R6043

1%1/16W

1M

MF-LF402

DEBUG_ADC

C6043

DEBUG_ADC

402

50V10%

470PF

CERM

R60421M

402

1/16W1%

DEBUG_ADC

MF-LF

C6042DEBUG_ADC

10%

CERM402

50V

470PF

R6040

DEBUG_ADC

402

1%

MF-LF1/16W

3.65K

R6041

DEBUG_ADC

402

1/16WMF-LF

1%

3.65K

57 75

57 75

C6054DEBUG_ADC


2.2UF10%

X5R6.3V

402

C6064


6.3V10%

DEBUG_ADC

2.2UF

X5R402

C60000.1UF

DEBUG_ADC

CERM402

10V20%

R6054

DEBUG_ADC

226K

MF-LF1/16W1%

402

C60400.1UF

CERM402

10V20%

DEBUG_ADC

R6064

1%

DEBUG_ADC

226K

MF-LF1/16W

402

R6053

DEBUG_ADC

280K

MF-LF1/16W1%

402 C6053

DEBUG_ADC

50V

402

470PF

CERM

10%

R6052DEBUG_ADC

280K1%

MF-LF402

1/16W

C6052

CERM50V10%

470PF

DEBUG_ADC

402

R6063

DEBUG_ADC

348K

MF-LF1/16W1%

402 C6063470PF

10%

402

50VCERM

DEBUG_ADC

R6062

1%

DEBUG_ADC

348K

MF-LF1/16W

402

C6062DEBUG_ADC

50V

470PF

CERM402

10%

C60062.2UF20%6.3V

402-LFCERM

DEBUG_ADC

34 75

34 75

34 75

34 75

R6051

MF-LF

499

1/16W1%

402

DEBUG_ADC

R6050

MF-LF

1%

DEBUG_ADC

1/16W

499

402

R6061

1%

MF-LF1/16W

412

DEBUG_ADC

402

SYNC_MASTER=K19_IMLB SYNC_DATE=02/25/2009

DEBUG SENSORS AND ADC

PP5V_S3_DEBUG_ADC_DVDD_FILT

ADC_CH7

=I2C_SMC_ADCS_SDA

=PP5V_S3_DEBUG_ISNS

ADC_CH3

ADC_CH1

=PP5V_S3_DEBUG_ADC_AVDD

ADC_VREF

ADC_SCL

ADC_CH0

=I2C_SMC_ADCS_SCLADC_SDA

=PP5V_S3_DEBUG_ADC_DVDD

ISNS_LCDBKLT_IOUT

PPVOUT_S0_LCDBKLT_DIV

ISNS_HDD_IOUT

ISNS_HDD_R_N

ADC_CH7

ISNS_HDD_PISNS_1V5_S3_IOUT

ISNS_ODD_N

=PP5V_S3_DEBUG_ISNS

ISNS_ODD_IOUT

ISNS_ODD_R_N

ISNS_ODD_P ISNS_ODD_R_P

ISNS_1V5_S3_R_P

ADC_CH1PP5V_SW_ODD_DIVPP3V3_WLAN_F_DIV

ISNS_AIRPORT_R_N

ISNS_AIRPORT_P

ADC_CH3

PP5V_SW_ODD_XWPP5V_SW_ODD

ADC_CH4

ADC_CH5

ADC_CH4

ADC_REFCOMP

ADC_CH6

ADC_CH2

PP3V3_WLAN_F_XW

PPVOUT_S0_LCDBKLT_XWPPVOUT_S0_LCDBKLT

ADC_CH6

ISNS_1V5_S3_P

ISNS_1V5_S3_NADC_CH5

ISNS_HDD_R_P

ISNS_HDD_N

PP3V3_WLAN_F

ADC_CH2

ISNS_AIRPORT_IOUT

ISNS_AIRPORT_R_P

ISNS_AIRPORT_N

ISNS_1V5_S3_R_N

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

=PP5V_S3_DEBUG_ISNS

ADC_CH0

PP5V_S3_DEBUG_ADC_AVDD_FILT

60 OF 109

B.0.0

051-8568

47 OF 77

6

11

109

18

20

25

19

21

13

12

14

15

17

16

22

23

24

1

2

3

4

5

7

8

1 2

2

1

1 2

2

1

2

1

1 2

1 2

2

1

1

2

1

2

23

14

5 6

1 2

1 2

2

5

4

1

3

2

5

4

1

3

2

5

4

1

3

2

5

4

1

3

2

1

2

1

2

1

1 2 1 2

2

11 2 1 2

1

2

1

2

1 2

2

1

2

1

1 2

1

2

1

2

2

1

2

11

2

1 2

1 2

1 2

1 2

2

1

2

1

1 2

2

1

2

1

1 2

1 2

1 2

1

2

2

1

1 2

1 2

2

1

2

1

2

1

1 2

2

1

1 2

1 2

1 2

1

2

2

1

1 2

1 2

1

2

2

1

2

1

1 2

1 2

1 2

47

8 47

47

47

8

47

8

75

8 47

75

75

75

47

75

47

7 34

47

47

47

47

47

7 64 67

47

47

75

30

47

75

75

8 47

47

ININ

IN

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1 OUT




36

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8 7 5 4 2 1

1

0

1

SPI_CLK

0

SPI_MOSI

1

0

1

0

42 MHz

1 MHz

25 MHz

Frequency

MCP79 SPI Frequency Select

31 MHz

21 38 72

R6100

5%3.3K

1/16WMF-LF

402

R619010K

1/16WMF-LF

5%

402

NO STUFF

R6150


MF-LF

5%1/16W

0

402

21 38 72

38

U610032MBIT

MX25L3205DM2I-12G

CRITICAL

OMIT

SOP

21 38 72

R6152

402

0

1/16W5%

MF-LF


R6105

402

0

1/16W5%

MF-LFPLACEMENT_NOTE=PLACE CLOSE TO U6100

R619110K

1/16W5%

MF-LF402

NO STUFF

C6100

20%

402CERM10V

0.1UF

R6101

402MF-LF

3.3K5%1/16W


SPI ROM

SPI_MLB_CS_L

SPI_CLK_R SPI_CLK

SPI_WP_L

=PP3V3_S5_ROM

SPI_MOSI

SPI_HOLD_L

SPI_MISO_R

SPI_MOSI_R

SPI_MISO

61 OF 109

B.0.0

051-8568

25MHz is selected with R5190 and R5191

with R6190, R6191, R5190 and R5191

Any of the 4 frequencies can be selected

48 OF 77

1

2

1

2

1 2

48

3

1

5

7

6

2

1 2

1 2

1

2

2

11

2

72

8 38

72

72

IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

OUTOUT

NR/FB

NC

IN

EN

GND

OUT

OUT

OUT

IN

IN

IN

OUT

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REFVD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC

FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+

MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI

SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+

LINEOUT_L2-

LINEOUT_R2+

/SPDIF_OUT2

OUT




36

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DR


SHEET

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Apple Inc.

PAGE


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345678

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8 7 5 4 2 1

GPIO1 = HP AMP CONTROL

GPIO3 = SPKR AMP SHDN CONTROL

DAC2/3 FSOUTPUTSE= 1.34VRMSDAC2/3 FSOUTPUTDIFF= 2.67VRMS

GPIO2 = K84A IDENTIFICATION

NC

GPIO0 = ANALOG SW CONTROL

APPLE P/N 353S2355

FR SPKR AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE

U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL

4.5V POWER SUPPLY FOR CODEC

NOTES ON CODEC I/O

AUDIO CODEC

NCNC

NCNC

RT. SPKR AMP. SIG. SOURCE

EXT MIC CODEC INPUT

BI MIC CODEC INPUT

DIFF FSINPUT= 2.45VRMSSE FSINPUT= 1.22VRMSDAC1 FSOUTPUT= 1.34VRMS

APPLE P/N 353S2456

603-1

CRITICAL

10UF

6.3VX5R

20%

PLACE NEAR C6220 AND C6221

SM

402-LF

2.2UF

6.3V20%

CERM402-LF

6.3V

2.2UF20%

CERM

603-1

10UF

X5R6.3V20%

CRITICAL

20%16V

1UF

TANT0603-SM

402

20%

X5R4V

4.7UF

21 73

21 73

21 73

21 73

21 73

54

52

51

51

52

52

52

54

54

54

54

54

X5R

10UF CRITICAL

603-1

20%6.3V

1UF10%10VX5R402

1UF

X5R402

10V10%

FERR-220-OHM

0402

402

2.21K

1/16WMF-LF

1%

402X5R10V10%1UF

0.1UF10%

X5R402

16V

10%

402

0.1UF

16VX5R

10%16V

402X5R

0.1UF

1/16WMF-LF

1%

402

2.67K

NOSTUFF

MF-LF1/16W5%

402

100K

X5R

0.1UF

16V10%

402

10UF

2012-LLP

16V20%

TANT-POLY2012-LLP

10UF

TANT-POLY

20%16V

8 49 51 53

8 49 53 54

53

7 49

8

7 49

53

7 49

1UF10%

X5R402-1

10V

TPS71745SON

CRITICAL

16VX7R-CERM

402

10%0.1UF

52

52

52

PLACE NEAR U6200

SM

NOSTUFF

0

1/16W5%

MF-LF402

0402

FERR-220-OHM

50

50

50

51

CS4206ACNZCQFN

CRITICAL

53

CRITICAL

16V

CASE-B2-SM

10UF20%

POLY-TANT

22

5%

402

1/16WMF-LF

402MF-LF1/16W5%

22

5%1K

402

1/16WMF-LF

NOSTUFF

5%1K

402

1/16WMF-LF

SYNC_MASTER=AUDIO SYNC_DATE=06/09/2009

AUDIO: CODEC/REGULATOR

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

=PP5V_S3_AUDIO

=PP3V3_S0_AUDIO

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.10MM AUD_HP_PORT_L

MIN_NECK_WIDTH=0.10MMMIN_LINE_WIDTH=0.20MM AUD_HP_PORT_R

TP_AUD_LO1_N_L

AUD_LO1_P_R

AUD_MIC_INP_R


=PP1V8_S0_AUDIOVOLTAGE=1.8VMIN_LINE_WIDTH=0.10MM

AUD_GPIO_2

HDA_SYNC

CS4206_FLYP

CS4206_FLYC

CS4206_VCOMCS4206_FLYN

AUD_SENSE_A

AUD_GPIO_3

AUD_GPIO_1

AUD_GPIO_0

HDA_RST_L

TP_AUD_SPDIF_IN

GND_AUDIO_HP_AMP

MIN_NECK_WIDTH=0.10MMMIN_LINE_WIDTH=0.20MM AUD_HP_PORT_REF

AUD_LI_P_L

AUD_LI_REF

AUD_SDI_R

HDA_BIT_CLK

AUD_LO2_N_L

AUD_LO2_P_R

AUD_LO2_N_R

HDA_SDOUT

TP_AUD_LO1_P_L

AUD_CODEC_MICBIAS

AUD_SPDIF_OUT

AUD_LO2_P_L

AUD_LO1_N_R

CS4206_FP

CS4206_FN

AUD_SPDIF_OUT_CHIP

HDA_SDIN0

GND_AUDIO_HP_AMP

AUD_LI_P_R

AUD_MIC_INN_R

AUD_MIC_INN_L

PP4V5_AUDIO_ANALOG

=PP5V_S3_AUDIO

4V5_REG_EN

=PP3V3_S0_AUDIO

VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG


TP_AUD_DMIC_CLK

AUD_MIC_INP_L

VBIAS_DAC

PP1V8_S0_AUDIO_DIG


VOLTAGE=5V

4V5_REG_IN

4V5_NR

CS4206_VREF_ADC


VOLTAGE=0VMIN_NECK_WIDTH=0.2MMGND_AUDIO_CODEC


VOLTAGE=0VGND_AUDIO_HP_AMP

C6221

XW6201

C6222 C6223

C6220

C6224

C6210

C6213

C6201 C6203

L6200

R6200

C6200

C6215

C6211

C6214

R6210

R6213

C6218 C6217C6219

C6216

U6200

C6202

XW6200

R6201

L6201

U6201

C6225

R6212

R6211

R6220

R6221

62 OF 109

B.0.0

051-8568

49 OF 77

2

1

1 2

2

1

2

1

2

1

1

2

2

1

2

1

2

1

2

1

21

1 2

2

1

2

1

2

1

2

1

1

2

1

2

2

1 1

2

1

2

2

1

1

3

5

2

6

4

2

1

1 2

1 2

21

3

13

12

2

44

14

11

34

29

45

24

9

15

41

37

36

33

48

22

43

42

47

35

49

46

40

39

28

26

25

23

21

18

17

16

10

7

4

38

8

5

1

6

20

19

27

31

30

32

1

2

1 2

1 2

1

2

1

2

49 50 53 54

8 49 53 54

8 49 51 53

8 49 53 54 49 50 53 54

49 51 53

49 51 53

49 50 53 54

49 51 53

IN

IN

IN

OUT

OUT

OUT

IN




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FC_LP = 43KHZ

NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)FC_HP = 3.6 HZ

CODEC RIN = 20K OHMS

LINE INPUT VOLTAGE DIVIDER

VIN = 2VRMS, CODEC VIN = 1.14 VRMS

52

52

52

49

49

49

49 52 53

C6301

402

10V

2.2UF

CRITICAL

X5R-CERM

20%

C6302

20%10V

2.2UF

X5R-CERM402

CRITICAL

C6312

20%

402

10V

2.2UF

CRITICAL

X5R-CERM

C63112.2UF

402

10V20%

X5R-CERM

CRITICAL

R6301

MF-LF1/16W

402

1%

7.87K

R6311

MF-LF1/16W

402

1%

7.87K

R6302

MF-LF1/16W

402

1%21.5K

R6312

MF-LF1/16W

402

1%21.5K

C6303NOSTUFF

50VCERM402

820PF10%

C6313NOSTUFF

50VCERM402

820PF10%

R6300101%

402MF-LF1/16W

AUDIO: LINE INPUT FILTER

AUD_LI_REFMIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUD_LI_R

GND_AUDIO_CODEC

MIN_NECK_WIDTH=.1MMMIN_LINE_WIDTH=.1MM

AUD_LI_P_R

AUD_LI_P_LMIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUD_LI_LMIN_NECK_WIDTH=.1MMMIN_LINE_WIDTH=.1MMAUD_LI_L_DIV

AUD_LI_R_DIVMIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUD_LI_GNDMIN_LINE_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

63 OF 109

B.0.0

051-8568

50 OF 77

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1

2

2

1

2

1

1

2

SVSS

INL

SHDN*

INR

VDD

PVSS

PGND

SGND

THRM

OUTR

OUTL

C1P

C1N

PAD

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN




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MAX9724 GAIN/FILTER COMPONENTS

AV_PB = -1V/V, FC_LPF = 35.2KHZ

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

NC

NC

HP/LO AMPAPN: 353S1637

C6500

402

16V10%

X7R-CERM

0.1UF

CRITICAL

R6500

5%1/16WMF-LF402

39

C6510

402X7R-CERM

16V10%

0.1UF

CRITICAL

R6510

1/16W

402

395%

MF-LF

U6500CRITICAL

TQFNMAX9724A

C6522CRITICAL

10%1UF

402X5R10V

C65231UF10V

402

10%

CRITICAL

X5R

C65241UF

X5R10V

402

10%

CRITICAL

C6521

6.3V20%10UF

X5R603

C6520

X7R-CERM

0.1UF

402

10%16V


0402-LF

R6522

402

5%

MF-LF1/16W

100K

R6531

1/16W

402MF-LF

13.7K

1%

R6530

MF-LF402

13.7K

1%1/16W

R6533

402MF-LF1/16W

13.7K

1%

R6532

MF-LF1/16W

402

13.7K

1%

C6530330PF

5%

CRITICAL

COG402

50V

C6531

50VCOG402

330PF

5%

CRITICAL

R6520

5%1/16W

402MF-LF

0

49 51

49 51

49

51 52

51 52

51 52

51 52

R65231%2.21K1/16W

402MF-LF

R65241%2.21K

402

1/16WMF-LF

49 51

49 51 52

49 51

SYNC_DATE=06/09/2009SYNC_MASTER=AUDIO

AUDIO: HEADPHONE FILTER

AUD_LO_AMP_INL_M

GND_AUDIO_HP_AMP

AUD_GPIO_1

AUD_LO_AMP_OUTRMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.15MM

AUD_LO_AMP_OUTL

MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.2MM

AUD_LO_AMP_OUTRAUD_HP_PORT_R

AUD_HP_PORT_LAUD_LO_AMP_INL_M

=PP5V_S3_AUDIO

AUD_LO_AMP_INR_M

GND_AUDIO_HP_AMP

AUD_HP_ZOBEL_R

AUD_HP_PORT_R

AUD_LO_AMP_INR_M

AUD_HP_ZOBEL_L

AUD_GPIO_1_R

MAX9724_SVSS

AUD_LO_AMP_OUTL

MAX9724_C1N

MAX9724_C1P


AUD_PP5V_FMIN_NECK_WIDTH=0.2MM

AUD_HP_PORT_L

65 OF 109

B.0.0

051-8568

51 OF 77

2

1

1

2

2

1

1

2

9

6

5

8

12

427

13

10

11

1

3

2

1

2

1

2

1

2

1

2

1

21

1

2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1

2

51

49 51 52

51

8 49 52

51

51

IN

IN

IN

IN

IN

IN

IN

IN-

SD*

IN+ OUTA

PVDD

GNDPGND

OUTB

VDD

IN-

SD*

IN+ OUTA

PVDD

GNDPGND

OUTB

VDD

IN-

SD*

IN+ OUTA

PVDD

GNDPGND

OUTB

VDD

OUT

OUT

OUT

OUT

OUT

OUT




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6DB (2V/V)

SPRK AMP. INPUT REFERRED CLIP POINT = ~-6dBFS

ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

796Hz < HPF FC < 936Hz

APN:353S2621

APN:353S2621

ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

SATELLITE

SUB

GAIN

80 Hz < HPF FC < 94 Hz

ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM APN:353S2621

49

49

C660710%

X5R10V

402

1UF

L6620FERR-1000-OHM

0402

L6610FERR-1000-OHM

0402

L6630FERR-1000-OHM

040249

C660910%

X5R10V

402

1UF

C6608

10VX5R

10%

402

1UF

C6603

CRITICAL

2012-LLPTANT16.3V20%47UF

R66100

1/16W

402MF-LF

5%

49

C6620CRITICAL

0.1UF

16V

402

10%

X5R

R6611100K5%1/16W

402MF-LF

L6611FERR-1000-OHM

040249

C6621CRITICAL

10%

402

16V

0.1UF

X5R

L6621

0402

FERR-1000-OHM

49

L6631FERR-1000-OHM

040249

U6620LM48311

BGA

CRITICAL

U6610CRITICAL

LM48311BGA

C6601

2012-LLPTANT16.3V20%47UF

CRITICAL

U6630BGA

LM48311

CRITICAL

C6605

2012-LLP

47UF6.3VTANT1

CRITICAL

20%

7 53

7 53

7 53

7 53

7 53

7 53

C6610

402

10%

0.01UF

CRITICAL

25VX7R

C6630

402

10%25VX7R

CRITICAL

0.01UF

C6611

402

10%

CRITICAL

0.01UF

25VX7R

C6631

402

0.01UF

CRITICAL

25VX7R

10%

C6602

10%0.01UF

402CERM16V

SYNC_MASTER=AUDIO

AUDI0: SPEAKER AMPSYNC_DATE=02/16/2010

AUD_LO2_P_R

SPKRAMP_SHDN

=PP5V_S3_AUDIO_AMP

LM48311_SUB_N

SPKRAMP_SHDN

SPKRAMP_INSUB_N

=PP5V_S3_AUDIO_AMP

MIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 MMSPKRAMP_L_N_OUT

SPKRAMP_L_P_OUTMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 mm

LM48311_SUB_P


SPKRAMP_SUB_P_OUTMIN_NECK_WIDTH=0.20 MM

LM48311_R_P MIN_LINE_WIDTH=0.30 mm

SPKRAMP_R_N_OUTMIN_NECK_WIDTH=0.20 MM

=PP5V_S3_AUDIO_AMP

SPKRAMP_INR_P

AUD_LO2_N_L

SPKRAMP_INSUB_PAUD_LO1_P_R

AUD_LO1_N_R

AUD_LO2_P_L

AUD_LO2_N_R SPKRAMP_INR_N

LM48311_L_PSPKRAMP_INL_P

SPKRAMP_INL_N

LM48311_L_N

SPKRAMP_SHDN

MIN_NECK_WIDTH=0.20 MMSPKRAMP_SUB_N_OUT


SPKRAMP_R_P_OUTMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 mm

AUD_GPIO_3

LM48311_R_N

66 OF 109

B.0.0

051-8568

52 OF 77

2

1

21

21

21

2

1

2

1

1

2

1 2

1 2

1

2

21

1 221

21

C1

A2

A1 A3

B1B2

C2B3

C3

C1

A2

A1 A3

B1B2

C2B3

C3

1

2

C1

A2

A1 A3

B1B2

C2B3

C3

1

2

1 2

1 2

1 2

1 2

2

1

52

8 52

52

8 52

8 52

52

IN

IN

IN

IN

OUT

OUT

OUT

BI

BI

BI

BI

VCC

COM1

COM2

EN*

NC1

CB

NO1

NEG

GND

NO2

NC2

IN

IN

OUT

OUT

IN

IN

IN

OUT

OPERATING VOLTAGE 3.3

B - VCC

SHELL

SHIELDPINS

HP DETECT

GND

PHS DETECT

AUDIO

A - VIN

POF

C - GND

IN

OUT

OUT




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APN:518S0520

AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

DYN. FULL RANGE

LEFT THIN DYN.

RT. THIN DYN.

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED

MIC CONNECTOR

SPEAKER CONNECTORS

APN: 353S2536

GND STUFFING OPTIONS FOR CMOS SWITCH

APN:518S0519

ANALOG AUDIO IO SWITCH

GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED

APN:514-0750

CERM

10%1UF

6.3V

402

C6700

7 52

7 52

7 52

7 52

78171-0002M-RT-SM

CRITICAL

J6702

6.8V-100PF402

CRITICAL

DZ6704

CRITICAL

4026.8V-100PFDZ6703

6.8V-100PF

CRITICAL

402

DZ6700

6.8V-100PF

CRITICAL

402

DZ6705

M-RT-SM78171-0003

CRITICAL

J6701

0402

FERR-1000-OHML6702

0402

FERR-1000-OHML6701

54

54

6.8V-100PF

CRITICAL

402

DZ6701

49

0.0033UF10%

402

50VCERM

C6711

SM

PLACE NEAR J6700

XW6700

SM

PLACE NEAR J6700

XW6701

53

53

5%1/16W

402

0

MF-LF

R6714MF-LF

0

5%1/16W

402

R6715

MF-LF

5%1/16W

402

0R6717

402MF-LF

0

5%1/16W

R6718

5%

0

1/16WMF-LF402

R6719

MF-LF1/16W

402

5%

0R6716

53

53

0

5%1/16WMF-LF402

R6720

U6700

CRITICAL

MAX14504WLP

100K

1/16W

402MF-LF

5%

R6721

402

10%

X5R

1UF

10V

C6710

0

402

5%1/16WMF-LF

R6724

NOSTUFF

MF-LF

5%

0

1/16W

402

R6727

50

50

51

51

49

CRITICAL

M-RT-SM

7 52

7 52

SM

PLACE NEAR J6700

XW6702

1/16W

24K5%

R6712

MF-LF402

24K5%1/16WMF-LF402

R6713

NOSTUFF

100PF5%50V

CERM

C6702NOSTUFF

CERM402

100PF5%50V

C6703

C6704

5%

402

50V

100PF

CERM

NOSTUFFNOSTUFF

C6705

50V5%

402CERM

100PF

NOSTUFF

50V

CERM402

100PF5%

C6706NOSTUFF

402CERM

100PF

50V5%

C6707

6.8V-100PF402

CRITICAL

DZ6702

54

0402

L6706

M-RT-SM78171-0003

CRITICALJ6704

R6708

603

5%1/10WMF-LF

0

R6709

603

5%1/10WMF-LF

R67100

5%1/10WMF-LF603

R6707

MF-LF

0

5%

603

1/10W

F-RT-TH

49

FERR-120-OHM-1.5A

CRITICAL

0402-LF

L6703

L6705

CRITICAL

0402

L6704

54

54

402

1/16WMF-LF

10K

5%

R6700

4.7

402MF-LF

5%1/16W

R6701

CERM

100PF

50V5%

402

C6701

AUDIO: JACKSYNC_DATE=06/09/2009SYNC_MASTER=AUDIO

SPKRAMP_SUB_P_OUT



SPKRAMP_R_P_OUT_CONN

SPKRAMP_SUB_N_OUT_CONN

SPKRAMP_R_N_OUT_CONN

SPKRAMP_R_N_OUT

SPKRAMP_SUB_P_OUT_CONN

AUD_GPIO_0

AUD_CONN_GND AUD_SWITCH_GND

MIN_NECK_WIDTH=0.15MM AUD_CONN_RMIN_LINE_WIDTH=0.2MM

SPKRAMP_L_P_OUT

SPKRAMP_L_N_OUT

AUD_J1_SLEEVEDET_R

BI_MIC_SHIELD

AUD_CONN_L

GND_AUDIO_HP_AMP

AUD_CONN_GND

AUD_CONN_GND


AUD_LI_GND

AUD_HP_PORT_REF

=PP5V_S3_AUDIO PP_MAX14504_VCC

AUD_LO_AMP_OUTL

AUD_LI_L

BI_MIC_LO

HS_MIC_HI

BI_MIC_HI

AUD_LI_L_SWITCH

AUD_LO_AMP_OUTL_SWITCH

AUD_LI_R_SWITCH

AUD_SWITCH_CTRL

SWITCH_CP

GND_AUDIO_CODEC

AUD_LI_R

AUD_LO_AMP_OUTR

AUD_IP_PERPH_DET

HS_MIC_LO

AUD_J1_TIPDET_R

AUD_CONNJ1_TIP

AUD_CONNJ1_RING

AUD_IP_PERPH_DET_JACK

AUD_CONNJ1_TIPDET

AUD_CONNJ1_SLEEVEDET

AUD_CONNJ1_SLEEVE


AUD_SPDIF_OUT=PP3V3_S0_AUDIO

AUD_CONNJ1_MIC

FERR-1000-OHM

0402

FERR-220-OHM

CRITICAL

FERR-220-OHM

SPKRAMP_R_P_OUT

AUD_CONN_L

SPKRAMP_SUB_N_OUT

0

J670378171-0002

402

AUD_CONN_R


AUD_LO_AMP_OUTR_SWITCH

AUDIO-JACK-TRANS-CFR-K86K87J6700

CRITICAL

67 OF 109

B.0.0

051-8568

53 OF 77

2

1

4

2

1

3

1

2

1

2

1

21

2

5

1

3

2

4

21

21

1

2

2

1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

A3

C3

B4

B1

B2

C4

C2

A4

A2B3

A1

C1

1

2

2

1

1 2

1 2

4

2

1

3

1 2

1

2

1

2

2

1

2

1

2

1

2

1

2

1

2

1

1

2

21

5

1

3

2

4

1 2

1 2

1 2

1 2

8

2

4

3

5

6

7

1

9

10

11

12

13

14

21

21

21

1 2

1 2

2

1

53

7 54

49 51

53 53

50

8 49 51

7 54

7 54

49 50 54

8 49 54

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

BI

IN

OUT

OUT

IN

GND THMENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASSINT*

SCL

D

SGD

SG

VEE1

VEE0

VCC

OUT




36

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

0X08 (8)

PORT B RIGHT(BUILT-IN MIC)

PORT A DETECT (HEADPHONES)

DET ASSIGNMENT

MCP79 GPIO_17 (PERIPH DETECT)MCP79 GPIO_4 (LOAD DETECT)

MCP79 GPIO_38

MIC_BIAS (80%)

PORT B DETECT(SPDIF DELEGATE)

NC

N/A

VREF/ENABLE

GPIO_0 AND GPIO_1

GPIO_0 AND GPIO_1

0X0D (13,V22,B,LEFT)

GPIO_3

COMP. TRIP PT. = 2.64V

PULLUPS ON MCP PAGE0X06 (6)

DRC MIKEY

APN:353S2256

PIN COMPLEX

HP=80HZ, LP=8.82KHZ

HEADSET MIC

0X02 (2)

CONVERTER

PORT B LEFT(HEADSET MIC)

HP=80HZ

N/A

N/A0X04 (4)

SPDIF OUT

SUB

N/A

0X09 (A) AND UI ELEMENT

0X09 (9,A)

0X0B (11)

MUTE CONTROL DET ASSIGNMENT

0X09 (A)

0X0D (B)

NC

0X06 (6)

APN:376S0613

0X0C (12)

GPIO_3

N/A

0X03 (3)

FUNCTION

FUNCTION

CODEC INPUT SIGNAL PATHS

0X04 (4)

0X05 (5)

0X02 (2)HP/LINE OUT

LINE IN

SATELLITES

BUILT-IN MIC

0X10 (16)

0X0A (10)

CONVERTER

OUTPUT HIGH WHEN MIC BIAS LOADED

OUTPUT LOW WHEN MIC BIAS UNLOADED

0X0D (13,B,RIGHT)

PIN COMPLEX

0X03 (03)

0X05 (5)

VOLUME

CODEC OUTPUT SIGNAL PATHS

MIKEY MIC LOAD DET CKT

PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA

EXTRACTION NOTIFICATION CKT

BI_MIC_LO_F

BI_MIC_HI_F

GND_AUDIO_CODEC

AUD_MIC_INP_R

AUD_SENSE_A

AUD_PORTB_DET_L

HS_MIC_LO

AUD_PORTA_DET_L

HS_MIC_HI

HS_SW_DET

HS_MIC_BIAS

GND_AUDIO_CODEC

BI_MIC_SHIELD

=I2C_MIKEY_SDA

AUD_I2C_INT_L

PP3V3_S0_AUDIO_F

AUD_J1_TIPDET_R AUD_J1_DET_RC

PP3V3_S0_AUDIO_F

=PP3V3_S0_AUDIO

VOLTAGE=3.3V


PP3V3_S0_HS_RX

BI_MIC_LO

AUD_MIC_INP_L

AUD_MIC_INN_R

AUD_CODEC_MICBIAS

BI_MIC_HI

MIC_BIAS_FILT

AUD_MIC_INN_L

GND_AUDIO_CODEC

=I2C_MIKEY_SCL

AUD_IPHS_SWITCH_EN

HS_MIC_HI_RC

HS_RX_BP

HS_MIC_BIAS

MIKEY_MIC_LOAD_DET

HS_MIC_BIAS_COMP

HS_MIC_HI

MIC_LOAD_COMP_OUT

GND_AUDIO_CODEC

AUD_OUTJACK_INSERT_L

PP3V3_S0_AUDIO_F

AUD_J1_SLEEVEDET_R

GND_AUDIO_CODEC

PERPH_DET_FILT

GND_AUDIO_CODEC

GND_AUDIO_CODEC

AUD_IP_PERIPHERAL_DET

AUD_J1_SLEEVEDET_INV

AUD_J1_SLEEVEDET_R

GND_AUDIO_CODEC

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

AUD_PERPH_DET_R

AUD_IP_PERPH_DET

AUD_J1_TIPDET_INV

PP3V3_S0_AUDIO_FVOLTAGE=3.3V


SYNC_MASTER=AUDIO SYNC_DATE=06/09/2009

AUDIO: JACK TRANSLATORS

MF-LF

MIKEY

300K5%1/16W

402

R6862

402MF-LF

5%

MIKEY_LOAD_DET

0

1/16W

R6873

9

100K

402

1%1/16WMF-LF

MIKEY_LOAD_DET

R6872MIKEY_LOAD_DET

402

0.1UF10%16VX5R

C6872

1%

MF-LF1/16W

402

100K

MIKEY_LOAD_DET

R6871

1%

402

1/16W

2.21K

MF-LF

MIKEY_LOAD_DET

R6870

27PF

402

5%

CERM50V

MIKEY_LOAD_DET

C68705%27PF

402CERM50V

MIKEY_LOAD_DET

C6871

MIKEY_LOAD_DET

MAX9028EBT+

CRITICAL

UCSP

U6870

MF-LF402

300K

1/16W5%

R6801

402

100K5%1/16WMF-LF

MIKEY

R6865MF-LF1/16W5%

402

MIKEY

220KR6864

MIKEY

0.1UF20%

402CERM10V

C6860402MF-LF

15K

1/16W5%

MIKEYR6860

SSM6N15FEAPESOT563

MIKEY

Q6802

SSM6N15FEAPESOT563

MIKEY

Q6802

CRITICAL

402CERM

1UF10%6.3V

MIKEY

C6880MIKEY

DRCCD3275U6880

53 52 49 8

0402

FERR-1000-OHM

L6862

10V 20%

0.1UF

CERM402

C6861

MF-LF

5%1/16W

0

MIKEY

402

R6861

17

2.4K

MF

1%

1/16W

402-1

R6853

MF-LF

1/16W1%

402

100

R6850

X5R

CRITICAL

0.1UF

25V10%

402

C6851

49

CRITICALMIKEY

0.1UF

X5R

10%25V

402

C68861/16W

MF-LF

402

5%

2.2K

MIKEY

R6884

19

39

39

21 2.2UF

CRITICAL

TANT6.3V

402

MIKEY

20%

C6882

0402

MIKEY

FERR-1000-OHM

L6880

10%0.01UF

CERM402

MIKEY

16V

C68815%

MF-LF

100K

402

1/16W

MIKEY

R6880

MIKEY

402

1%

MF-LF

1K

1/16W

R6881

49

SM

PLACE NEAR C6886

XW6880

0.1UF

X5R

10%25V

MIKEYCRITICAL

402

C6883

5%

100K

MIKEY

402MF-LF1/16W

R6883

0.0082UF

402

25V10%

CRITICAL

X7R

MIKEY

C6884MIKEY

27PF

CRITICAL

40250V5%

CERM

C6885

1/16W

2.2K5%

MIKEY

402

MF-LF

R6882

52

53 52

FERR-1000-OHM

0402

L6850

FERR-1000-OHM

0402

L6851

402TANT6.3V20%

2.2UF

CRITICAL

C6852

52 7

52 7

52 7

49

49

49

SM

PLACE NEAR J6701

XW6851

402

100K5%

1/16WMF-LF

R6852

402 CERM

0.001UF50V

CRITICAL

10%

C6853

10%25V

402X5R

0.1UF

CRITICAL

C6850

50V

CERM 4025%27PF

CRITICAL

C6854

2.4K

1/16W1%

402-1MF

R6851

SSM6N15FEAPESOT563

Q6801

SOT563

SSM6N15FEAPE

Q6801

SSM6N15FEAPESOT563

Q6800

SOT563

SSM6N15FEAPE

Q6800

1/16W

MF-LF

1%

20.0K

402

R6805

53 52

49

402

10%

0.01UF

CERM

16V

C6802

402

220K

1/16WMF-LF

5%

R68045%

1/16W

220K

402MF-LF

R6803

402

39.2K

1/16W1%

MF-LF

R6806

52

47K

1/16WMF-LF402

5%

R6802

402

0.1UF

CERM20% 10V

C6801

68 OF 109

B.0.0

051-8568

54 OF 77

2

1

1 2

1

2

1 2

1

2

2

1

1

2

3

45

6

12

3

45

6

12

1 2

2

1

1 2

2

1

1

2

1 2

1

2

21

21

1

2

2

1

2

1

1

2

1 2

1 2

1

2

1

22

1

21

1

2

1 2

1 2

1 2

1 2

1 2

2

1

21

9

11

8

4

3

5

1

2

107

6

2

1

6

12

3

45

1 2

2

1

1

21

2

1

2

B2

A2

A1

B1

B3

A3

2

1

2

1

1

2

1

2

2

11

2

1 2

1

2

53 52 50 49

53

53 52 50 49

53

53

53 52 49 8

53 52 50 49

53

53 52

53 52 50 49

53

53 52 50 49

53 52 50 49

53 52 50 49

53 52

53 52 50 49

53 52 50 49

52

53

NC

NC NC

VCC

EXTINT

NCGND

BI

Y

B

A

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

P3

P4

P5

P6

P7

P8

P1

P2

P9

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1


1-Wire OverVoltage Protection

MagSafe DC Power Jack

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

518S0656

Vout = 3.425V

250MA MAX OUTPUT

(Switcher limit)

518-0359

<Rb>

<Ra>

NC

Vout = 1.25V * (1 + Ra / Rb)

BATTERY CONNECTOR

339S0114

Assembly APN: 339S0114

- BOM: 639-0680

- PCBF: 820-2801

- MCO: 056-3515

- Conn APN:518S0788

PN: 607-6831 for WCPM. PN: 339S0114 for schematic/board layout

PROTO 1: STUFFING K87 HALL EFFECT ASSEMBLY ONTO K87 PADS

PROTO 0: STUFFING K84 CONNECTOR ONTO MODIFIED K84 PADS

HALL EFFECT ASSEMBLY

C6999

6.3V20%

CERM

CRITICAL

805

22UF

C6994

X5R402

20%6.3V

R6995

1%1/16WMF-LF

348K

402

C699522pF

50V

402CERM

5%

R6996

402

200K

MF-LF1/16W

1%

C6990

10%25V

X5R805

10UF

R6905

805

5%1/8W

47

MF-LF

J6900

M-RT-SM78048-0573

CRITICAL

D6905HN2D01JEAPE

SOT665

R6928

402

MF-LF1/16W5%

0

C6950

10%

402

25VX5R

0.1UF

6AMP-24V

D6950

SC-75

CRITICAL

RCLAMP2402B

NOSTUFF

C6908

PLACEMENT_NOTE=PLACE NEAR U6901

0.1UF

402CERM10V20%

SC70-5MAX9940

36

TC7SZ08AFEAPESOT665

R6950

402

1/16WMF-LF

5%

10K

U6990LT3470A

DFN

CRITICAL

2.0K402

5%1/16WMF-LF

ONEWIRE_PU

J6950M-RT-TH

CRITICAL

BAT-K24

L699533UH-20%-0.44A-0.455OHM

CRITICAL

D52LC-SM


DC-In & Battery Connectors

MIN_NECK_WIDTH=0.25 mmSWITCH_NODE=TRUE


P3V42G3H_SW

DIDT=TRUE

=SMBUS_BATT_SDA

SYS_DETECT_L

=SMBUS_BATT_SCL

=PP3V42_G3H_ONEWIREADAPTER_SENSE

SYS_ONEWIRE

SMC_BC_ACOK

VOLTAGE=18.5V


PPDCIN_S5_P3V42G3H


=PP18V5_DCIN_CONN

SMC_BC_ACOK_VCC

P3V42G3H_BOOSTDIDT=TRUEVOLTAGE=18.5V


PPVIN_G3H_P3V42G3H


BATT_POS_F

BATT_POS_FMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.3 mmVOLTAGE=12.6V

P3V42G3H_FB

=PP3V42_G3H_REG

0.22uF

SMC_LID SMC_LID_R

1607-6831 CRITICALJ6955SUB ASSY - HALL EFFECT, K86 K87

43 36 35

50V10%

402

0.001UF

NOSTUFF

CERM

C6955

R6961

5%

MF-LF

0

1/16W

402

OMIT

F-ST-SM

J6955HALLEFFECT-ASSY-K87

R6929

=PP3V42_G3H_HALL

U6901U6900

ADAPTER_SENSE_R

CRITICAL

F6905

1206-1

CERM

20%

603

0.01UF

50V

C6905

MIN_LINE_WIDTH=1mmMIN_NECK_WIDTH=0.20mmVOLTAGE=18.5V

5%1000PF

402NP0-C0G25V

5%

402NP0-C0G25V 25V

NP0-C0G402

5%

C69701000PF

C69711000PF

C6972

PP18V5_DCIN_FUSE =PP18V5_DCIN_CONN

69 OF 109

B.0.0

051-8568

55 OF 77

2

1

2

1

2

1

1

2

2

1

1

2

2

1

1 2

3

2

1

4

5

2

4

5

3

1

1 2

2

1

21

3

21

2

1

1

54

2 3

3

5

1

4

2

1

2

4

36

2

8

5

7

19

12

3

4

5

6

7

8

1

2

9

10

11

12

13

211

43

2

6512

2

1

2

1

2

1

2

1

39

7

39

8 7

36 37

8 54

7 54 55

7 54 55

8

7

8

7 8 54

GND

VCC

D

SG

D

SG

CSON

CSOP

VNEG

VCOMP

ICOMP

VREF

ACIN

SDA

VHST

SCL

VDDP

BGATE

VDD

ACOK

THRM_PAD

AGATE

AGND

AMON

BMON

BOOT

CSIN

CSIP

DCIN

LGATE

PGND

PHASE

UGATE

TRKL*

D

G

S

NC

D

G

S

D

G

S

S

D

G

S

D

G




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PBUS SUPPLY / BATTERY CHARGER

BATTERY CHARGE LIMITING FETS

(CHGR_ACIN)

(CHGR_CSON)

MAX CURRENT = 7A

(CHGR_CSOP)

(??? limited)

TO SYSTEM

(CHGR_CSO_R_N)

PWM FREQ. = 400 kHz

AMON PULLDOWN LOGIC

C7060



RJK0365DPA-02

CHGR_VDD

CHGR_DCIN

CHGR_BOOT

CHGR_PHASE

WPAK

CRITICAL

Q7021

CRITICAL

WPAK

Q7020RJK0365DPA-02

62K

CHGR_CSIN_XW7021

C70240.047UF

MF-LF

CRITICAL

0.1UF

10%

10VX5R402-1

CHGR_AGATE

CHGR_UGATE

DIDT=TRUEMIN_NECK_WIDTH=0.2 MM

CRITICAL

DIDT=TRUE

C7025



0.001UF

CHGR_CSO_R_P

L7000

IHLP4040DZ-SM

4.7UH-9.5A

ISL6258AHRTZ

XW7021OMIT

R7021

SM

R7020

C7021CRITICALCRITICAL

0612-1

C7020

25VPOLY-TANT


PLACEMENT_NOTE=PLACE C7027 ACROSS PIN 5 OF Q7020 AND PINS 1/2/3 OF Q7021MIN_LINE_WIDTH=0.6 MM

PP18V5_S5_CHGR_SW_R

=SMBUS_CHGR_SCL

CHGR_ICOMP

PPVBAT_G3H_CHGR_REG

CERM

1/16W


PPVDCIN_G3H_PRE


PPVDCIN_G3H_PRE2

SI7149DPSO-8

CRITICAL

CHGR_LOWCURRENT_GATE_R100K

PLACEMENT_NOT=PLACE XW7021 ON PAD OF R7020

MF

10

402

1/16W

R7001

5%1/16W

402

R7060

=PP3V42_G3H_CHGR

CHGR_LOWCURRENT_GATE

0.1UF10%

R7040

1/16WMF-LF

C7040

CHGR_VDDP

100K

402MF-LF

CHGR_LOWCURRENT_REF

SOT23-5

XW7020

CHGR_PIN6

=CHGR_ACOK

CHGR_AMON

402

GND_CHGR_SGND

PLACEMENT_NOT=PLACE XW7000 CLOSE TO U7000

CHGR_PIN26

D7010

POLY-TANTCASE-D2-SM

1206

F7000

62K

PLACEMENT_NOT=PLACE XW7020 ON PAD OF R7020

1/16W

U7000

CHGR_LGATE

TP_CHGR_TRKL

XW7000

16V10%

CHGR_CSIN

CHGR_BGATE

4.7

C7026

50V

C7063

25V

=PP18V5_G3H_CHGR

C7022 0.001UF

0.001UF

CHGR_SGATE

5%

=PP3V42_G3H_CHGR

CHGR_DCIN

CHGR_VCOMP

CHGR_VNEG

CHGR_CSOP

CHGR_CSON

CHGR_ACIN

CHGR_CSO_R_N

GND_CHGR_SGND

CHGR_PIN26

CHGR_PIN6

CHGR_AMON

CHGR_VDD_L

CHGR_VDD_R

CHGR_VDD

CHGR_VNEG_R

CHGR_VCOMP_R

PPVBAT_G3H_CHGR_OUT

=PPBUS_G3H

CHGR_AMON

CHGR_BMON

=PP3V42_G3H_CHGR

PPVBAT_G3H_CHGR_OUT

GND_CHGR_SGND

GND_CHGR_SGND

CHGR_CSIP

BATT_POS_F

CHGR_BGATE

=SMBUS_CHGR_SDA


PBUS Supply/Battery Charger

402X5R

10%16V

0.1UF0.01uF

16V

402CERM

10%

C7050

PLACEMENT_NOT=PLACE XW7054 CLOSE TO U7000

SM

OMIT

XW7054

SM

OMIT

PLACEMENT_NOT=PLACE XW7052 CLOSE TO U7000XW7052

402

50V20%

C7028

CRITICALSO-8SI7137DP

Q7050

0.5%

0612-1

CRITICAL

0.01

MF1W

R7008

50V20%

402CERM

C7027

SOD-723-HF1SS418

0.033UF10%16VX5R402

C7042

QFN

0

1/16W5%

402MF-LF

R7047

2.2

MF-LF

5%1/16W

402

R7031

33UF20%

CRITICAL

POLY-TANTCASED2E-SM

16V

C70081UF

25VX5R603-1

10%

C7011

7AMP

CRITICAL

1.82K1%

1/16W

R7061

NOSTUFF

MF-LF1/16W

402

1M5%

R7075

402

1M5%

1/16WMF-LF

R7074

5%1/16WMF-LF

1K

402

R7073

MF-LF

9.31K1%

402

1/16W

R7011

402

1%1/16W

30.1K

MF-LF

R7010

X5R402

1UF

C7043

5%

5%

402

1/16WMF-LF

R7062

402

10%25V25V

0.1UF

X5R402

MF-LF

CERM402

10V

SM OMIT

SSM6N15FEAPESOT563

Q7070

SOT563SSM6N15FEAPE

Q7070

X5R402

25V

CRITICAL

TL331U7060

402MF-LF

1/16W

R7098

5%

MF-LF402

R7099

402

57.6K1%

MF-LF

0.1UF

X5R

10%

402

10%

402X7R

OMIT

SM

470PF

CERM

10%50V

C7046

402

1%3.01K

MF-LF

R7046

0.001UF

50VCERM

10%

402

C7045

1/16W1%

MF-LF

56.2K

402

R7045

0.01UF

CERM16V

402

10%

C7044

0.1UF10%

402X5R25V

C7010

X5R402-1

10%10V

1UFC7047

10%1UF

20%25V

22UF

CASE-D2-SM

22UF20%

1UF

25VX5R

10%

603-1 603-1

25VX5R

1UF10%

C7023

10%10V

1UF

X5R402-1

C7041

0.1UF

25V10%

MF-LF

0.5%

CRITICAL

1W

0.02

C7051

R7023105%1/16W

402

CHGR_CSIP_XW7020

C7061

GND_CHGR_SGND

402

1/16W

C7062

5%

X5R

DIDT=TRUE

DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM


10%

X5R

402

SI7149DPQ7000

CRITICAL

SO-8

Q7001

70 OF 109

B.0.0

051-8568

56 OF 77

1

2

1 2

2

1

1 2

2

1

2

11

2

1

2

2

1

2

1

2

1

2

1

1

2

2

1

1

2

2

1

1 2

2

1

2

1

1

2

1 2

1

2

4

3

1

2

5

2

1

6

12

3

45

1 2

1 2

2

1

1 2

1 2

2

1

2

1

1

2

1 2

21

1

2

1

2

1

2

1

2

1

2

1

2

21

2

1

1

2

1 2

1 2

17

18

8

7

5

4

3

10

12

11

20

16

19

14

29

1

6

26

9

15

25

27

28

2

21

22

23

24

13

2

1

21

21

2

1

43

21

4

3

521

2

1

1 2

1 2

4

3

521

4

3

5 21

4

321

5

4

321

5

2

1

2

1

41

55

55 8

55

75

55

55 41

55

55

8

39

55

55

55

55 41

55

55

37

75

55

8

55 41

55 8

55

55

55

55

55 8

54 7

55

39

55

IN

IN

D

SG

D

SG

D1

G1

S2

G2

S1/D2

G

D

S

G

D

S

DRVH1

SKIPSEL

VBST1

GND THRM_PAD

ENTRIP1

VFB1

VO1

DRVL1

LL1

EN0

VCLK

ENTRIP2

PGOOD

VO2

VFB2

DRVL2

LL2

DRVH2

VBST2

VREG5

VREG3

VREFVIN

TONSEL




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

EMI request

EMI request

MAX CURRENT = 10A

EMI request

Place XW7203 by Pin1 OF L7260.

PWM FREQ. = 300 KHZ

EMI request

Place XW7201 between Pin 15 and Pin 25 of U7200.

Place XW7202 by C7292.

ROUTING NOTE:

EMI request

5V S3/3.3V S5 POWER SUPPLY

ROUTING NOTE:

ROUTING NOTE:


PWM FREQ. = 375 KHZ

VOUT = (2 * RA / RB) + 2

NC

VOUT = (2 * RC / RD) + 2

<RC><RD><RB><RA>

MAX CURRENT = 4A

EMI request

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

ROUTING NOTE:

EMI request

Place XW7204 by Pin 2 of L7220.

ROUTING NOTE:

- COPY THIS PAGE FROM K36 CSA.76

10UFX5R20%

6036.3V

XW7201PLACEMENT_NOT=PLACE XW7201 BETWEEN PIN 15 AND PIN 25 OF U7200

OMIT

SM

62

62

Q7221

SOT563

SSM6N15FEAPE

Q7221

SOT563

SSM6N15FEAPE

XW7202

PLACEMENT_NOT=PLACE XW7202 BY C7292

SM

OMIT

OMIT

XW7205


OMIT

SM

XW7204OMIT

SM

C7230

40250VCERM20%0.001UF

X5R402

C723150V0.001UF20%

402CERM

C7232

40250VCERM20%0.001UF

C7233

402

50V

0.001UF

CERM

20%100PF

402

5%50VCERM

C7294NO STUFF

402CERM50V5%100PF

R7294NO STUFF

402

1/16W5%

MF-LF

2.2

C7280

ELECC6-SM

16V

CRITICAL

20%68UF C7240

CRITICAL

POLY

39UF-0.027OHM

B1A-SM

L7260

CRITICALPCMB104E4R7-SM

4.7UH-13A-15MOHML7220

CRITICALPCMC063T-SM

4.7UH-10A

R7273100K

1/16WMF-LF

5%

402

C728239UF-0.027OHM

POLY

20%16V

CRITICAL

B1A-SM

C725010UF6.3V20%

603X5R

R7270

402MF-LF1%6.49K1/16W

R72691%

402MF-LF1/16W

10K

X5R

10%

603-1

C7252

CASE-B2-SM

150UF-.025-OHM

TANT6.3V20%

CRITICAL

C72600.1UF10%

40216VX5R

R7267

MF-LF1%

4021/16W

15.0KR72681/16W402

10K1%MF-LF

C7281

X5R

10%25V

603-1

1UF

C7292

CASE-B2-SM

CRITICAL

150UF-.025-OHM

TANT6.3V20%

C7291

CASE-B2-SM

150UF-.025-OHM

CRITICAL

TANT

20%6.3V

C72906.3V20%10UF

603X5R

Q7260CRITICAL

PWRPK-12128SIS426DN

Q7261CRITICAL

SIS426DNPWRPK-12128

U7200CRITICAL

TPS51125

QFN

5V3V3S5_REG5

R7271

MF-LF402

1/16W

75K1%

402MF-LF

1%1/16W

75K

C727210%1UF

X5R25V

603-1

C727010UF6.3V603X5R20%

C7271

402CERM10%10V

5V/3.3V SUPPLY

=PP5V_S3_REGVOLTAGE=5V 3V3S5_ENTRIP

GND_5V3V3S5_SGND

P5V3V3_PGOOD


MIN_LINE_WIDTH=0.6 MM3V3S5_LL

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM3V3S5_DRVH

3V3S5V02VO2

=PP3V3_S5_REGVOLTAGE=3.3VMIN_LINE_WIDTH=1.5 mm

3V3S5_VFB

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM 5V_S3_LL

DIDT=TRUE 5V_S3_VBSTMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

5V_S3_VFB

5V_S3_VFB_XW7203

5VS3_3V3S5_VREF

GND_5V3V3S5_SGND

SMC_PM_G2_EN

3V3S5_VFB_R7270

=P5VS3_EN_L

=P3V3S5_EN_L

5V3V3_REG_EN

5V_S3_LL_SNUBBER

5V_S3_ENTRIP


DIDT=TRUE5V_S3_DRVH

=PPVIN_S3_5VS3


5V_S3_DRVLDIDT=TRUE


MIN_LINE_WIDTH=0.6 MMDIDT=TRUE 3V3S5_VBST

5V_S3_VO1

0.22UF

=PPVIN_S3_5VS3

XW7203SM

PLACEMENT_NOT=PLACE XW7203 BY PIN 1 OF L7260

NO STUFF

C7295


C7273 R7272

PLACEMENT_NOT=PLACE XW7204 BY PIN 2 OF L7220

C7220 16V20%

C72411UF25V

10%0.1UF

WPAKRJK0384DPA

DIDT=TRUE3V3S5_DRVL



Q7220

16V

MIN_NECK_WIDTH=0.2 MMDIDT=TRUE

5V3V3S5_REG3

5%1/16W

2.2

NO STUFF

402MF-LF

R7295

3V3S5_LL_SNUBBER

CRITICAL

PLACEMENT_NOTE=PLACE C7230 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7220

=PPVIN_S5_3V3S5

72 OF 109

B.0.0

051-8568

57 OF 77

2

1

1 2

6

12

3

45

12

12

12

12

2

1

12

2

1

2

1

2

1

2

1

1

2

2

1

1

2

1

2

1

2

21 21

1 2

1

2

2

1

3 4 5

6

7

2

1

1 21 2

2

1

1

2

12

1 2 1 2

2

1

1

2

1

22

1

21

14

22

15

25

1

2

24

19

20

13

18

6

23

7

5

12

11

10

9

17

8

316

4

1

2

1

2

2

1

2

1

2

1

8

56

62

8

8 56

56

7 36 62

8 56

8

VDDQSET

S3

COMP

VTT

THRM_PAD

DRVH

LL

PGNDCS_GND

CS

PGOOD

NC1

S5

NC0

GND VTTGND

MODE

DRVL

VTTREF VLDOIN VBST V5IN VDDQSNS VTTSNSV5FILT

SYM (1 OF 2)

OUT

OUT

S

D

G

S

D

G




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

<RB>

USING KEVIN CONNECTION.

NC

EMI request

EMI request

NC

PM_SLP_S3_L

Place XW7302 by Q7321.

<RA>

Q7321 PIN1,2.3

S5/G3HOT 0.0V

0.0VLOW

LOW

S3

0.0V

HIGH

1.5V

PP0V75_S0

0.75V1.5V

PP1V5_S3

LOW

HIGH

HIGH

PM_SLP_S4_L

S0

STATE

ROUTING NOTE:CONNECT CS_GND TO

PUT 6 VIAS UNDER THE THERMAL PADROUTING NOTE:

Pin 3 and Pin 25

ROUTING NOTE:Place XW7300 between

of U7300.

ROUTING NOTE:

PWM FREQ. = 400 KHZMAX CURRENT = 13APlace XW7303 by C7308.

ROUTING NOTE:

1.5V/0.75V(DDR3) POWER SUPPLYVOUT = 0.75V * (1 + RA / RB)

ROUTING NOTE:Place XW7301 by L7320.

U7300CRITICAL

QFNTPS51116

L7320CRITICAL

SM-IHLP-11.0UH-13A-5.6M-OHM

R73001/16W5%0

402MF-LF

C7309

402X5R10%16V

0.1uF

C7342

2.5VTANT

20%330UF

CRITICAL

CASE-B2-SM

C73416.3VX5R603

10UF20%

C7302

6036.3V10UF20%X5R

R7310

402

1/16WMF-LF

1%10.7K

R73075%4.7MF-LF1/16W402

XW7300

PLACEMENT_NOT=PLACE XW7300 BETWEEN PIN 3 AND PIN 25 OF U7300

SM

OMIT

R732120.0K

MF-LF1/16W

402

1%

R73221/16W402

0.1%MF

20K C7303

CERM50V

100PF5%

402

NO STUFF

C73016.3V20%

603X5R

10UFC73400.033UF16VX5R10%

402

C730722UFX5R-CERM-16.3V

603

20%

C7308

X5R-CERM-1603

22UF20%6.3V

C730010VX5R

1UF10%

402-1

C7343CRITICAL

20%330UF

TANT2.5V

CASE-B2-SM

R7399100K

MF-LF4021/16W5%

C733120%16VPOLY

CRITICAL

B1A-SM

39UF-0.027OHMC7332

603-1

1UF25VX5R10%

C733350V0.001UF20%

402CERM

PLACEMENT_NOTE=PLACE C7333 ACROSS Q7320 PWR AND Q7321 GND

XW7301SM

OMITPLACEMENT_NOTE=PLACE XW7301 BY L7320

XW7302

PLACEMENT_NOT=PLACE XW7302 BY Q7321

SM

OMIT

XW7303

SM

PLACEMENT_NOT=PLACE XW7303 BY C7308OMIT

C7390

402

50VCERM

5%100PF

NO STUFF

R7390

402

1/16W

NO STUFF

MF-LF

2.25%

47 75

47 75

C7345

16V20%

POLY

CRITICAL

B1A-SM

39UF-0.027OHM

R7350

0612MF-11W

0.0011%PLACE NEXT TO L7320

CRITICAL

C734420%50VCERM402

PLACE CLOSE TO L7320

0.001UF

Q7320CSD58858Q33.3X3.3-QFN

CRITICAL

Q7321CRITICAL

CSD58858Q33.3X3.3-QFN

XW7304

SM


OMIT

1.5V/0.75V DDR3 SUPPLY

1V5S3_VBST_RC

DIDT=TRUE

DIDT=TRUE

1V5S3_LLMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mm

1V5S3_V5FILT_XW

ISNS_1V5_S3_N

1V5S3_LL_SNUBBER

MIN_NECK_WIDTH=0.25 mm1V5S3_DRVLMIN_LINE_WIDTH=1 mm

DIDT=TRUE

PP1V5_S3_REG_R

GND_1V5S3_CSGND =PP3V3_S3_PDCISENS

=DDRVTT_EN

DIDT=TRUE1V5S3_VBST

1V5S3_V5FILT =PP5V_S3_1V5S30V75S0

=DDRREG_EN

1V5S3_CS

GND_1V5S3_SGND

=PPVTT_S3_DDR_BUF

DDRREG_PGOOD

=PP0V75_S0_REG

1V5S3_DRVHDIDT=TRUEMIN_LINE_WIDTH=1 mm


1V5S3_VDDQSET

1V5S3_VTTSNS

=PP1V5_S3_REGMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1.5 mm

VOLTAGE=1.5V

ISNS_1V5_S3_P1V5S3_VDDQSNS

=PPVIN_S5_1V5S30V75S0

73 OF 109

B.0.0

051-8568

58 OF 77

9

10

624

25

2120

18

17

16

13

12

11

73 1

4

19

5 23

22

15

8 214

21

1 2

2

1

2

1

2

1

1

2

1 2

1 2

1 2 1 2

2

1

1 2

2

1

2

1

1 2

1 2

1

2 2

1

2

1

1 2

1 2

12

2

1

1

2

1

2

4 3

2 1

2

1

4

321

5

4

321

5

1 2

8

25 63

62

8 26

62

8

8

8

IN

IN

IN

OUT

IN

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT*

NTC

VR_ON

PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3

VID2

VID4

VID5

VID6

PGND2

VIN VDD PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1

BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPADGND

CLK_EN*

IMONOUT

S

G

D

S

G

D

D

G

S

D

G

S




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

IMVP6 CPU VCORE REGULATOR

NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.

0

DPRSTP*

FROM SMC

MAX CURRENT = 44A0

1-PHASE DCM0

MIN_NECK_WIDTHMIN_LINE_WIDTH

(IMVP6_COMP)

(IMVP6_FB)

ERT-J1VR103J

MIN_LINE_WIDTH MIN_NECK_WIDTH

1

1

0

1

1

1

0

1

0

1-PHASE DCM

(IMVP6_ISEN2)

MIN_NECK_WIDTH

DPRSLPVR

MIN_LINE_WIDTH

(GND)

(IMVP6_VO)

(GND)

(NC)

1-PHASE CCM

OPERATION MODE

(IMVP6_VSUM)

2-PHASE CCM

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

PWM FREQ. = 300 KHZ

LOAD LINE SLOPE = -2.1 MV/A

(IMVP6_ISEN1)

PSI*

DCR=0.75MOHMPIMA104E-R36MN0R755

(IMVP6_PHASE1)

(IMVP6_VW)

DCR=0.75MOHMPIMA104E-R36MN0R755

(IMVP6_PHASE2)

(IMVP6_VO)

XW7400OMIT

SM

PLACEMENT_NOTE=PLACE CLOSE TO PIN 21 OF U7400

R740010K

MF-LF402

1/16W1%

R74013.65K

MF-LF402

1/16W1%

C7415

16V

X5R402

10%

0.1UF

R7416

1/16W1%

402

13.7K

MF-LF

R7415

402

10.5K1%1/16WMF-LF

R7405

MF-LF1/16W

402

10K1%

C7404

402

10%6.3VCERM-X5R

0.22uF

R7443

MF-LF402

1%1/16W

3.65K

C7427

16V

402X5R

10%

0.1UF

R7420

MF-LF1/16W

402

105%

R7412

MF-LF1/16W

10

402

5%

C7426

402

10%1UF

CERM6.3V

C74960.01UF

16V10%

CERM402

R74215%

MF-LF1/16W

10

402

C7430

16V10%

402X5R

0.1uF

R7413

1K1%1/16WMF-LF402R7409

MF-LF

1K

1/16W1%

402 R7411255

MF-LF1/16W1%

402

C7414

CERM50V

470PF

402

10%

R741497.6K

MF-LF1/16W1%

402

C7413220PF5%25V

402CERM

C7407

50VCERM

0.001UF

402

10%

R74106.81K

MF-LF1/16W1%

402

R7417

402

1/16W1%5.36K

MF-LF

R7418

1%1K

1/16W

402MF-LF

C7429180pF5%

402CERM

50V

C7428

CERM-X5R402

0.47UF10%6.3V

C74320.001UF

20%

402

50VCERM

R7422

MF-LF1/16W

402

5%0

R7423

402

0

MF-LF

5%1/16W

C7434

CERM-X5R

NOSTUFF

10%10.0V

0.12UF

402

C7435

X5R6.3V20%

603

10UF

C74050.015uF

16V10%

402X7R

R7408147K1%1/16WMF-LF402

C7406

402

0.001UF10%50VCERM

C7416

CERM402

50V

NO STUFF

10%

0.001UF

R7430

1/16WMF-LF

1%

402

3.92K

C7421

6.3VCERM-X5R402

10%

0.22uF

C7403

6.3V

402CERM-X5R

10%

0.22uFR7404

MF-LF

1

1/16W

402

5%

R7407

402MF-LF1/16W5%1

R7431CRITICAL

0603-LF

10KOHM-5%

R74454991%1/16WMF-LF402

R7425

1/16WMF-LF402

05%

R7424

MF-LF402

5%1/16W

0

C740933UF16V

CRITICAL

20%

POLY-TANTCASED2E-SM

C7417

CASED2E-SMPOLY-TANT

20%16V

33UF

CRITICAL

C7408CRITICAL

CASED2E-SMPOLY-TANT

33UF16V20%

C7418

10%25V

1UF

X5R603-1

C74111UF10%

603-1X5R25V

U7400

ISL9504BCRZ

CRITICAL

QFN

R74472.0K

402

5%1/16WMF-LF

C7420

50V20%

402CERM

0.001UF

C7419

PLACEMENT_NOTE=PLACE C7419 ACROSS PINS 1/2/5/6 OF Q7400 AND PINS 3/4 OF Q7401

0.001UF

402

20%50V

CERM

C7422

CERM

20%0.001UF

50V

402

PLACEMENT_NOTE=PLACE C7422 ACROSS PINS 1/2/5/6 OF Q7402 AND PINS 3/4 OF Q7403

C7423

50V

0.001UF20%

402CERM

PLACEMENT_NOTE=PLACE C7423 CLOSE TO PIN 2 OF L7401

C7401

POLY-TANT

33UF20%16V

CRITICAL

CASED2E-SM

Q7400

CRITICAL

S1IRF6710

Q7402S1

IRF6710

CRITICAL

Q7401DIRECTFET-MX

CRITICAL

IRF6795

Q7403CRITICAL

DIRECTFET-MXIRF6795

L7400

PIMA104E-SM

0.36UH-20%-40A-0.00075OHMCRITICAL

L7401CRITICAL

PIMA104E-SM

0.36UH-20%-40A-0.00075OHM

XW7401OMIT

SM

PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7400

XW7402OMIT

SMPLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7400

XW7403OMIT


SM XW7404OMIT

SM


C74310.001UF

50V20%

CERM402

C7433

CERM

20%

0.001UF

50V

402


IMVP6 CPU VCore Regulator

CPU_VID<4>

CPU_VID<0>

IMVP_DPRSLPVR

PM_DPRSLPVR

=PP5V_S0_CPU_IMVP

DIDT=TRUE

IMVP6_BOOT1

CPU_PSI_L

DIDT=TRUE

IMVP6_BOOT1_RC

=PPVIN_S5_CPU_IMVP

IMVP6_SOFT

CPU_VCCSENSE_N

IMVP6_NTC

=PPVIN_S5_CPU_IMVP

IMVP6_ISEN2 0.25 MM 0.25 MM

IMVP6_LGATE2 0.25 MM 0.25 MM

IMVP_VR_ON

IMVP6_VO 0.25 MM 0.20 MM

GND_IMVP6_SGND 0.50 MM 0.20 MM


VOLTAGE=5VMIN_NECK_WIDTH=0.2 MM

PP5V_S0_IMVP6_VDD

0.20 MMIMVP6_DFB 0.25 MM

IMVP6_DROOP 0.25 MM 0.20 MM

0.25 MM0.25 MMIMVP6_VSENIMVP6_RTN 0.25 MM 0.25 MM

IMVP6_VW 0.25 MM0.25 MM

CPU_VID<1>

0.25 MM1.5 MMIMVP6_PHASE1

IMVP6_COMP_RC

CPU_VID<5>

IMVP6_UGATE2 0.25 MM0.25 MM

0.20 MM0.25 MMIMVP6_OCSET

0.25 MMIMVP6_FB2 0.20 MM

0.20 MM0.25 MMIMVP6_COMP0.25 MM1.5 MMIMVP6_UGATE10.25 MM 0.25 MMIMVP6_BOOT1

0.20 MM0.25 MMIMVP6_RBIAS0.20 MM0.25 MMIMVP6_VDIFF

0.20 MM0.25 MMIMVP6_FB

IMVP6_VSUM 0.20 MM0.25 MM

CPU_DPRSTP_L

0.25 MM0.25 MMIMVP6_PHASE2

IMVP6_VDIFF_RC

0.25 MM 0.25 MMIMVP6_ISEN1

=PP3V3_S0_IMVP

1.5 MM 0.25 MMIMVP6_LGATE1

0.20 MM0.25 MMIMVP6_SOFT

0.25 MM0.25 MMIMVP6_BOOT2

IMVP6_BOOT2_RCDIDT=TRUE

CPU_VID<2>

IMVP6_IMON

DIDT=TRUE

IMVP6_BOOT2

IMVP6_VDIFF

CPU_VID<6>


PPVIN_S5_IMVP6_VINMIN_LINE_WIDTH=0.25 MM

DIDT=TRUE

IMVP6_PHASE1

IMVP6_DFB

CPU_VCCSENSE_P

IMVP6_RBIAS

IMVP6_FB2

IMVP6_VR_TT

VR_PWRGOOD_DELAY

IMVP6_DROOP

IMVP6_PHASE2_XW

PPVCORE_S0_CPU_XW_2

=PPVIN_S5_CPU_IMVP

IMVP6_PHASE1_XW

DIDT=TRUE

IMVP6_UGATE1

IMVP6_LGATE1

DIDT=TRUE

IMVP6_ISEN1

PPVCORE_S0_CPU_XW

=PPVCORE_S0_CPU_REG

GND_IMVP6_SGND

CPU_VID<3>


PP3V3_S0_IMVP6_3V3

DIDT=TRUE

IMVP6_LGATE2

DIDT=TRUE

IMVP6_PHASE2

DIDT=TRUE

IMVP6_UGATE2

IMVP6_ISEN2

IMVP6_OCSET

IMVP6_FB

IMVP6_COMP

IMVP6_VW

IMVP6_RTN

VOLTAGE=0VGND_IMVP6_SGND

IMVP6_VO_R

IMVP6_VSUM

IMVP6_VO

IMVP6_VSEN

74 OF 109

B.0.0

051-8568

59 OF 77

2

1

1 2

1

2

2

1

1

2

1

2

1 2 1 2

1

2

2

1

1 2

1 2

2

1

2

1

1 2

2

1

1 2

1

21

2

2

1

1

2

2

1

2

11

2

1 2

1

2

2

1

2

1

1 2

1

2

1

2

2

1

2

1

1 2

1 2

2

1

2

1

1

2

1 2

1 2 1 2

1 2

2

1

1

2

1 2

1 2

1

2

1

2

1

2

2

1

2

1

37

46

25

9

10

11

12

4

5

6

44

1

2

15

14

17

16

18

8

19

23

38

40

39

41

42

43

29

20 22 31

30

28

27

24

33

32

35

34

36

26

48

13

7

45

4921

47

3

1

2

2

1

2

1

2

1

2

1

1

2

3

4

2

1

5

6

3

4

2

1

5

6

5

3 4

71 2 6

5

3 4

71 2 6

21

21

2

1

2

1

2

1

2

11 2

1 2

11 69

11 69

69

21 69

8

58

10

8 58

58

11 69

9

8 58

58

58

36

58

58

58

58

58

58

58

11 69

58

11 69

58

58

58

58 58

58

58

58

58

58

10 14 69

58

58

8

58

58

58

11 69

41

58

58

11 69

58

58

11 69

58

58

9

25

58

8 58

58

58

58

8

58

11 69

58

58

58

58

58

58

58

58

58

58

58

58

58

IN

IN

IN

IN

OUT

OCSET

ICOMP

RBIAS

LGATE

THRM_PAD

FDE

IMON

PVCC

PHASE

UGATE

BOOT

VDD

VSS

VIN

VO

VSEN

VDIFF

FB

COMP

VW

SOFT

PGND

ISN

ISP

RTN

PGOOD

AF_EN

VR_ON

OFFSET1

OFFSET0

VID2

VID1

VID0

G

D

S

G

D

S




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

f = 300 kHz

(MCPCORES0_VO)

OCP=14.5A

(MCPCORES0_VSEN)

MAX CURRENT: 13A

VID<2:0> MCP TARGET

111 +0.70V

101 +0.80V

100 +0.85V

011 +0.90V

010 +0.95V

001 +1.00V

000 +1.05V

(MCPCORES0_RTN)

(MCPCORES0_COMP)

(MCPCORES0_FB)

(MCPCORES0_VDIFF)

(MCPCORES0_ISN)

(MCPCORES0_VW)

110 +0.75V

(Q7560 Limit)

(MCPCORES0_ICOMP)

(MCPCORES0_UGATE)

(MCPCORES0_PHASE)

(MCPCORES0_LGATE)

XW7563SM

OMIT

PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP

XW7562SM

OMIT

PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP

21

21

21

R756820

1/16WMF-LF

1%

402

R756620

1%1/16WMF-LF402

C75700.001UF

402X7R

10%50V

R7563

MF-LF402

1/16W1%100

R7582

1/16W1%

MF-LF

20.0K

402

PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE R7583

1%

MF-LF

20.0K

402

1/16W

PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE

R7592

1/16W

402

5%

MF-LF

0

R7580NOSTUFF

402MF-LF

20.0K1%1/16W


R7581

1%

402

NOSTUFF

20.0K

MF-LF1/16W


R7591

5%

402MF-LF

0

1/16W

C7576

16V

0.022UF10%

CERM-X5R402

R7572

1/16W1%

MF-LF

150K

402

62

62

R7590

MF-LF

0

5%1/16W

402

R7561

1/16W5%

402MF-LF

1K

U7500QFN

ISL6263D

XW7561SM

PLACEMENT_NOTE=PLACE XW7561 CLOSE TO PIN 15 OF U7500

OMIT

R7575

402

1%1/16W

47.0K

MF-LF

R7573

402

1/16WMF-LF

10K1%

R7569

MF-LF

1%1/16W

11.3K

402

R7565

MF-LF603

1

C7564

6035%

10VCERM-X7R

C75501UF10%16V

402X5R

R7560

603

1/10W5%

MF-LF

2.2

C7562

10%

402X5R16V

1UF

R7578

MF-LF1/16W1%

402

100

R7579

1/16W1%

402MF-LF

2.21K

R7577

MF-LF402

1/16W1%

133K

C7580

50V5%

402-1CERM

68PF

C7581

50V10%

402CERM

560PF

R7571

1%100

1/16W

402MF-LF

C7582

50V10%

402CERM

560PF

C7579

10%50V

402X7R

0.001UF

R7576

1/16W1%

402MF-LF

6.98K

R758915%

603MF-LF1/10W

NO STUFF

C7589

10%402

0.001UF50VX7R

NO STUFF

C756610UF

4V20%

603X5R

C7568

CASE-B4-SM

270UF20%2VTANT

CRITICALC7565CRITICAL

CASE-B4-SM

270UF20%2VTANT

C7567

603

10UF

4VX5R

20%

C7561

10%25V

603-1X5R

1UF

PLACEMENT_NOTE=PLACE C7563 ACROSS PIN 5 OF Q7560 AND PINS 1/2/3 OF Q7565

X7R50V10%

R7500

402MF-LF1/16W

100

1%

C7573

402CERM

5%50V

47PF

C7575

402

47PF

CERM

5%50V

R75930

5%

402MF-LF1/16W

R7525

1W1%

0.001

0612MF

L7560

PCMB065T-SM

CRITICAL

0.68UH-16A

C7560

C6-SM

CRITICAL

16VELEC

68UF20%

C7569

X7R

10%50V

402

0.001UF

C757168UF20%

CRITICAL

C6-SMELEC16V

C7590

603

16VX5R

2.2UF10%

Q7565

PWRPK-12128

CRITICAL

SIS426DN

MCP CORE REGULATORSYNC_DATE=02/15/2009SYNC_MASTER=K24_MLB

MCPCORES0_VO

=PPMCPCORE_S0_REG

VOLTAGE=0VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 MM

GND_MCPCORES0_AGND

MCPCORES0_VSEN

MCPCORES0_ICOMP

MCP_VID1_R

5V_S0_MCPREG_VINVOLTAGE=5V


MCPCORES0_VDIFF

MCPCORES0_IMON

MCPCORES0_FB

=PPMCPCORE_S0_REG

MCPCORES0_IMON_R

MCPCORES0_PGOOD

=MCPCORES0_EN

MCPCORES0_RSEN_P

MCPCORES0_COMP_C

MCPCORES0_VDIF_C

MCP_VID<0>

MCPCORES0_RSEN_N

MCP_VID<1>

=PPMCPCORE_S0_REG

MCPCORES0_COMP

MCPCORES0_RBIAS

MCPCORES0_SOFT

MCPCORES0_FDE

MCPCORES0_OS1

MCPCORES0_VW

MCP_VID<2>

MCP_VID2_R

MCPCORES0_OS0

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1V

PPMCPCORE_S0_RMIN_LINE_WIDTH=0.5 MM

MCPCORES0_ISP_R

=PP5V_S0_MCPREG

0.2 MM0.25 MM

DIDT=TRUE

MCPCORES0_BOOT_R

DIDT=TRUE

GATE_NODE=TRUE

MCPCORES0_LGATE MIN_LINE_WIDTH=0.5 MM

MCPCORE_SNUBBER

MCPCORES0_UGATE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MMGATE_NODE=TRUE

DIDT=TRUE

MCP_VID0_RMCPCORES0_PHASE

DIDT=TRUESWITCH_NODE=TRUE


MCPCORES0_RTN

0.25 MM0.2 MM

MCPCORES0_BOOT


5%

PWRPK-12128

CRITICAL

SIS426DNQ7560

MCPCORES0_OCSET

MCPCORES0_ISP

MCPCORES0_ISN


SWITCHNODE

0.22UF

=PPVIN_S0_MCPCORE

402

C75630.001UF


1/10W


75 OF 109

B.0.0

051-8568

60 OF 77

1 2

1 2

1 2

1 2

2

1

1

2

1

2

1

2

1 2

1

2

1

2

1 2

2

11

2

1 2

1

2

3

10

1

21

33

32

28

22

19

18

17

16

15

14

12

8

7

6

5

4

2

20

11

13

9

31

30

29

24

23

27

26

25

1 2

1

2

1

2

1 2

1 2 21

2

1

1 2

2

1

1 2

1 2

1 2

1 2

1 2

1

2

1 2

2

1

1

2

1

2

2

1

2

1

1

2

1

2

2

1

2

1

2

1

1 2

2

1

2

1

1 2

4 3

2 121

1

2

2

1

1

2 2

1

4

1 32

5

4

1 32

5

8 59

41

8 59

8 59

8

8

VBST

TON

LL

DRVH

DRVL

V5FILT V5DRV

PGNDGND

EN_PSV

VOUT

TRIP

VFB

THRM_PAD

PGOOD

SYM 2

IN

OUT

S

D

G

S

D

G




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

<Rb>

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

ROUTING NOTE:


7.2A MAX OUTPUT

VOUT = 1.052V

F = 320 KHZ

Place XW7600 between Pin 7 and Pin 15 of U7600.

(CPUVTTS0_VFB)

(GND)

(=PPCPUVTT_S0_REG)

(=PPCPUVTT_S0_REG)

CPUVTT POWER SUPPLY

ROUTING NOTE:

C7665

X5R

10UF

6.3V

603

20%XW7665SM

OMIT

PLACEMENT_NOTE=Place XW7665 next to L7620

C7670100PF

5%50VCERM

402

NO STUFF

R7670

1%

402MF-LF

1/16W

8.06K

R7671

1%

402

1/16WMF-LF

20.0K

R7603200K

1/16W

402

1%

MF-LF

C7695

X5R

1UF

25V10%

603-1

C7630

20%16V

CRITICAL

POLY-TANT

CASED2E-SM

33UF

C76030.1UF

10%

X7R

603-1

50V

C7604

10%4.7UF

X5R-CERM603

6.3V

U7600

CRITICAL

QFN

TPS51117RGY_QFN14

XW7600OMIT

PLACEMENT_NOT=PLACE XW7600 BETWEEN PIN 7 AND PIN 15 OF U7600

SM

C7601

10%

402-1

10V

X5R

1UF

62

62

R76046.04K1%

402MF-LF

1/16W

R7601301

1%

MF-LF

402

1/16W

C7696

20%0.001UF

50V

402CERM

PLACEMENT_NOTE=PLACE C7696 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7620

C76610.001UF

402

20%50V

CERM

L7620

CRITICAL

PCMB065T-SM

2.2UH-8.0A

XW7601OMIT


SM

C7660

2.5VTANT

CASE-B2-SM

CRITICAL

20%330UF

Q7620CSD58858Q3

CRITICAL

3.3X3.3-QFN

Q7621CRITICAL

CSD58858Q33.3X3.3-QFN

CPU VTT(1.05V) SUPPLYSYNC_MASTER=K24_MLB SYNC_DATE=02/04/2009

CPUVTTS0_VOUT

CPUVTTS0_VFB

GND_CPUVTTS0_SGND



DIDT=TRUEMIN_LINE_WIDTH=0.6MMSWITCH_NODE=TRUE

CPUVTTS0_LL



DIDT=TRUEMIN_NECK_WIDTH=0.2MM

CPUVTTS0_DRVHGATE_NODE=TRUE


DIDT=TRUECPUVTTS0_VBST


CPUVTTS0_TON

=PP5V_S0_CPUVTTS0

CPUVTTS0_VSNSCPUVTTS0_DRVL

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM DIDT=TRUE

=PPVIN_S0_CPUVTTS0

=PPCPUVTT_S0_REG

CPUVTTS0_PGOOD

=CPUVTTS0_EN

CPUVTTS0_TRIP

PP5V_S0_CPUVTTS0_V5FILTMIN_LINE_WIDTH=0.6 mm


76 OF 109

B.0.0

051-8568

61 OF 77

2

12

1

2

11

2

1

2

1

2

2

11

2

2

1

2

1

14

2

12

13

9

4 10

87

1

3

11

5

15

6

1 2

2

1

1

2

1 2

2

1

2

1

21

2

1

1

2

4

321

5

4

321

5

8

8

8

VI

SWENFB

GND

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND THRM_PAD

SS

IN0

IN1

THRML_PAD

EN FB

BIAS

OUT0

OUT1

GND

PG




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

<Rb>

MAX CURRENT = 0.8A

Vout = 1.05V

FREQ = 1.6MHZ

<Ra>

MAX CURRENT = 200MA

<Ra>

1.8V S0 SWITCHER

VOUT = 0.8V * (1 + RA / RB)

MAX CURRENT = 0.5A

Vout = 1.05V

1.05V S0 PLL LDO

<Rb>

VOUT = 0.8V * (1 + RA / RB)

MCP 1.05V S5 (AUXC) SUPPLY

L7760

CRITICAL

PCAA031B-SM

10UH-0.55A-330MOHM

C7762

6.3V

X5R

10uF

603

20%

C7760

603

6.3V

X5R

20%10uF

U7760

CRITICAL

TPS62202SOT23-5

C7771

0805X5R

47UF

CRITICAL

20%6.3V

C7750

CERM805

22UF

CRITICAL

20%6.3V

R778025.5K

1/16W1%

MF-LF402

R7781

1%1/16W

80.6K

402MF-LF

C7776

CERM402

50V5%

47PF

L7770

1V05S5_SW

IHLP1616BZ-SM

2.2UH-3.25A

CRITICAL

62

U7750

CRITICAL

DFN

ISL8009B

R77440

1/16W

LDO_YES

MF-LF402

5%

R7745

LDO_NO

402

1/16W5%

0

MF-LF

C7742

LDO_YES

X5R4V

402

20%4.7UF

C7740

LDO_YESCERM402

6.3V10%1UF

R7743

MF-LF

5%

LDO_YES

100

1/16W

402

C7741

402

6.3V10%1UF

CERM

LDO_YES U7740

CRITICAL

SON

LDO_YES

TPS74701

C7743NOSTUFF

402CERM50V10%

0.0022UF

R7746

LDO_YES

MF-LF

1/16W

402

1%

1.37K

R7747

4.42K

LDO_YES

MF-LF

1/16W

402

1%

R7748

5%

402MF-LF1/16W

0

LDO_YES

R7782NOSTUFF

402

05%1/16WMF-LF

R7783

402

05%1/16WMF-LF

MISC POWER SUPPLIESSYNC_MASTER=K24_MLB SYNC_DATE=03/24/2009

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05VDIDT=TRUE

PP1V05_S0_MCP_PLL_UF_LDO=PP1V5_S0_MCP_PLL_VLDO


=P1V8S0_EN P1V8S0_SWDIDT=TRUE

P1V05S0_LDO_SS


=PP1V05_S0_MCP_PLL_UF_R

P1V05S0_LDO_PGOOD

P1V05S0_LDO_FB



PP3V3_S0_MCP_PLL_VLDO_BIAS

P1V05S0_PGOOD

=PP1V8_S0_REG

=PP3V3_S0_P1V8S0

DIDT=TRUE

1V05S5_FB

=PP1V05_S5_REG

PP3V3_S5_P1V05S5_R_SKIP

P1V05_S5_PGOOD

=P1V05_S5_EN

=PP3V3_S5_P1V05S5

77 OF 109

B.0.0

051-8568

62 OF 77

21

2

1

2

1

2

1

4

3 5

2

1

2

1

1

2

1

2

2

1

21

1

8

6

5

2

3

4

7 9

1 2

1 2

2

1

2

1

1 2

2

1

7

1

2

11

5 8

4

9

10

6

3

2

1

12

12

1 2

1

2

1

2

8

8

62

8 23

8

62

8

8

8

62

8

OUTD

G S

D

G S

OUT

OUT

SENSE

CT

VDD

GND

RESET*

MR*

IN

OUT

OUT

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND THRM_PAD

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

3.3V 1.05V S5 ENABLE

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

VOLTAGE MONITOR

TPS3808 MR* HAS INTERNAL PULLUP

OTHER S0 RAILS PGOOD

(S0PGOOD_PWROK)

353S2310

Battery Off (G3Hot)

State

0 0

1 0

0

Soft-Off (S5)

Sleep (S3)

Run (S0) 1 1

1

PM_SLP_S3_L

0

0

1

1

SMC_PM_G2_ENABLE

1.5V S0 AND 1.05V S0 ENABLE

MCPDDR, CPUVTT,MCPCORES0 ENABLE

3.3V_S0, 1.8V_S0 ENABLE

(PM_SLP_S3_L)

PM_SLP_S4_L

Power Control Signals

S3 ENABLE

NC

V2MON THRESHOLD IS 2.866V

V3MON THRESHOLD IS 0.6VV4MON THRESHOLD IS 0.6V

(PM_S4_STATE_L)

Unused PGOOD signal

56 Q7813

SOD-VESM-HF

SSM3K15FV

Q7800

SOD-VESM-HF

SSM3K15FV

R7802

1/16W

100K

5%

402

MF-LF

25 36

R7813

1/16W

402

68K

MF-LF

5%

C7813

10%

CERM

0.068UF

402

10V

NO STUFF

C7802

10%

NO STUFF

CERM

10V

402

0.068UF

R7801

5%

5.1K

402

MF-LF

1/16W

61

R7812

5%

1/16W

MF-LF

0

402

C7812NO STUFF

0.47UF

10%

6.3V

CERM-X5R

402

R7840

MF-LF

1/16W

402

5%

100K

U7840TPS3808G33DBVRG4

SOT23-6

C7840

CERM

20%

0.1uF

10V

402

C7841

CERM

402

0.001UF20%

50V

C7801

CERM-X5R

0.47UF10%

6.3V

402

56

C7870

CERM

10V

0.1uF

402

20%

56

35

R7859100

402

5%

1/16W

MF-LF

63

U7870OMIT

ISL88042IRTEZTDFN

R7884

402

MF-LF

1/16W

5%

5.1K

C78840.47UF

10%

CERM-X5R

402

6.3V

63

R7870

402

MF-LF

1%

1/16W

10K

R7871

402

1%

20.0K

MF-LF

1/16W

R7892

5%

0

402MF-LF1/16W

R7890

402

1/16WMF-LF

0

5%

R7891

402

5%

MF-LF1/16W

0

R7894

5%

0

1/16WMF-LF402

R7893

402

0

MF-LF

5%1/16W

61

R7895

MF-LF1/16W5%

402

0

63

R7800

5%

MF-LF

402

1/16W

100K

7 36 56

7 21 36 37

R7811

402

5.1K

5%

MF-LF

1/16W

C7810

6.3V

10%

0.47UF

402

CERM-X5R

57

40

R7810

1/16W

100K

5%

402

MF-LF

61

R7883

402

MF-LF

1/16W

5%

10K

R7882

402

0

MF-LF

1/16W

5%

R7881

402

MF-LF

5%

1/16W

33K

R7880

402

5%

1/16W

MF-LF

22K

C78830.47UF

6.3V

10%

CERM-X5R

402

C7882

402

10%

CERM-X5R

0.47UF

NO STUFF

6.3V

C7881

10%

CERM-X5R

0.47UF

6.3V

402

C7880

6.3V

402

10%

0.47UF

CERM-X5R

60

7 21 32 36 66

R7879

1/16W

5%

MF-LF

100K

402

59

R7820

MF-LF

5%

402

1/16W

10K

59

60

63

POWER SEQUENCING

PM_G2_P3V3S5_EN_L

MAKE_BASE=TRUE

=PP1V05_S0_VMON

=PP1V5_S0_VMON

P1V05_S5_PGOOD

RSMRST_PWRGD

=PP3V42_G3H_PWRCTL

TP_U7840_MR_L

P1V05S0_LDO_PGOOD

ALL_SYS_PWRGD

=PP3V3_S5_PWRCTL

P5V3V3_PGOOD

MCPCORES0_PGOOD

=PP3V3_S0_PWRCTL

MAKE_BASE=TRUE

PM_G2_P1V05S5_EN

PP3V3_VMON_VDD

=P5VS3_EN_L

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

P3V3S0_EN =P3V3S0_EN

MAKE_BASE=TRUE

MCPCORES0_EN

TP_DDRREG_PGOOD

=P1V05_S5_EN

=DDRREG_EN

=USB_PWR_EN

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_PWRCTL

=MCPCORES0_EN

=MCPDDR_EN

=CPUVTTS0_EN

=P1V8S0_EN

=PBUSVSENS_EN

=P5VS0_EN

MCPDDR_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CPUVTTS0_EN

MAKE_BASE=TRUE

PM_SLP_S3_L_BUFPM_SLP_S3_L

SMC_PM_G2_EN

=P3V3S5_EN_L

CT

=PP3V3_S0_VMON

PM_SLP_S3_L_INVERT

MAKE_BASE=TRUE

=PP5V_S0_VMON

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_EN

S0PGOOD_PWROK

CPUVTTS0_PGOOD

MAKE_BASE=TRUEPM_SLP_S4_L

=P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_PGOOD

78 OF 109

B.0.0

051-8568

63 OF 77

12

3

12

3

12

12

2

1

2

1

12

1 2

1 2

1

2

5

4

6

2

1

3

2

1

2

1

2

1

2

1

12

2

1

86

5

3

7

4 9

12

2

1

1

2

1

2

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1 2

1 2

1

2

1

2

1

2

1

2

1

2

2

1

2

1

2

1

2

1

1

2

1

2

8

8

61

36

8 62

8

8

8 62

8 62

8

8

57

SG

D

SG

D

D

G S

IN

IN

IN

D

SG

D

SG

IN

D

G S

D

G S

S

G

D

IN

D

SG

D

SG

D

SKELVIN

NC

GND

SENSE

G

OUT

OUT

D

G S

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

1.302 A (EDP)

5.0V LT S0 FET

5.0V RT S0 FET

376S0778

5.0V RT S0 FET

5.0V LT S0 FET

RDS(ON)

MOSFET

CHANNEL

LOADING

TPCP8102

P-TYPE

13.5 MOHM @4.5V

0.48 A (EDP)

13.5 MOHM @4.5V

P-TYPE

TPCP8102

LOADING

CHANNEL

MOSFET

RDS(ON)

LOADING

3.3V S0 FET

LOW THROUGH VTT TERMINATION RESISTORS.

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

BEFORE RAIL IS TURNED OFF, AND REMAINS LOW

WILL EXIT SELF-REFRESH PREMATURELY.

ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS

UNTIL AFTER RAIL TURNS BACK ON OR DIMMS

MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP

1.5V S0 FET

Rome SenseFET

6.3 mOHM @4.5V VGS

5A (EDP)

N-TYPE

LOADING

MOSFET

RDS(ON)

CHANNEL

1.5V S0 FET

(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)

CKT FROM T18

81mW max power

90mA max load @ 0.9V

IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE

MUST GUARANTEE MEM_CKE SIGNALS ARE LOW

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.

MCP79 DDRVTT FET

3.3V S3 FET

FDC638P

P-TYPE

48 mOhm @4.5V

0.182 A (EDP)

CHANNEL

MOSFET

LOADING

RDS(ON)

26 MOHM @4.5V

P-TYPE

FDC606P

3.3V S0 FET

1.431 A (EDP)

RDS(ON)

MOSFET

CHANNEL

3.3V S3 FET

376S0778

Q7910CRITICAL

FDC638P_G

SM

Q7940

23V1K-SM

CRITICAL

TPCP8102

Q7948

23V1K-SM

TPCP8102

CRITICAL

C79420.033UF

10%

16V

X5R

402

C79430.01UF

402

CERM

16V

10%

R7944

5%

MF-LF

402

47K

1/16W

R7943

5%

402

MF-LF

1/16W

47K

Q7947SSM3K15FV

SOD-VESM-HF

62 63

C7911

402

10%

X5R

16V

0.033UF

R7910

402

1/16W

5%

47K

MF-LF

R7912

402

10K

1/16W

MF-LF

5%

C79300.01UF

402

CERM

16V

10%

C7931

10%

402

X5R

16V

0.033UF

R7930

1/16W

MF-LF

402

47K

5%

R7932

402

100K

MF-LF

1/16W

5%

62

62

Q7975SSM6N15FEAPE

SOT563

C7976

402

NO STUFF

0.001UF20%

50V

CERM

R7975

MF-LF

603

10

5%

1/10W

R7976100K

MF-LF

402

1/16W

5%

Q7975SSM6N15FEAPE

SOT563

25 57

Q7903

SOD-VESM-HF

SSM3K15FV

Q7905

SOD-VESM-HF

SSM3K15FV

Q7930FDC606P_GSOT-6

CRITICAL

62

Q7971SSM6N15FEAPE

SOT563

R7971

402

47K

5%

1/16W

MF-LF

Q7971SSM6N15FEAPE

SOT563

C7903

CERM

402

0.068UF

10V

10%

R7903

1/16W

5%

100K

MF-LF

402

R7901

MF-LF

1/16W

402

10K

5%

C7902

CERM

402

20%

10V

0.1UF

Q7901

DFNROME

CRITICAL

41

41

C7940

10%

16V

CERM

402

0.01UF

C7941

402

X5R

16V

10%

0.033UF

C7910

16V

CERM

10%

0.01UF

402

R7940

1/16W

47K

402

MF-LF

5%

R794247K

1/16W

MF-LF

402

5%

Q7945

SOD-VESM-HF

SSM3K15FV

62 63


POWER FETS

=PP5VRT_S0_FET

P5V0LTS0_SS

=PP5V_S3_P5VLTS0FET

=P5VS0_EN

P5V0LTS0_EN_L

P5V0RTS0_SS

=P5VS0_EN

=P3V3S0_EN

=PP3V3_S0_FET

P1V5_S0_SENSE

MCPDDR_SS

=PP5V_S3_MCPDDRFET

MCPDDR_EN_L_RC

=PP1V5_S0_FET

=PP1V5_S3_P1V5S0FET

P1V5_S0_KELVIN

MCPDDR_EN_L

=MCPDDR_EN

=PP5V_S3_VTTCLAMP

VTTCLAMP_EN

VTTCLAMP_L=PPVTT_S0_VTTCLAMP

=DDRVTT_EN

=PP3V3_S3_FET

P3V3S3_SSP3V3S3_EN_L

=P3V3S3_EN

P3V3S0_SS

=PP3V3_S5_P3V3S0FET

P3V3S0_EN_L

=PP3V3_S5_P3V3S3FET

P5V0RTS0_EN_L

=PP5V_S3_P5VRTS0FET

=PP5VLT_S0_FET

79 OF 109

B.0.0

051-8568

64 OF 77

5

6

2

1

4

3

78

56

4

31

2

78

56

4

31

2

2

1

1 21 2

1

2

12

3

2

1

1 2

1

2

1 2

2

1

1 2

1

2

6

12

2

1

12

1

2

3

45

12

3

12

36

52

1

4

3

3

45

1 2

6

12

2

1

1

2

1 2

2

1

7

6

4

51 2 3

9

8

1 2

2

1

1 2

1 2

1

2

12

3

8

8

8

8

8

8

8

8

8

8

8

8

8

SYM_VER-1

FOUR GROUNDING VIAS SHOULD BE DISTRIBUTEDALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY

SYM_VER-1

NC

NC

OUT

OUT

GND THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

LED BKLT I/F

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP LCD CONNECTOR

CAMERA

CAMERA I/F

(LVDS DDC POWER)

LVDS I/F

LVDS CONNECTOR:518S0650

C9012

X5R6.3V20%10UF

603

C9011

16V

0.1UF

402X5R

10%

L9008

0402-LF

120-OHM-0.3A-EMI

CRITICAL

R9014

402

1K5%1/16WMF-LF

C90150.001UF

402

10%

X7R50V

C9010

50V10%

X7R

0.001UF

402

L9080CRITICAL

AMC2012-SM

90-OHM-200MA

C9009

10%

402

16VX5R

0.1UF

J9000F-RT-SM

CRITICAL

20474-030E-11

L9050


C9016

402CERM

20%10V

0.1uF

L9060

CRITICAL

PLACEMENT_NOTE=PLACE CLOSE TO J9000.

90-OHMDLP0NS

20 72

20 72

U9000FPF1009MFET-2X2

CRITICAL

C9017PLACEMENT_NOTE=PLACE CLOSE TO J9000

5%50VC0G-CERM

1000PF

603

R9009100K5%

MF-LF1/16W

402

R9008

1/16WMF-LF

100K5%

402

L9004

0402-LF

FERR-120-OHM-1.5A


LVDS CONNECTORSYNC_MASTER=K24_MLB



=PP5V_S3_CAMERA

VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MM

PP3V3_LCDVDD_SW


=PP3V3_S0_LCD

USB_CAMERA_P

USB_CAMERA_N

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

=PP3V3_S5_LCD

LVDS_IG_PANEL_PWR

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V

PP3V3_S0_LCD_F

LVDS_IG_A_CLK_F_N

LVDS_IG_A_CLK_F_P

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

PPVOUT_S0_LCDBKLT

LED_RETURN_5

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<2>

LVDS_IG_DDC_CLK

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<1>

LED_RETURN_6

LED_RETURN_4

LED_RETURN_3

LED_RETURN_2

LED_RETURN_1



PP5V_S3_CAMERA_F

VOLTAGE=5V

USB_CAMERA_CONN_N

USB_CAMERA_CONN_P

MIN_LINE_WIDTH=0.30 MMVOLTAGE=3.3VMIN_NECK_WIDTH=0.20 MM

PP3V3_LCDVDD_SW_F

LVDS_IG_DDC_DATA

90 OF 109

B.0.0

051-8568

65 OF 77

2

1

2

121

1

2

2

1

2

1

4

3 2

1

2

1

30

29

28

27

26

25

24

23

21

11

16

9

10

6

5

31

33

34

12

13

20

22

17

19

18

8

7

15

14

4

3

2

1

32

2 1

2

1

43

12

6 7

1

2

3

4

5

2

1

1

2

1

2

21

8

8

18 71

18 71

8

18

7

7 71

7 71

7 18 71

7 18 71

7 47 67

7 67

7 18 71

7 18 71

7 18

7 18 71

7 18 71

7 67

7 67

7 67

7 67

7 67

7

7 72

7 72

7

7 18

D

SG

D

GS

BI

BI

BI

BI

BI

BI

D

S G

IN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

or sinks which do both DP and DVI must depend on the

external adapter for pull ups on DDC lines (since DP

Display Port Interoperability spec says that sources

AUX CH has 100K pull up/down on the MLB)..

Q9300

SOT563SSM6N15FEAPE

R930133

5%

MF-LF402

1/16W

R9300

5%1/16W

33

402MF-LF

C93000.1UF

X5R

10%16V

402

Q9301SSM3K15FVSOD-VESM-HF

65

65

18 71

18 71

66 71

66 71

Q9300

SOT563SSM6N15FEAPE

66

18

C9301

402

10%16VX5R

0.1UF

R9302

5%1/16WMF-LF402

100K

R9306

1/16W

402MF-LF

5%1K

DISPLAYPORT SUPPORTSYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009

=PP5V_S0_DP_AUX_MUX

DP_IG_CA_DET

DP_CA_DET

DDC_CA_DET_LS5V_L

DP_IG_DDC_DATAMAKE_BASE=TRUE

DP_IG_DDC_CLKMAKE_BASE=TRUE

=MCP_HDMI_DDC_DATA

MAKE_BASE=TRUE

DP_ML_N<1>

MAKE_BASE=TRUE

DP_ML_P<0>

=MCP_HDMI_TXC_N

DP_ML_P<3>MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_ML_N<3>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<2>

=MCP_HDMI_TXD_N<2>MAKE_BASE=TRUE

DP_ML_N<0>

MAKE_BASE=TRUE

DP_ML_P<1>MAKE_BASE=TRUE

DP_ML_N<2>MAKE_BASE=TRUE

DP_ML_P<2>

=MCP_HDMI_HPD DP_HPDMAKE_BASE=TRUE

=MCP_HDMI_DDC_CLK

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXC_P

DP_AUX_CH_C_P

DP_IG_DDC_DATA

DP_AUX_CH_SW_P

DP_IG_AUX_CH_P

DP_AUX_CH_SW_N

DP_AUX_CH_C_N

DP_IG_DDC_CLK

DP_IG_AUX_CH_N

93 OF 109

B.0.0

051-8568

66 OF 77

6

12

1 2

1 2 1 2

12

3

3

45

1 2

1

2

1

2

8

65

65

18

66 71

66 71

18

66 71

66 71

18

18

18 66 71

66 71

66 71

66 71

18 66

18

18

18

18

18

71

71

OUT

BI

IN

IN

IO

NC NC

IO

GND

OUT

IO

NC NC

IO

GND

IO

NC NC

IO

GND

IO

NC NC

IO

GND

IN

IN

IN

IN

IN

IN

G

D

S

G

D

S

SYM_VER-2

SYM_VER-2

SYM_VER-2

SYM_VER-2

G

D

S

G

D

S

BI

IN

IN

OC*

OUT

EN

GND

GND

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

GND

DP_PWR

ML_LANE2PAUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P

ML_LANE3N

ML_LANE2N

CONFIG1

CONFIG2

BOT ROW TOP ROWTH PINS SM PINS

SHIELD PINS




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

HAVE BEEN USED BEACUSE ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES

POR IS PLASTIC MINI DP CONNECTOR BUT METAL PART’S SCHEMATIC AND CAD SUMBOLS

514-0691

Port Power Switch

Cable Adapter

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

down HPD input with

DP to DVI/HDMI

DP Source must pull

greater than or equal

pull-up to DP_PWR.

to 100K (DPv1.1a).

(CA) has 100k

down HPD input with

MCP79 requires pull

100K if DP_HPD is used.

65

65 71

65 71

65 71

R9421

MF-LF

100K

1/16W

5%

402

3

D9411

CRITICAL

DP_ESD

SLP2510P8

RCLAMP0524P

C941516V

0.1uFX5R10% 402

C941440210% X5R

0.1uF16V

65

C941110% 16V 402

0.1uFX5R

C941016V10% 402X5R

0.1uF

R9420

1/16W

MF-LF

5%

100K

402

3

D9410

DP_ESD

CRITICAL

SLP2510P8

RCLAMP0524P

52

D9400

SC70-6-1

RCLAMP0504F

CRITICAL

DP_ESD

3

D9411

SLP2510P8

DP_ESD

CRITICAL

RCLAMP0524P

R94251M

1/16W

5%

MF-LF

402

3

D9410

DP_ESD

SLP2510P8

CRITICAL

RCLAMP0524P

C941716V10% 402X5R

0.1uF

C941616V10% 402X5R

0.1uF

C941316V10% 402X5R

0.1uF

C9412

0.1uF16V 402X5R10%

65 71

65 71

65 71

65 71

C9400

X5R-CERM

6.3V

20%

4.7UF

402

L9400

0603

FERR-120-OHM-3A

R9423100K

402

1/16W

MF-LF

5%

65 71

65 71

Q94402N7002DW-X-G

SOT-363

Q9440

SOT-363

2N7002DW-X-G

R9443

1/16W

402

MF-LF

5%

100KR9442

100K

1/16W

402

5%

MF-LF

FL9401TCM1210-4SM12-OHM-100MA

FL940212-OHM-100MATCM1210-4SM

FL9400

TCM1210-4SM12-OHM-100MA

FL9403TCM1210-4SM12-OHM-100MA

R9444

1/16W

402

5%

MF-LF

10K

R9445

5%

1/16W

402

MF-LF

10K

Q9441

SOT-363

2N7002DW-X-G

R9422

MF-LF

1/16W

402

5%

1M

Q9441

SOT-363

2N7002DW-X-G

R9446100K

402

1/16W

MF-LF

5%

C9480

20%22UF

X5R-CERM-1603

6.3V

C9481

20%

X5R-CERM

6.3V

4.7UF

402

C9485

6.3VX5R-CERM-1

22UF

603

20%

C9486

603X5R-CERM-16.3V

22UF

CRITICAL

20%

65 71

7 21 32 36 62

U9480

SOT23TPS2051B

CRITICAL

J9400MINIDSPLYPRT-K83

OMIT

F-RT-THSM

CRITICAL

SYNC_MASTER=K24_MLB

DisplayPort ConnectorSYNC_DATE=04/06/2009

DP_ML_CONN_N<0>

DP_CA_DET_Q

DP_ML_CONN_N<3>DP_ML_C_N<3>

DP_AUX_CH_C_P

DP_AUX_CH_C_N

=PP3V3_S0_DPCONN

TP_DPPWR_OC_L

DP_ML_CONN_P<0>

DP_ML_P<3>

DP_ML_C_N<2>

DP_ML_C_P<2>

DP_ML_C_N<1>

DP_ML_C_P<1>

DP_ML_C_P<0>

DP_ML_C_N<0> DP_ML_N<0>

DP_CA_DET_L_Q

=PP3V3_S0_DPCONN

DP_CA_DET

DP_HPD_L_Q

DP_ML_N<3>

DP_ML_P<0>

DP_ML_P<1>

DP_ML_N<1>

DP_ML_P<2>

DP_ML_N<2>

DP_HPD

PM_SLP_S3_L

=PP3V3_S5_DP_PORT_PWR

DP_ML_C_P<3>

DP_ML_CONN_P<3>



PP3V3_S0_DPILIM

DP_ML_CONN_P<1>

HDMI_CEC

PP3V3_S0_DPPWRMIN_LINE_WIDTH=0.38 MM


DP_ML_CONN_N<2>

DP_ML_CONN_P<2>

DP_ML_CONN_N<1>

DP_HPD_Q

94 OF 109

B.0.0

051-8568

67 OF 77

1

2

1

10

2

9

1 2

1 2

1 2

1 2

1

2

4

7

5

6

1

3

6

4

4

7

5

6

1

2

1

10

2

9

1 2

1 2

1 2

1 2

2

1

21

1

2

3

5

4

6

2

1

1

2

1

2

4

32

1

4

32

1

4

32

1

4

3 2

1

1

2

1

2

3

5

4

1

2

6

2

1

1

2

2

1

2

1

2

1

2

1

5

3

1

2

4

22

1

7

5

3

9

13

11

8

14

21

20

1516

19

2

18

10

12

17

4

6

71

71 71

8 66

71

71

71

71

71

71

71

8 66

8

71

71 71

71

71

71

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

VIN

VDC2

VDC1

EN

WAKE

PWM

COMP

OVP

VOUT

SWB

SWA

FAIL

THRM

PGNDB

PGNDA

GND

ISET

CH1

CH2

CH3

CH4

CH5

CH6

PAD




36

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D

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Apple Inc.

PAGE


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B

C

345678

D

B

8 7 5 4 2 1

ISET = 153mA / <Riset>

<Riset>

f = 600kHz

<Rb>

OVP = Vovp * (1 + Ra/Rb)

VOVP = 6.9V +/- 0.35V

PLACEMENT_NOTEs:

(C9710-C9711)

(SGND) <Ra>

PLACEMENT_NOTEs:

(C9721-C9726)

WF: C9711 AND C9717 NOT IN REF SCHEMATIC.

13.3 Inch Panel (9 LEDs per string)TARGET: ISET = 20MA, OVP = 35V

ACTUAL: ISET = 19.9MA, OVP = 35.2V

C9722

PLACE NEAR U9700

5%50VCERM402

100PF

NOSTUFF

C9724

5%50V

100PF

402

NOSTUFF

PLACE NEAR U9700

CERM

C9723100PF

50VCERM

PLACE NEAR U9700

402

5%

NOSTUFF

C9726100PF

50VCERM

5%

402

PLACE NEAR U9700

NOSTUFF

C9725

50VCERM

5%

PLACE NEAR U9700100PF

NOSTUFF

402

XW9700

PLACEMENT_NOT=PLACE XW9700 FAR FROM THE NOISY PINS 3 AND 4

SM

OMIT

R971710.2

MF-LF

1%1/16W

402

R9718

1/16WMF-LF

1%

10.2

402R9720

402

10.2

1%1/16WMF-LF

R972110.2

1%

402

1/16WMF-LF

R9722

1/16W

402

10.2

MF-LF

1%

R9719

402

1/16W

10.2

MF-LF

1%

R9702

NOSTUFF

MF-LF

5%1/16W

402

0

R9730

402MF-LF

5%10

1/16W

C9713

PLACEMENT_NOTE=PLACE CLOSE TO L9710

0.1UF

402

25V

X5R

10%

1%

R9700CRITICAL

0.020

805MF-LF0.25W

47 75

47 75

R97250

5%

MF-LF1/16W

402

R9726

MF-LF

5%

402

1/16W

22K

XW9701OMIT

SM

0.0022UF

C9705

CERM

50V10%

402

R970510K

1/16W1%

402MF-LF

C9727PLACEMENT_NOTE=PLACE CLOSE TO U9700 PIN 1

603

50VC0G-CERM

5%1000PF

L971010UH-2.1A

IHLP2020BZ11-SM

CRITICAL

C97154.7UF

CRITICAL

20%

X7R-CERM50V

1206

C9716

10%50VX7R

2.2UF

CRITICALNOSTUFF

1206

D9710SOD-123

CRITICAL

RB160M-40

PLACEMENT_NOTE=PLACE NEAR L9710

7 64

7 64

7 64

7 64

7 64

7 64

C9710PLACEMENT_NOTE=PLACE CLOSE TO L9710

10%

X5R25V

805

10UF

CRITICAL

C9700

10VX5R-CERM

2.2UF20%

402

2.2UFC9701

X5R-CERM10V20%

402

R9716

402

1%1/16WMF-LF

243K

R9715

MF-LF402

1%1M

1/16W

C9711

25V

603-1

1UF

X5R

10%

R9710

1%1/16WMF-LF

7.68K

402

C970656PF

50VCERM

5%

402

18 68

C9717

603X7R100V10%1000PF

PLACEMENT_NOTE=PLACE C9717 CLOSE TO D9710 PIN 2 & XW9701

C9721NOSTUFF

5%

PLACE NEAR U9700

402CERM

100PF

50V

SYNC_MASTER=VEMURI_K19I SYNC_DATE=02/09/2009

LCD Backlight Driver (MC34845)

VOLTAGE=9VMIN_NECK_WIDTH=0.38 MM

PPVIN_BKL

VOLTAGE=0V

GND_LCDBKLT_SGNDMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.24 MM


PP2V5_S0_LCDBKLTMIN_LINE_WIDTH=0.3 MM

VOLTAGE=2.5V


BKL_MC_CH2


BKL_MC_CH3MIN_LINE_WIDTH=0.5 mm


LCDBKLT_VIN

BKL_MC_CH5


LCDBKLT_FAIL

ISNS_LCDBKLT_P

VOLTAGE=50V

MIN_LINE_WIDTH=0.5 MMPPVOUT_S0_LCDBKLT


MIN_NECK_WIDTH=0.4 MMMIN_LINE_WIDTH=0.6 mmGND_LCDBKLT_PGNDGND_LCDBKLT_PGND

DIDT=TRUE

PPVOUT_S0_LCDBKLT_SW

SWITCH_NODE=TRUEVOLTAGE=50VMIN_NECK_WIDTH=0.38 MMMIN_LINE_WIDTH=0.5 MM

ISNS_LCDBKLT_N

LCDBKLT_OVP

LCDBKLT_ISETMIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mmLED_RETURN_3

MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mmLED_RETURN_2

MIN_LINE_WIDTH=0.5 mmLED_RETURN_4


LED_RETURN_6MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm

LED_RETURN_1MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mmLED_RETURN_5


LCDBKLT_COMP_RC

MIN_LINE_WIDTH=0.3 MMPP5V5_S0_LCDBKLT



BKL_MC_CH1

BKL_MC_CH6MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm

BKL_MC_CH4


MIN_LINE_WIDTH=0.2 MMLCDBKLT_COMP

LVDS_IG_BKL_PWM_RLVDS_IG_BKL_PWM



U9700


LLP

CRITICAL

MC34845CEP

97 OF 109

B.0.0

051-8568

68 OF 77

2

1

2

1

2

1

2

1

2

1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

2

1

2

2

143

21

12

1

2

1 2

2

1

1

2

2

1

21

2

1

2

1

1 2

2

1

2

1

2

1

1

2

1

2

2

1

1

2

2

1

2

1

1

23

20

6

18

16

17

22

24

3

4

14

2525

21

13

19

15

7

8

9

10

11

12

2

1

68 7 47 64

67 67

OUT

IN

IN

D

SG

D

SGIN




36

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D

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Apple Inc.

PAGE


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B

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345678

D

B

8 7 5 4 2 1

MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS

PPBUS S0 LCDBkLT FET

CHANNEL

MOSFET

RDS(ON)

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.4 A (EDP)LOADING

F9800

2AMP-32V

0402-HF

67

R9808

1/16W

MF-LF

301K

1%

402

R9809

147K

1%

MF-LF

1/16W

402

C9802

16V

10%

X5R

0.1UF

402

8

Q9806

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

R9841

5%

MF-LF

1/16W

1K

402

R98401K5%

1/16W

MF-LF

402

25

Q9807

SOT563

SSM6N15FEAPE

Q9807SSM6N15FEAPE

SOT563

18 68


LCD Backlight Support

LVDS_IG_BKL_ON

LVDS_IG_BKL_ON

VOLTAGE=12.6V



=PPBUS_S0_LCDBKLT

BKLT_EN_L

BKLT_PLT_RST_L



VOLTAGE=12.6V


LVDS_IG_BKL_PWM

VOLTAGE=12.6V



PPBUS_S0_LCDBKLT_FUSED

PPBUS_S0_LCDBKLT_EN_DIV

PPBUS_S0_LCDBKLT_EN_L

98 OF 109

B.0.0

051-8568

69 OF 77

21

1

2

1

2

2

1

3

12

56

4

1

2

1

2

6

12

3

45

18 68

18 67

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD
























36

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Apple Inc.

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345678

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8 7 5 4 2 1

















Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5


CPU Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MCP FSB COMP Signal Constraints

Some signals require 27.4-ohm single-ended impedance.

FSB Clock Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SR DG recommends at least 25 mils, >50 mils preferred

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

PHYSICAL

FSB 2X

FSB 4X Signal Groups

ELECTRICAL_CONSTRAINT_SET

FSB 1X Signals

SPACING

NET_TYPE

Signals

(See above)

(FSB_CPURST_L)

(CPU_VCCSENSE)

(CPU_VCCSENSE)

CPU / FSB Net PropertiesFSB (Front-Side Bus) Constraints

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 4X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.

FSB 2X signals / groups shown in signal table on right.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.

*CLK_FSB ?=3x_DIELECTRIC

CLK_FSB_100D * =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

MCP_FSB_COMP ?* 8 MIL

=STANDARD=STANDARD* =50_OHM_SE =50_OHM_SE=50_OHM_SEMCP_50S =50_OHM_SE

25 MIL ?CPU_VCCSENSE *

?*CPU_GTLREF 25 MIL

=2:1_SPACING ?*CPU_ITP

25 MIL*CPU_COMP ?

* ?CPU_8MIL 8 MIL

=STANDARD* ?CPU_AGTL

CPU_27P4S 7 MIL 7 MIL=27P4_OHM_SE=27P4_OHM_SE* =27P4_OHM_SE =27P4_OHM_SE

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SECPU_50S =STANDARD=STANDARD*

TOP,BOTTOM ?CLK_FSB =4x_DIELECTRIC

=2x_DIELECTRICTOP,BOTTOM ?CPU_AGTL


CPU/FSB Constraints

* =1:1_DIFFPAIR =1:1_DIFFPAIRFSB_DSTB_50S =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE

=4x_DIELECTRIC ?FSB_ADSTB TOP,BOTTOM

=50_OHM_SE =STANDARD=50_OHM_SE=50_OHM_SEFSB_50S =STANDARD* =50_OHM_SE

=4x_DIELECTRICFSB_DATA ?TOP,BOTTOM

=5x_DIELECTRIC ?FSB_DSTB TOP,BOTTOM

=3x_DIELECTRIC ?TOP,BOTTOMFSB_ADDR

=3x_DIELECTRIC ?TOP,BOTTOMFSB_1X

=2x_DIELECTRIC ?*FSB_DATA

=3x_DIELECTRIC*FSB_DSTB ?

?FSB_ADDR * =STANDARD

* ?FSB_1X =STANDARD

=2x_DIELECTRIC* ?FSB_ADSTB

FSB_DATA_GROUP0 FSB_50S FSB_DINV_L<0>FSB_DATA

FSB_50SFSB_1X FSB_1X FSB_LOCK_L

CPU_50SCPU_ASYNC CPU_A20M_LCPU_AGTL

FSB_50S FSB_DATAFSB_DATA_GROUP2 FSB_D_L<47..32>

FSB_DSTB_L_N<1>FSB_DSTB_50S FSB_DSTBFSB_DSTB1

FSB_ADSTBFSB_50S FSB_ADSTB_L<0>FSB_ADSTB0

CPU_VID<6..0>CPU_50S CPU_8MIL

CPU_50S IMVP6_VID<6..0>CPU_8MIL

CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_P

CPU_VCCSENSE IMVP6_VSEN_NCPU_27P4S

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_N

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P

XDP_CPURST_LCPU_ITPCPU_50S

XDP_BPM_L5 CPU_50S CPU_ITP XDP_BPM_L<5>

XDP_BPM_L CPU_50S XDP_BPM_L<4..0>CPU_ITP

XDP_TRST_L CPU_50S CPU_ITP XDP_TRST_L

XDP_TCK CPU_50S CPU_ITP XDP_TCK

XDP_TMS CPU_50S CPU_ITP XDP_TMS

XDP_TDO CPU_50S CPU_ITP XDP_TDO

XDP_TDI CPU_50S CPU_ITP XDP_TDI

CPU_COMP CPU_COMPCPU_27P4S CPU_COMP<0>

CPU_COMP CPU_COMP<1>CPU_50S CPU_COMP

CPU_COMP CPU_COMP<2>CPU_27P4S CPU_COMP

CPU_COMP CPU_50S CPU_COMP<3>CPU_COMP

CPU_GTLREF CPU_GTLREFCPU_50S CPU_GTLREF

CPU_50S CPU_AGTL IMVP_DPRSLPVR

CPU_50SPM_DPRSLPVR CPU_AGTL PM_DPRSLPVR

CPU_IERR_L CPU_50S CPU_IERR_L

FSB_CLK_MCP CLK_FSBCLK_FSB_100D FSB_CLK_MCP_N

FSB_CLK_MCP CLK_FSBCLK_FSB_100D FSB_CLK_MCP_P

FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_N

FSB_CLK_ITP CLK_FSBCLK_FSB_100D FSB_CLK_ITP_P

FSB_CLK_CPU FSB_CLK_CPU_NCLK_FSBCLK_FSB_100D

FSB_CLK_CPU FSB_CLK_CPU_PCLK_FSBCLK_FSB_100D

MCP_FSB_COMPMCP_CPU_COMP MCP_CPU_COMP_GNDMCP_50S

MCP_FSB_COMPMCP_CPU_COMP MCP_CPU_COMP_VCCMCP_50S

MCP_FSB_COMPMCP_CPU_COMP MCP_BCLK_VML_COMP_GNDMCP_50S

MCP_FSB_COMPMCP_CPU_COMP MCP_BCLK_VML_COMP_VDDMCP_50S

CPU_50SCPU_ASYNC FSB_DPWR_LCPU_AGTL

CPU_50SCPU_DPRSTP_L CPU_DPRSTP_LCPU_AGTL

CPU_50SCPU_FROM_SB CPU_DPSLP_LCPU_AGTL

CPU_50SFSB_CPUSLP_L FSB_CPUSLP_LCPU_AGTL

CPU_50SPM_THRMTRIP_L PM_THRMTRIP_LCPU_8MIL

CPU_50SCPU_ASYNC CPU_STPCLK_LCPU_AGTL

CPU_50SCPU_ASYNC CPU_SMI_LCPU_AGTL

CPU_50SCPU_PWRGD CPU_PWRGDCPU_AGTL

CPU_50SCPU_PROCHOT_L CPU_PROCHOT_LCPU_AGTL

CPU_50SCPU_ASYNC_R CPU_NMICPU_AGTL

CPU_50SCPU_ASYNC_R CPU_INTRCPU_AGTL

CPU_50SCPU_INIT_L CPU_INIT_LCPU_AGTL

CPU_50SCPU_ASYNC CPU_IGNNE_LCPU_AGTL

CPU_50SCPU_FERR_L CPU_FERR_LCPU_8MIL

CPU_50SCPU_BSEL CPU_BSEL<2..0>CPU_AGTL

FSB_50SFSB_1X FSB_TRDY_LFSB_1X

FSB_50SFSB_1X FSB_RS_L<2..0>FSB_1X

FSB_50SFSB_CPURST_L FSB_CPURST_LFSB_1X

FSB_50SFSB_1X FSB_1X FSB_HITM_L

FSB_50SFSB_1X FSB_HIT_LFSB_1X

FSB_50SFSB_1X FSB_DRDY_LFSB_1X

FSB_50SFSB_1X FSB_DEFER_LFSB_1X

FSB_50SFSB_1X FSB_DBSY_LFSB_1X

FSB_50SFSB_1X FSB_1X FSB_BPRI_L

FSB_50SFSB_1X FSB_1X FSB_BNR_L

FSB_50S FSB_BREQ1_LFSB_BREQ1_L FSB_1X

FSB_50SFSB_BREQ0_L FSB_BREQ0_LFSB_1X

FSB_50SFSB_1X FSB_1X FSB_ADS_L

FSB_ADSTB_L<1>FSB_ADSTB1 FSB_ADSTBFSB_50S

FSB_50SFSB_ADDR_GROUP1 FSB_ADDR FSB_A_L<35..17>

FSB_ADDR_GROUP0 FSB_REQ_L<4..0>FSB_ADDRFSB_50S

FSB_ADDRFSB_ADDR_GROUP0 FSB_A_L<16..3>FSB_50S

FSB_DSTB_50S FSB_DSTBFSB_DSTB3 FSB_DSTB_L_N<3>

FSB_DSTB_50S FSB_DSTB_L_P<3>FSB_DSTBFSB_DSTB3

FSB_50SFSB_DATA_GROUP3 FSB_DINV_L<3>FSB_DATA

FSB_50S FSB_D_L<63..48>FSB_DATA_GROUP3 FSB_DATA

FSB_DSTB_50S FSB_DSTBFSB_DSTB2 FSB_DSTB_L_N<2>

FSB_DSTB_50S FSB_DSTB_L_P<2>FSB_DSTBFSB_DSTB2


FSB_DSTB_50SFSB_DSTB1 FSB_DSTB FSB_DSTB_L_P<1>


FSB_50SFSB_DATA_GROUP1 FSB_D_L<31..16>FSB_DATA

FSB_DSTB_50SFSB_DSTB0 FSB_DSTB FSB_DSTB_L_N<0>

FSB_DSTB_50S FSB_DSTBFSB_DSTB0 FSB_DSTB_L_P<0>

FSB_DATA_GROUP0 FSB_50S FSB_D_L<15..0>FSB_DATA

100 OF 109

B.0.0

051-8568

70 OF 77

10 14

10 14

10 14

10 14

10 14

10 14

11 58

11 58

11 58

13

10 13

10 13

10 13

10 13

10 13

10 13

10 13

10

10

10

10

10 26

58

21 58

10

14

14

13 14

13 14

10 14

10 14

14

14

14

14

10 14

10 14 58

10 14

10 14

10 14 37

10 14

10 14

10 13 14

10 14 37

10 14

10 14

10 14

10 14

10 14

9 10

10 14

10 14

10 13 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14




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C

A

D

2 1


Apple Inc.

PAGE


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B

C

345678

D

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8 7 5 4 2 1

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM
























































Memory Net Properties

DQ signals should be matched within 20 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.

All DQS pairs should be matched within 100 ps of clocks.

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.

A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

NET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET PHYSICAL

Memory Bus Constraints

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Spacing Group Assignments

Need to support MEM_*-style wildcards!

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ signals should be matched within 5 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps

No DQS to clock matching requirement.

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.

A/BA/cmd signals should be matched within 5 ps of CLK pairs.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

MCP MEM COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

DDR3:

DDR2:


Memory Constraints

MEM_CLK * MEM_DQS2MEMMEM_DQS

MEM_CTRL * MEM_DQS2MEMMEM_DQS

MEM_CMDMEM_DQS MEM_DQS2MEM*

=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF* =70_OHM_DIFF =70_OHM_DIFFMEM_70D

=70_OHM_DIFF=70_OHM_DIFF* =70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFFMEM_70D_VDD

MEM_40S =STANDARD* =STANDARD=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

MEM_40S_VDD =40_OHM_SE=40_OHM_SE=40_OHM_SE =STANDARD* =STANDARD=40_OHM_SE

=1.5:1_SPACINGMEM_CMD2CMD * ?

MEM_CTRL2CTRL =2:1_SPACING* ?

MEM_CLK2MEM * ?=4:1_SPACING

MEM_CTRL2MEM * ?=2.5:1_SPACING

MEM_DATA2DATA * ?=1.5:1_SPACING

MEM_CMD2MEM * ?=3:1_SPACING

MEM_DATA2MEM =3:1_SPACING* ?

25 MILMEM_2OTHER * ?

?=3:1_SPACINGMEM_DQS2MEM *

MEM_CMD * MEM_CMD2MEMMEM_CLK

*MEM_CMD MEM_CMD2MEMMEM_CTRL

*MEM_CMD MEM_CMD MEM_CMD2CMD

*MEM_CMD MEM_CMD2MEMMEM_DATA

MEM_CMD2MEMMEM_CMD *MEM_DQS

* MEM_DATA2MEMMEM_DATA MEM_CLK

MEM_DATA * MEM_DATA2MEMMEM_CTRL

MEM_DATA2MEMMEM_DATA *MEM_DQS

MEM_DATA MEM_DATA2DATAMEM_DATA *

MEM_DATA2MEMMEM_DATA *MEM_CMD

MEM_2OTHERMEM_CLK **

MEM_2OTHERMEM_CTRL * *

MEM_2OTHERMEM_DQS **

MEM_2OTHERMEM_CMD **

MEM_2OTHERMEM_DATA * *

MEM_CLK MEM_CLK MEM_CLK2MEM*

MEM_CLK MEM_CTRL MEM_CLK2MEM*

MEM_CMD MEM_CLK2MEMMEM_CLK *

MEM_DATA *MEM_CLK MEM_CLK2MEM

MEM_DQS MEM_CLK2MEMMEM_CLK *

MEM_CTRL MEM_CTRL2MEMMEM_CLK *

MEM_CTRL2CTRLMEM_CTRL *MEM_CTRL

MEM_DATA MEM_CTRL2MEM*MEM_CTRL

MEM_DQSMEM_CTRL * MEM_CTRL2MEM

MEM_CMD * MEM_CTRL2MEMMEM_CTRL

MEM_DATA * MEM_DQS2MEMMEM_DQS

MEM_DQSMEM_DQS MEM_DQS2MEM*

=STANDARD7 MIL7 MILYMCP_MEM_COMP * =STANDARD =STANDARD

MCP_MEM_COMP 8 MIL* ?

MEM_DQS MEM_A_DQS_N<6>MEM_A_DQS6 MEM_70D

MEM_A_DQS_P<0>MEM_70D MEM_DQSMEM_A_DQS0

MEM_40SMEM_A_DQ_BYTE7 MEM_A_DM<7>MEM_DATA

MEM_40S_VDD MEM_A_A<14..0>MEM_CMDMEM_A_CMD

MEM_40S_VDD MEM_B_A<14..0>MEM_CMDMEM_B_CMD

MEM_40S_VDD MEM_CMD MEM_B_RAS_LMEM_B_CMD

MEM_40S_VDD MEM_CMD MEM_B_CAS_LMEM_B_CMD

MEM_70D MEM_DQS MEM_A_DQS_P<7>MEM_A_DQS7


MCP_MEM_COMP_GNDMCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MCP_MEM_COMP_VDDMCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MEM_B_CLK MEM_CLK MEM_B_CLK_P<5..0>MEM_70D_VDD

MEM_B_CLK MEM_B_CLK_N<5..0>MEM_CLKMEM_70D_VDD

MEM_40S_VDD MEM_CTRLMEM_B_CNTL MEM_B_CS_L<3..0>

MEM_40S_VDD MEM_CTRLMEM_B_CNTL MEM_B_ODT<3..0>

MEM_DATAMEM_40S MEM_B_DM<1>MEM_B_DQ_BYTE1



MEM_DQSMEM_70D MEM_B_DQS_N<7>MEM_B_DQS7




MEM_DQSMEM_70D MEM_B_DQS_P<3>MEM_B_DQS3










MEM_DQS MEM_B_DQS_N<4>MEM_70DMEM_B_DQS4






MEM_40S_VDD MEM_CMD MEM_B_BA<2..0>MEM_B_CMD


MEM_DATAMEM_40S MEM_B_DQ<7..0>MEM_B_DQ_BYTE0




MEM_40S_VDD MEM_CMD MEM_B_WE_LMEM_B_CMD



MEM_DATA MEM_B_DQ<39..32>MEM_40SMEM_B_DQ_BYTE4


MEM_40SMEM_A_DQ_BYTE5 MEM_DATA MEM_A_DQ<47..40>

MEM_40SMEM_A_DQ_BYTE4 MEM_DATA MEM_A_DQ<39..32>

MEM_40S_VDD MEM_CMD MEM_A_RAS_LMEM_A_CMD

MEM_40S MEM_A_DQ<15..8>MEM_A_DQ_BYTE1 MEM_DATA

MEM_40S MEM_DATA MEM_A_DQ<23..16>MEM_A_DQ_BYTE2

MEM_40S_VDD MEM_A_WE_LMEM_A_CMD MEM_CMD

MEM_40SMEM_A_DQ_BYTE3 MEM_A_DQ<31..24>MEM_DATA

MEM_40S_VDDMEM_A_CMD MEM_CMD MEM_A_CAS_L

MEM_40S MEM_DATA MEM_A_DQ<63..56>MEM_A_DQ_BYTE7




MEM_40S_VDD MEM_CMDMEM_A_CMD MEM_A_BA<2..0>


MEM_DQS MEM_A_DQS_P<6>MEM_A_DQS6 MEM_70D


MEM_70D MEM_DQS MEM_A_DQS_N<5>MEM_A_DQS5





MEM_DQSMEM_A_DQS1 MEM_A_DQS_P<1>MEM_70D






MEM_40SMEM_A_DQ_BYTE5 MEM_DATA MEM_A_DM<5>




MEM_40S_VDDMEM_A_CNTL MEM_A_CS_L<3..0>MEM_CTRL

MEM_40S_VDDMEM_A_CNTL MEM_A_ODT<3..0>MEM_CTRL

MEM_CLKMEM_A_CLK MEM_A_CLK_N<5..0>MEM_70D_VDD

MEM_40S_VDDMEM_A_CNTL MEM_CTRL MEM_A_CKE<3..0>

MEM_CLKMEM_A_CLK MEM_A_CLK_P<5..0>MEM_70D_VDD

MEM_40S_VDD MEM_CTRLMEM_B_CNTL MEM_B_CKE<3..0>

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36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1



SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

NET_TYPE

PHYSICAL SPACING

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

Digital Video Signal Constraints

SATA Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

ELECTRICAL_CONSTRAINT_SETPCI-Express

I182

I183

?=4X_DIELECTRICTOP,BOTTOMPCIE

?8 MIL*MCP_PEX_COMP

?=4x_DIELECTRICTOP,BOTTOMDISPLAYPORT

=3X_DIELECTRIC ?*PCIE

?* 20 MILCLK_PCIE

?=4x_DIELECTRICTOP,BOTTOMLVDS

DISPLAYPORT * ?=3x_DIELECTRIC

TOP,BOTTOMSATA ?=3x_DIELECTRIC

LVDS * ?=3x_DIELECTRIC

MCP_DV_COMP =STANDARD=STANDARD=STANDARD20 MIL20 MILY*

LVDS_100D =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF*

DP_100D =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF* =100_OHM_DIFF

SATA_100D * =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

SATA_90D_HDD =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF* =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

*SATA =4x_DIELECTRIC ?

8 MIL ?*SATA_TERMP

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF*CLK_PCIE_100D


MCP Constraints 1SYNC_MASTER=K24_MLB

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF*PCIE_90D

DISPLAYPORTDP_100DTMDS_IG_TXC TMDS_IG_TXC_P

DISPLAYPORTDP_100DDP_ML DP_ML_P<3..0>

DISPLAYPORTDP_100D DP_ML_C_P<3..0>

DP_100D DISPLAYPORT DP_ML_C_N<3..0>

DP_100DTMDS_IG_TXC DISPLAYPORT TMDS_IG_TXC_N

TMDS_IG_TXD_N<2..0>DP_100DTMDS_IG_TXD DISPLAYPORT

DP_IG_AUX_CH_NDP_100D DISPLAYPORT

DP_AUX_CH_C_PDP_100D DISPLAYPORT

DP_AUX_CH_C_NDISPLAYPORTDP_100D

LVDS_IG_A_CLK_F_NLVDS_100D LVDS

LVDS_IG_A_DATA_P<2..0>LVDS_100D LVDSLVDS_IG_A_DATA

LVDS_IG_A_DATA_N<2..0>LVDSLVDS_IG_A_DATA LVDS_100D

MCP_IFPAB_RSETMCP_IFPAB_RSET MCP_DV_COMP

MCP_HDMI_VPROBE MCP_HDMI_VPROBEMCP_DV_COMP

SATA_90D_HDD SATA_HDD_R2D_UF_NSATA

DP_100DTMDS_IG_TXD DISPLAYPORT TMDS_IG_TXD_P<2..0>

MCP_IFPAB_VPROBEMCP_IFPAB_VPROBE

SATA_90D_HDD SATA SATA_HDD_D2R_C_N

SATA_ODD_D2R SATA_100D SATA SATA_ODD_D2R_P

SATA_100D SATA SATA_ODD_D2R_N

SATA_ODD_D2R_UF_PSATA_100D SATA

SATASATA_100D SATA_ODD_D2R_C_N

SATA_ODD_R2D_UF_NSATASATA_100D

SATA_ODD_R2D_UF_PSATASATA_100D

SATA_ODD_R2D_NSATASATA_100D

SATA_90D_HDDSATA_HDD_D2R SATA SATA_HDD_D2R_P

SATA_100D SATA SATA_ODD_D2R_C_P

SATA_ODD_D2R_UF_NSATASATA_100D

MCP_SATA_TERMPSATA_TERMPMCP_SATA_TERMP

LVDS_IG_A_CLK_PLVDS_100D LVDSLVDS_IG_A_CLK

LVDS_IG_A_CLK LVDS_IG_A_CLK_NLVDS_100D LVDS

LVDS_IG_A_CLK_F_PLVDS_100D LVDS

SATA_90D_HDD SATA_HDD_D2R_C_PSATA

SATA_100D SATA_ODD_R2D_C_NSATA

SATA_100D SATA_ODD_R2D_PSATA

SATA_ODD_R2D_C_PSATASATA_100DSATA_ODD_R2D

SATA_90D_HDD SATA_HDD_D2R_UF_NSATA

SATA_90D_HDD SATA_HDD_D2R_UF_PSATA

SATA_90D_HDD SATA SATA_HDD_D2R_N

SATA_90D_HDD SATA_HDD_R2D_UF_PSATA

SATA_90D_HDD SATA_HDD_R2D_C_NSATA

SATA_90D_HDD SATA_HDD_R2D_C_PSATASATA_HDD_R2D

SATA_90D_HDD SATA SATA_HDD_R2D_P

SATA_90D_HDD SATA SATA_HDD_R2D_N

DP_ML DP_ML_N<3..0>DP_100D DISPLAYPORT

DP_IG_AUX_CH_PDP_100D DISPLAYPORTDP_AUX_CH

DISPLAYPORT DP_AUX_CH_SW_PDP_100D

DP_AUX_CH_SW_NDP_100D DISPLAYPORT

MCP_HDMI_RSETMCP_HDMI_RSET MCP_DV_COMP

DP_ML DP_ML_CONN_P<3..0>DP_100D DISPLAYPORT

DP_100D DP_ML_CONN_N<3..0>DISPLAYPORT

PCIEPCIE_90D PCIE_FW_D2R_N

PCIE PCIE_FW_R2D_NPCIE_90D

PCIE_90D PCIE PCIE_MINI_R2D_N

PCIEPCIE_90D PCIE_FW_R2D_C_N

PCIEPCIE_90D PCIE_FW_R2D_P

PCIE_90D PCIEPCIE_MINI_D2R PCIE_MINI_D2R_P

PCIE_90D PCIE PCIE_MINI_D2R_N

PCIE_FW_D2R PCIE PCIE_FW_D2R_PPCIE_90D

PCIE_FW_R2D PCIE PCIE_FW_R2D_C_PPCIE_90D

PCIE_90DPCIE_MINI_R2D PCIE PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_PPCIEPCIE_90D

PCIE_90D PCIE PCIE_MINI_R2D_C_N

MCP_PEX_CLK_COMP MCP_PEX_CLK_COMPMCP_PEX_COMP

PCIE

PCIE_90DCONN_PCIE_MINI_D2R_P

CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FC_N

PCIEPCIE_90D

CONN_PCIE_MINI_D2R_N

PCIEPCIE_90D CONN_PCIE_MINI_R2D_N

PCIEPCIE_90D CONN_PCIE_MINI_R2D_P

MCP_PE4_REFCLK PCIE_CLK100M_FC_PCLK_PCIECLK_PCIE_100D

CLK_PCIECLK_PCIE_100D PCIE_CLK100M_MINI_CONN_N

CLK_PCIE PCIE_CLK100M_MINI_CONN_PCLK_PCIE_100D

CLK_PCIE PCIE_CLK100M_MINI_NCLK_PCIE_100D

CLK_PCIECLK_PCIE_100D PCIE_CLK100M_MINI_PMCP_PE1_REFCLK

PCIE_90D PCIE PCIE_FW_D2R_C_N

PCIE_90D PCIE PCIE_FW_D2R_C_P

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7 34

20 34

20 34

34

7 34

34

34

7 34

20 34

7 34

34

20

18 64

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7 34

20 34

7 34

20 34

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20 34

34

20 34

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36

BRANCH

REVISION

DRAWING NUMBER SIZE

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SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1







SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

PCI Bus Constraints

LPC Bus Constraints


USB 2.0 Interface Constraints



SPACING

NET_TYPE

PHYSICALELECTRICAL_CONSTRAINT_SET

SPI Interface Constraints


SIO Signal Constraints


HD Audio Interface Constraints

SMBus Interface Constraints


=55_OHM_SE=55_OHM_SE =STANDARDCLK_PCI_55S * =55_OHM_SE =STANDARD=55_OHM_SE

=STANDARD* =STANDARD=55_OHM_SE =55_OHM_SE =55_OHM_SEPCI_55S =55_OHM_SE

USB_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF* =90_OHM_DIFF

=STANDARD=STANDARD* =55_OHM_SE =55_OHM_SE =55_OHM_SESPI_55S =55_OHM_SE

USB ?TOP,BOTTOM =4x_DIELECTRIC

=STANDARD*LPC_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD

=2x_DIELECTRIC ?*SMB

=2x_DIELECTRICHDA * ?

?* 8 MILMCP_HDA_COMP

*CLK_SLOW ?8 MIL

* ?PCI =STANDARD

* ?CLK_PCI 8 MIL

* =STANDARD=STANDARDHDA_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

*SPI ?8 MIL

?* 8 MILCLK_LPC

* ?LPC 6 MIL

=STANDARD =STANDARD=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SECLK_LPC_55S *

=STANDARD =STANDARDCLK_SLOW_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE*


MCP Constraints 2

MCP_USB_RBIAS 8 MIL 8 MIL =STANDARD=STANDARD =STANDARD =STANDARD*

=2x_DIELECTRIC* ?USB

=55_OHM_SE* =STANDARD =STANDARDSMB_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE

USBUSB_90D USB_IR_PUSB_IR

USBUSB_90D USB_IR_N

USB_90D USBUSB_EXTB USB_EXTB_P

USB_90D USB USB_CARDREADER_PUSB_SD

USBUSB_90D USB_CARDREADER_N

USB_90D USB CONN_USB_EXTB_N

CONN_USB_EXTB_PUSBUSB_90D

USB_90D USBUSB_TPAD USB_TPAD_P

USBUSB_90D USB_TPAD_N

USB_90D USB USB_TPAD_R_P

USB_90D USB USB_TPAD_R_N

USB_90D USB USB_EXTB_N

HDA HDA_SDIN_CODECHDA_55S

HDA_RST_L HDA_55S HDA HDA_RST_R_L

HDA_55S HDA HDA_BIT_CLK_R

SMB_55S SMB SMBUS_MCP_1_CLKSMBUS_MCP_1_CLK

SMBUS_MCP_0_DATASMBSMBUS_MCP_0_DATA SMB_55S

SMB_55SSMBUS_MCP_0_CLK SMBUS_MCP_0_CLKSMB

MCP_USB_RBIAS MCP_USB_RBIAS_GNDMCP_USB_RBIAS

HDA_55S HDA HDA_SDOUT_R

PM_CLK32K_SUSCLK_RCLK_SLOWCLK_SLOW_55SMCP_SUS_CLK

MCP_HDA_PULLDN_COMP MCP_HDA_PULLDN_COMPMCP_HDA_COMP

SMB_55S SMB SMBUS_MCP_1_DATASMBUS_MCP_1_DATA

USBUSB_90D USB_EXTA_MUXED_N

USBUSB_90D CONN_USB_EXTA_P

USBUSB_90D CONN_USB_EXTA_N

USB_90D USB_EXTA_NUSB

USBUSB_90D USB_EXTA_MUXED_P

PCIPCI_55SPCI_GNT0_L PCI_GNT0_L

PCI_REQ1_L PCI_REQ1_LPCIPCI_55S

PCIPCI_GNT1_L PCI_GNT1_LPCI_55S

PCI_INTW_L PCI PCI_INTW_LPCI_55S

PCI_INTZ_L PCIPCI_55S PCI_INTZ_L

LPC_55SLPC_AD LPC LPC_AD<3..0>

LPC_55S LPCLPC_FRAME_L LPC_FRAME_L

LPC_55SLPC_RESET_L LPC LPC_RESET_L

LPC_CLK33M_SMCCLK_LPCCLK_LPC_55S

MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC_R

USB_EXTA_PUSB_90D USBUSB_EXTA

PCI PCI_FRAME_LPCI_55SPCI_CNTL

PCI_REQ0_L PCI PCI_REQ0_LPCI_55S

PCI_AD PCI_AD<31..25>PCIPCI_55S

PCI_CNTL PCIPCI_55S PCI_DEVSEL_L

PCI_AD<23..8>PCI_AD PCIPCI_55S

MCP_DEBUG<7..0>MCP_DEBUG PCIPCI_55S

LPC_CLK33M_LPCPLUSCLK_LPCCLK_LPC_55S

MCP_PCI_CLK2 CLK_PCICLK_PCI_55S PCI_CLK33M_MCP_R

CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP

PCI_55S PCI_INTY_LPCI_INTY_L PCI

PCIPCI_55SPCI_INTX_L PCI_INTX_L

PCI_CNTL PCIPCI_55S PCI_TRDY_L

PCI_CNTL PCI PCI_SERR_LPCI_55S

PCIPCI_CNTL PCI_55S PCI_STOP_L

PCI_CNTL PCI PCI_PERR_LPCI_55S

PCI_CNTL PCI PCI_IRDY_LPCI_55S

PCIPCI_AD PCI_PARPCI_55S

PCI PCI_C_BE_L<3..0>PCI_55SPCI_C_BE_L

PCI_AD24 PCI PCI_AD<24>PCI_55S

PM_CLK32K_SUSCLKCLK_SLOW_55S CLK_SLOW

HDA_55S HDAHDA_SDIN0 HDA_SDIN0

HDA_55S HDA HDA_RST_L

HDA_55S HDAHDA_BIT_CLK HDA_BIT_CLK

SPISPI_55S SPI_ALT_CLK

SPI_55SSPI_CLK SPI SPI_CLK_R

HDA_55SHDA_SDOUT HDA HDA_SDOUT

SPI_55S SPI_CLKSPI

HDA_55SHDA_SYNC HDA HDA_SYNC

HDA_55S HDA HDA_SYNC_R

SPISPI_55SSPI_CS0 SPI_CS0_R_L

SPI_55SSPI_MISO SPI SPI_MISO

SPI_MOSISPISPI_55S

SPI_MISO_RSPI_55S SPI

SPISPI_55S SPI_CS0_L

SPI_55S SPI SPI_CS1_R_L_USE_MLB

SPI_55S SPI SPI_CS1_R_L

SPISPI_55S SPI_ALT_MISO

SPI SPI_ALT_MOSISPI_55S

SPI_MOSI_RSPI_MOSI SPISPI_55S

USB_CAMERA_CONN_PUSBUSB_90D

USB_90DUSB_CAMERA USB_CAMERA_PUSB

USB_BT USB_BT_PUSBUSB_90D

USBUSB_90D USB_BT_N

USB_90D USB USB_CAMERA_CONN_N

USB_90D USB_CAMERA_NUSB

USB_90D USB CONN_USB2_BT_N

CONN_USB2_BT_PUSB_90D USB

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20 35

21

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21 39

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13 21 39

20

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21 25

21

21 39

35

35

35

20 35

35

19

19 36 38

19 36 38

19 25

25 36

19 25

20 35

19

13 19

25 38

19

19

25 36

21 49

21 49

21 49

38

21 38 48

21 49

48

21 49

21

21 38

21 38 48

48

48

38

38

21 38 48

7 64

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20 30

20 30

7 64

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7 30

7 30







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88E1116R (Ethernet PHY) Constraints

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4


ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE

MCP RGMII (Ethernet) Constraints

SPACING

ENET_MDI_100D =100_OHM_DIFF* =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF


Ethernet Constraints

=STANDARD7.5 MIL =STANDARD =STANDARD7.5 MIL=STANDARD*MCP_MII_COMP

=3:1_SPACING* ?MCP_BUF0_CLK

?*ENET_MII 12 MIL

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SEENET_MII_55S =STANDARD =STANDARD*

25 MIL ?*ENET_MDI

ENET_RXCTL_RENET_MIIENET_MII_55S

ENET_RXD ENET_RX_CTRLENET_MII_55S ENET_MII

ENET_MDIENET_MDI_100D ENET_MDI_TRAN_N<3..0>

ENET_MDI_100D ENET_MDI ENET_MDI_TRAN_P<3..0>

ENET_MDI ENET_MDI_P<3..0>ENET_MDI_100DENET_MDI

ENET_MDI ENET_MDI_N<3..0>ENET_MDI_100D

ENET_RESET_LENET_MII_55S ENET_MII

ENET_TXD ENET_TX_CTRLENET_MIIENET_MII_55S

ENET_TXD0 ENET_MIIENET_MII_55S ENET_TXD<0>

ENET_TXD ENET_MII_55S ENET_MII ENET_TXD<3..1>

ENET_TXCLK ENET_MIIENET_MII_55S ENET_CLK125M_TXCLK

ENET_CLK125M_TXCLK_RENET_MIIENET_MII_55S

MCP_MII_COMPMCP_MII_COMP MCP_MII_COMP_GND

ENET_INTR_L ENET_MII_55S ENET_INTR_LENET_MII

ENET_MIIENET_MII_55S ENET_CLK125M_RXCLK_R

ENET_RXD ENET_RXD<0>ENET_MII_55S ENET_MII

ENET_PWRDWN_L ENET_MII_55S ENET_MII ENET_PWRDWN_L

ENET_MDCENET_MDC ENET_MIIENET_MII_55S

ENET_MII_55S ENET_MIIENET_MDIO ENET_MDIO

RTL8211_CLK25M_CKXTAL1MCP_BUF0_CLKENET_MII_55S

MCP_CLK25M_BUF0_RENET_MII_55SMCP_CLK25M_BUF0 MCP_BUF0_CLK

ENET_RXD_STRAP ENET_RXD<3..1>ENET_MII_55S ENET_MII

ENET_CLK125M_RXCLKENET_MII_55S ENET_MIIENET_RXCLK

ENET_RXD_R<3..0>ENET_MII_55S ENET_MII

MCP_MII_COMP MCP_MII_COMP_VDDMCP_MII_COMP

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18




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SMBus Charger Net Properties


NET_TYPE

PHYSICAL SPACING

SMC SMBus Net Properties

SPACINGPHYSICAL

NET_TYPE


SMC ConstraintsSYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009

=STANDARD =STANDARD 0.1 MM 0.1 MM* =STANDARD=STANDARD1TO1_DIFFPAIR

CHGR_CSO_N1TO1_DIFFPAIR

CHGR_CSO_P1TO1_DIFFPAIRCHGR_CSO

CHGR_CSI_P1TO1_DIFFPAIRCHGR_CSI

CHGR_CSI_N1TO1_DIFFPAIR

SMB_55S SMBUS_SMC_A_S3_SCLSMBUS_SMC_A_S3_SCL SMB

SMB_55S SMBUS_SMC_A_S3_SDASMBUS_SMC_A_S3_SDA SMB

SMBUS_SMC_BSA_SDASMBUS_SMC_BSA_SDA SMBSMB_55S

SMBSMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SDASMB_55S

SMB SMBUS_SMC_MGMT_SCLSMB_55SSMBUS_SMC_MGMT_SCL

SMBSMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCLSMB_55S

SMBUS_SMC_0_S0_SDASMBUS_SMC_0_S0_SDA SMBSMB_55S

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCLSMBSMB_55S

SMBSMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SDASMB_55S

SMBSMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SCLSMB_55S

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K84 SENSOR NET PROPERTIES


NET_TYPE

PHYSICAL SPACING


K84 SPECIAL CONSTRAINTSSYNC_MASTER=K24_MLB

=STANDARD =STANDARD* 0.1 MM=STANDARD=STANDARDDIFFPAIR 0.1 MM

ISNS_CPUVTT_PDIFFPAIR

DIFFPAIR ISNS_HDD_R_P

MCPTHMSNS_D2_PDIFFPAIR

DIFFPAIR MCP_THMDIODE_P

MCP_THMDIODE_NDIFFPAIR

DIFFPAIR ISNS_ODD_R_P

DIFFPAIR ISNS_ODD_R_N

DIFFPAIR ISNS_AIRPORT_R_P

DIFFPAIR ISNS_1V5_S3_N

DIFFPAIR ISNS_1V5_S3_R_P

DIFFPAIR ISNS_AIRPORT_R_N

DIFFPAIR CPU_THERMD_N

ISNS_CPUVTT_NDIFFPAIR

DIFFPAIR ISNS_HDD_P

DIFFPAIR MCPTHMSNS_D2_N

DIFFPAIR ISNS_HDD_R_N

DIFFPAIR ISNS_ODD_P

DIFFPAIR ISNS_ODD_N

DIFFPAIR ISNS_AIRPORT_N

DIFFPAIR ISNS_1V5_S3_P

DIFFPAIR ISNS_LCDBKLT_N

DIFFPAIR ISNS_LCDBKLT_P

ISNS_HDD_NDIFFPAIR

DIFFPAIR ISNS_1V5_S3_R_N

DIFFPAIR ISNS_AIRPORT_P

DIFFPAIR CPU_THERMD_P

CPUTHMSNS_D2_NDIFFPAIR

CHGR_CSO_R_PDIFFPAIR

DIFFPAIR CHGR_CSO_R_N

DIFFPAIR CPUTHMSNS_D2_P

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TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS


































PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM














































K84 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS


K84 RULE DEFINITIONSSYNC_MASTER=K24_MLB

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA_P1MM MM 15.5.1

30 MM0.100MMDEFAULT =50_OHM_SE* Y 0 MM 0 MM

*STANDARD =DEFAULT =DEFAULT=DEFAULT =DEFAULT12.7 MMY

0.090 MM55_OHM_SE YTOP,BOTTOM 0.090 MM

100_OHM_DIFF =STANDARD* =STANDARD =STANDARDN =STANDARD =STANDARD

100_OHM_DIFF TOP,BOTTOM 0.091 MM 0.230 MM 0.230 MM0.091 MMY

100_OHM_DIFF 0.075 MM 0.075 MM 0.244 MM0.244 MMYISL3,ISL4,ISL9,ISL10

=STANDARDN*100_OHM_DIFF_HDD =STANDARD =STANDARD =STANDARD=STANDARD

0.400 MM0.095 MM0.095 MMTOP,BOTTOM100_OHM_DIFF_HDD Y 0.400 MM

TOP,BOTTOM Y90_OHM_DIFF 0.220 MM 0.220 MM0.112 MM0.112 MM

ISL3,ISL4,ISL9,ISL1090_OHM_DIFF Y 0.095 MM 0.095 MM 0.234 MM 0.234 MM

* =STANDARD=STANDARD90_OHM_DIFF =STANDARD=STANDARD =STANDARDN

0.100 MMTOP,BOTTOM70_OHM_DIFF Y 0.185 MM 0.200 MM0.200 MM

=STANDARD70_OHM_DIFF =STANDARD=STANDARD* N =STANDARD=STANDARD

0.100 MMISL3,ISL4,ISL9,ISL1070_OHM_DIFF Y 0.151 MM 0.224 MM 0.224 MM=STANDARD

50_OHM_SE * =STANDARD =STANDARDY =STANDARD0.076 MM0.076 MM

STANDARDBGA_P1MMMEM_40S_VDD

BGA_P1MM STANDARDMEM_40S

* BGA_P2MMBGA_P1MMMEM_CLK

* * BGA_P1MM BGA_P1MM

BGA_P2MM*CLK_FSB BGA_P1MM

CLK_LPC BGA_P2MM* BGA_P1MM

BGA_P1MM BGA_P2MM*CLK_PCI

BGA_P1MMFSB_DSTB BGA_P3MMFSB_DSTB

BGA_P1MMCLK_SLOW * BGA_P2MM

BGA_P2MMBGA_P1MM*CLK_PCIE

BGA_P1MM ?* =DEFAULT

STANDARD * ?=DEFAULT

* 0.1 MM ?DEFAULT

=DEFAULTBGA_P2MM * ?

* =DEFAULT ?BGA_P3MM

0.25 MM ?2.5:1_SPACING *

2:1_SPACING 0.2 MM* ?

1.5:1_SPACING * 0.15 MM ?

* 0.3 MM ?3:1_SPACING

?* 0.4 MM4:1_SPACING

0.140 MMTOP,BOTTOM ?2X_DIELECTRIC

2X_DIELECTRIC * ?0.126 MM

3X_DIELECTRIC ?* 0.189 MM



110_OHM_DIFF TOP,BOTTOM Y 0.330 MM 0.330 MM0.077 MM0.077 MM

1:1_DIFFPAIR * =STANDARD 0.1 MM0.1 MM=STANDARD=STANDARDY

110_OHM_DIFF YISL3,ISL4,ISL9,ISL10 0.330 MM 0.330 MM0.075 MM0.075 MM

=STANDARD27P4_OHM_SE * Y =STANDARD =STANDARD0.222 MM 0.222 MM

0.350 MMTOP,BOTTOM ?5X_DIELECTRIC

0.210 MM ?3X_DIELECTRIC TOP,BOTTOM

0.280 MM4X_DIELECTRIC ?TOP,BOTTOM

110_OHM_DIFF =STANDARD* =STANDARD=STANDARDN =STANDARD =STANDARD

0.400 MM0.400 MMISL3,ISL4,ISL9,ISL10100_OHM_DIFF_HDD Y 0.083 MM 0.083 MM

* 0.076 MM55_OHM_SE =STANDARD =STANDARD=STANDARDY 0.076 MM

0.100 MM =STANDARD =STANDARD*40_OHM_SE Y =STANDARD0.126 MM

0.165 MMTOP,BOTTOM40_OHM_SE Y 0.100 MM

TOP,BOTTOM 0.115 MMY 0.115 MM50_OHM_SE

TOP,BOTTOM 0.310 MM27P4_OHM_SE Y 0.310 MM

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