74370936 NanoRoute Recommendations

COPYRIGHT © 2011, CADENCE DESIGN SYSTEMS, INC ALL RIGHTS RESERVED. PAGE 1

Cadence Design Systems, Inc.

Application Note

NanoRoute Recommended Options with emphasis on 32nm and below advance node/technology (EDI)

Revision: 1.0 May 2011


Recommended NanoRoute Options with emphasis on 32nm and below advance node/technology (EDI)

Introduction

This NanoRoute application note discusses the following topics:

• Unnecessary NanoRoute options which are no longer needed for routing using NanoRoute

• New option to improve routability for designs using technologies 32nm and smaller

• Post Route double cut insertion • New routing strategies for double cut insertion • Recommended NanoRoute scripts for increased double-cut vias

insertion • Recommended NanoRoute scripts for increased double-cut vias

insertion targeting TSMC and IBM technologies 28nm and smaller • NanoRoute debugging options

The goal being to improve overall QoR, ease of use and runtime.


Unnecessary NanoRoute options which are no longer needed for routing using NanoRoute

The following list of options is no longer needed when using NanoRoute to route designs.

The reasons being some of these options are too conservative and hence are not recommended, while in some cases NanoRoute has been enhanced to automatically use these options where needed and hence does not have to be explicitly specified by user.

• routeWithViaInPin

This forces the ‘via connection to pin’ to be buried inside the pin. This is too conservative and hence not recommended

• routeWithViaInPinForStandardCellPin

This forces the connection to standard cell pin with via, forbidding planar connection. This is too conservative and hence not recommended

The following options below are no longer needed as NR has been enhanced to automatically use them when needed

• routeSiEffort

• routeTdrEffort

• routeTdrPreferLayerPercentage

• drouteAllowExtraAccess

• routeAutoPinAccess

• drouteAllowMergedWireAtPin

• routeSiLengthLimit


New option to improve routability for designs using technologies 32nm and below

For 32nm designs and below, the following option should be used to improve QoR and runtime.

setNanoRouteMode -routeAutoTuneOptionsForAdvancedDesign true

Setting this option results in the following:

• via reduction during routing

• Improves wire and via connection by aligning the wire with the via

• Improves stack-ability with more accurate MAR calculation

• Triggers advanced algorithm to handle dense pin configuration

• Triggers algorithm to resolve difficult context based rules, such as EOL with parallelwithin, opposite EOL

Post Route double cut insertion

To increase percentage of double cut vias post route, the recommendation flow is:

• Set option "routeWithTimingDriven" to false; as setting it to true prevents NR to replace single cut via to double cut via on critical nets, including clock nets

• Set option "droutePostRouteSwapVia" to multiCut to turn on double cut via insertion

• Run routeDesign -viaOpt


New routing strategies for double cut insertion

Described below are some double cut via insertion strategies to get good, better or best ratios of double-cut vias.

• Good double cut ratio

The following strategy should result in good double cut ratio:

Reserve space for Via Insert double cut vias during post Route

• Better double cut ratio

The following strategy should result in better double cut ratio as compared to the flow above:

Concurrent double cut via insertion with Medium effort Reserve space for Via (optional) Insert double cut vias post Route (optional)

• Best double cut ratio

The following strategy should give the best double cut ratio:

Concurrent double cut via insertion with high effort Reserve space for Via (optional) Insert double cut vias post Route (optional)


Recommended NanoRoute scripts for increased double-cut vias insertion for 45nm and above


setNanoRouteMode -routeReserveSpaceForMultiCut true routeDesign setNanoRouteMode -routeWithTimingDriven false setNanoRouteMode -droutePostRouteSwapVia multiCut routeDesign -viaOpt

• Better double cut ratio (optional steps are preceded with #)

setNanoRouteMode -routeUseMultiCutViaEffort medium #setNanoRouteMode -routeReserveSpaceForMultiCut true routeDesign #setNanoRouteMode -routeWithTimingDriven false #setNanoRouteMode -droutePostRouteSwapVia multiCut #routeDesign -viaOpt

• Best double cut ratio (optional steps are preceded with #)

setNanoRouteMode -routeUseMultiCutViaEffort high #setNanoRouteMode -routeReserveSpaceForMultiCut true routeDesign #setNanoRouteMode -routeWithTimingDriven false #setNanoRouteMode -droutePostRouteSwapVia multiCut #routeDesign -viaOpt


Recommended Nano Route scripts for increased double-cut vias insertion for 32nm and below


setNanoRouteMode -routeReserveSpaceForMultiCut true setNanoRouteMode -routeAutoTuneOptionsForAdvancedDesign true routeDesign setNanoRouteMode -routeWithTimingDriven false setNanoRouteMode -droutePostRouteSwapVia multiCut routeDesign -viaOpt

• Better double cut ratio (optional steps are preceded with #)

setNanoRouteMode -routeUseMultiCutViaEffort medium #setNanoRouteMode -routeReserveSpaceForMultiCut true setNanoRouteMode -routeAutoTuneOptionsForAdvancedDesign true routeDesign #setNanoRouteMode -routeWithTimingDriven false #setNanoRouteMode -droutePostRouteSwapVia multiCut #routeDesign -viaOpt

• Best double cut ratio (optional steps are preceded with #)

setNanoRouteMode -routeUseMultiCutViaEffort high #setNanoRouteMode -routeReserveSpaceForMultiCut true setNanoRouteMode -routeAutoTuneOptionsForAdvancedDesign true routeDesign #setNanoRouteMode -routeWithTimingDriven false #setNanoRouteMode -droutePostRouteSwapVia multiCut #routeDesign -viaOpt


Recommended NanoRoute scripts for increased double-cut vias insertion targeting TSMC and IBM technologies 28nm and below

• For TSMC 28nm and smaller (optional steps are preceded with #)

TSMC requires DFM vias i.e. which have a larger enclosure, and the order of DFM vias is predefined

setNanoRouteMode -dbViaWeight "FBD -1, FBS -1, PBD -1, PBS -1" #setNanoRouteMode -routeConcurrentMinimizeViaCountEffort high setNanoRouteMode -routeReserveSpaceForMultiCut true setNanoRouteMode -routeAutoTuneOptionsForAdvancedDesign true routeDesign

setNanoRouteMode -dbViaWeight "FBD 8, FBS 7, PBD 6, PBS 5, 2cut_p1 4, 2cut_p2 3, 2cut_p3 2, FAT 1" setNanoRouteMode -routeWithTimingDriven false setNanoRouteMode -droutePostRouteSwapVia multiCut routeDesign -viaOpt

• For IBM 28nm and smaller (optional steps are preceded with #)

setNanoRouteMode -routeReserveSpaceForMultiCut true setNanoRouteMode -routeAutoTuneOptionsForAdvancedDesign true routeDesign

setNanoRouteMode -routeWithTimingDriven false setNanoRouteMode -droutePostRouteSwapVia multiCut routeDesign -viaOpt

Note: Based on customer process requirements, you might need to set the following:

setNanoRouteMode -routeWithViaInPin 1:1 setNanoRouteMode -routeWithViaInPinForStandardCellPin 1:1


NanoRoute debugging options

To get more details on NR violations set the following option to print categorized violations:

setNanoRouteMode -drouteVerboseViolationSummary 1

Example:

By layer and Type:

H/V Via MAR EOL ENC Totals M1 0 895 0 1 75 971 M2 1702 1054 0 513 4158 7427 M3 31392 1683 38 507 15690 49310 M4 55915 1383 644 1227 2001 61170 M5 28366 0 0 51 0 28417 Totals 117375 5015 682 2299 21924 147295

74370936 NanoRoute Recommendations

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