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Data Acquisition and Analog-digital Conversion

Computer Science & Engineering DepartmentArizona State University

Tempe, AZ 85287

Dr. Yann-Hang Leeyhlee@asu.edu

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Data Acquisition

Data acquisition (DAQ) refers to the process of capturing data from a real-world physical system (Eg. Transducers) and presenting the data in a form that is readily available to a digital processing system.

Acronyms: ADC Analog to Digital ConverterDAC Digital to Analog Converter

Topics Covered: - Architecture of a typical DAQ System. Range, Resolution, Conversion Rate, Data Transfer,

Differential Non-Linearity etc. Circuits: ADC (Dual-Slope Integrating, Successive

Approximation, Flash (Parallel)) and DAC (R-2R Ladder).

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Architecture of a typical DAQ System

Transducer: Converts non-electric input signals into proportionate analog electrical signals.

Actuator: Converts electrical signals to proportionate physical quantities.

ADC

DAC

Real World. Eg., Force,Velocity, Light etc.

Analog Output

Analog Input

Analog Voltage/Current

Digital Voltage/Current

Transducer

Actuator

DAQ Hardware

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Architecture of a typical DAQ System

ADC is used to convert analog electrical signals to proportional digital values. This digital data can then be processed, recorded and visualized in a digital computer.

DAC is used to convert a value represented in digital code by the computer, to a proportionate analog voltage/current signal. This signal can then be used to control a real-world device through an actuator.

Example: Cruise control of an automobile. Speedometer interfaced to a Transducer DAQ Microcontroller.

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Key Terminologies: ADC

Full-Scale Voltage Range: The difference between the maximum voltage and minimum voltage that the ADC is converting.

Resolution: The number of bits the ADC uses to represent the digital data determines the resolution. Example: A 3-bit ADC. For a full-scale voltage of 10 volts, the

resolution will be 10/(23)=1.25volts.

Differential sensing: In the regular single sensing mode, the ADC samples the difference

between the applied signal and ground pin. In differential mode, the input signal is applied between a signal line

and its own special reference, the signal return path is through this reference signal and not the regular ground pin.

Differential mode is used when noise on input line is high, or the voltages are extremely low (< 1 volt).

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Key Terminologies: ADC (Resolution)

However, if we increase the number of bits to 12, then resolution becomes 10/(212)=2.44 mV.

Volts Volts

Sampling

Time Time

Digital Output

4/8 8/8FS

LSB

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Key Terminologies: ADC (Sample Rate)

Sampling Rate or Conversion Rate: Data is acquired by the ADC by using a process called sampling.

Instantaneous values from the analog signal are sampled at discrete time intervals. The rate at which signals are sampled is called the sampling frequency.

Higher the rate of sampling, better is the quality of conversion. The minimum sampling frequency must be at least twice the maximum frequency of the input analog signal (Nyquist Rate). Sampling at a lower rate will lead to aliasing.

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Key Terminologies: ADC (Sample Rate)

Time

Voltage

Red wave: Original Signal (34.1 KHz) Black wave: Undersampled waveform (Fs=10KHz)

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How fast should ADC be? Examples

ApplicationsNo. of Conversions per

second (Approx.)

Monitor and Control 1-1000

Telephone Voice 8000

CD-Quality Audio 85, 42.5, 21.3 Kilo

Video 2*10^6

Radar 100…1000*(10^6)

Large rate of collecting data by the DAQ can result in a transfer bottleneck because of the limited memory bandwidth and the lack of processor availability for such data transfers

DMA bus master transfers data directly to RAM without any need for processor intervention.

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ADC Hardware

ADC architectures can be divided into three categories as shown below: -

Integrating, Successive Approximation and Flash architectures are the most popular.

Low Speed, High Accuracy

Medium Speed, Medium Accuracy

High speed, Low-to-medium Accuracy

Integrating

Oversampling

Successive Approximation, Algorithmic

Flash, Two-step, Interpolating, Folding, Pipelined, Time-interleaved

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Dual-Slope Integrating ADC- Operation

ControlLogic Counter

Comparator

C1

R1S1

S2

Vx

Clockfclk

-Vin

-Vref.......

b0

b1

b2

bN

Phase I: C1 is charged with S1 connected to –Vin with charging duration equal to T1=(2N)/fclk.

At the end of Phase I,

11

1

011

11

CR

TVdt

CR

)V()T(V inT in

x

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Dual-Slope Integrating ADC - Operation

Phase II : At the start, the counter is reset and S1 is connected to Vref. C1 discharges in time T2, proportional to the value it was charged in Phase I. Counter counts until Vx is less than zero. This count value is the digitized value of Vin.

The counter output is proportional to Vin, all other quantities in the above equation are constant.

Merits and Demerits: - 100 microseconds (slow), Very Accurate, Low Cost, Long life.

)V

V(TT )TT(V

)T(VdtCR

V)TT(V

ref

inx

x

TT

T

refx

1221

111

21

0

21

1

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Successive Approximation-Operation

Follows the concept of Binary Search Algorithm. Begins by comparing analog input with midpoint voltage, i.e.,

SAR sets MSB to 1. If analog input is greater, MSB remains unchanged and in the next cycle, the SAR sets the next bit in line and the cycle repeats until all the bits are covered.

N-Bit SuccessiveApproximationRegister (SAR)

ControlLogic

LATCH

Vref

Microcontroller

Start Conversion

End Conversion

DigitalControlLines

Dig

ital

outp

ut to

Mic

roco

ntr

olle

r

Analog Input

D/AConverter

Op-AmpComparator

.

.

.

.

.

.

.

b0

b1

b2

bN

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Successive Approximation - Example

A simple example:

Step 1> Step 2> Step 3>

Final Value: Merits and Demerits: -

Good combination of simple circuit and reasonable conversion time.

1-10 microseconds.

0 0 0

D/A Value Analog Value

(4*0.625v)=2.5 V 1.7 V

(2*0.625v)=1.25 V 1.7 V

(3*0.625v)=1.875 V 1.7 V

1 0 0

0 1 00 1 0

0 1 1 0 1 0

0 1 0

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Flash (Parallel) ADC - Circuit

(2^N -1) toN Encoder

N digitaloutputs

Vref

Vin

R

R

R

R

R/2Comparators

R/2

R

R

R

Vr7

Vr6

Vr1

Vr2

Vr3

Vr4

Vr5

OverRange

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Flash (Parallel) ADC - Operation

Input signal is fed to all the comparators. The other input is connected to different nodes of a resistor string.

When Vri is larger than Vin, a “one” is output.

The only NAND gate that will have low output is the one having one at both inputs. This happens when there is a transition from one to zero at the comparator outputs. All other NAND-gate outputs will be one. This makes it easy for the encoder.

Merits and Demerits: - Extremely fast, 4-50 ns. Occupies large chip area, exponential order of complexity.

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DAC Circuit - R-2R Ladder

When the above ladder circuit is analyzed, we can see that the resistance “as seen” at the arrows shown, is always 2R irrespective of the number of stages.

This gives the current relationships shown. Thus, the ladder circuit can be used to obtain binary

weighted currents.

R R R 2R

2R 2R 2R 2R

Vref

2R 2R2R 2R

V ref / 2R V ref / 16RV ref / 8RVref / 4R

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DAC: R-2R Ladder Circuit

The ladder circuit connected to an Op-amp to perform D/A conversion.

The switches are controlled by the digital value. The switch positions are shown when bit equals one.

R R R 2RVref

2R 2R 2R2R

Rf

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R-2R Ladder Circuit - Operation

When the bit is high, (MSB on extreme left), the current through the branch will pass through to resistor Rf, if bit is low, the current flows to ground.

Therefore, only when the bit is high a binary weighted current will flow through Rf. The output voltage is equal to the drop across Rf. Hence, a voltage proportional to the digital value will appear at the output.

Merits: - Only two resistor values required. Fully modular, stages can be added or deleted easily.

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ADC in MCF5211

Two separate and complete ADCs of 12-bit resolution Internal multiplex to select two of 8 inputs Single conversion time of 8.5 ADC clock cycles, additional conversion

time of 6 ADC clock cycles Maximum ADC clock frequency of 5.0 MHz, 200ns period

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Single Ended or Differential

Single ended upper switch is closed and bottom switch select Vref

Differential upper switch is open and bottom switch selects V- differential pairs: AN0-1, AN2-3, AN4-5, and AN6-7

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Operation Mode of ADC

Conversion process is either initiated by a sync signal from one of two input pins (SYNCx) or by writing 1 to a STARTn bit.

Operation modes: a single scan and halt a scan whenever triggered scan sequence repeatedly until manually stopped.

an ordered list of the analog input channels defined in ADLST1/2 sequential (8 channels) or parallel (AN0-AN3 and AN4-AN7)

12-bit samples + offset result registers (ADRSLT0-7) Conversion clock for sampling

the IPBus clock (system clock) and the clock divisor bits within the CTRL2 should be between 100 kHz and 5.0 MHz.

Reference voltages VREFH and VREFL: all analog inputs are

measured against.

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ADC and Resistive Screen Touch Panel

Resistive touch screens embed a thin glass substrate between two layers of a plastic overlay

The surface of the glass substrate has a tin oxide coating onto which a slight electrical current is constantly applied

When pressure is applied to the outside of the overlay, the two surfaces touch and a ground occurs

The x- and y-coordinates of the ground (touched area) are detected and registered with the control device

Cheap and popular Scratches and long time wear

& tear, makes it inaccurate

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Touch Panel Controller: TI ADS7843

SPI interface receive command and respond samples

Pen-down interrupt and 2 addition analog inputs

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Touch Panel Controller: TI ADS7843

Successive Approximation Register (SAR) ADC Analog inputs to the converter are provided via a

four-channel multiplexer

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Touch Panel Controller: TI ADS7843

Configuration of switches to measure Y position X+ +IN, Y+ +Vcc, Y- -IN and GND