70572-AN601-Unclamped Inductive Switching Rugged MOSFETs for Rugged Environments

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Document Number: 7057215-Feb-94

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Unclamped Inductive Switching Rugged MOSFETsFor Rugged Environments

The evolution of the power MOSFET has resulted in a veryrugged transistor. The semiconductor industry defines thisruggedness as the capability to withstand avalanche currentswhen subjected to unclamped inductive switching. Historically,MOSFET manufacturers chose to quantify ruggedness, notbased principally on individual performance, but rather oncomparative performance with other manufacturers. Siliconixhas optimized the cell structure of power MOSFETs, resulting

in a new class of extremely rugged devices. Todaysavalanche-rated MOSPOWER FET exhibits a ruggednessthat far exceeds the performance of any power MOSFET ofearlier years.

This application note reviews the history of unclampedinductive switching (UIS) and examines various theoriespertaining to failure. It further identifies what appears to be tworelated mechanisms thermal and bipolar believed to beresponsible for failure during unclamped inductive switchingand concludes by recommending how a power MOSFET

should be qualified for ruggedness in the data sheet.

Two failure modes exist when MOSFETs are subjected to UIS.In this article, these failure mechanisms are labelled as eitheractiveor passive. The first, or active mode, results when theavalanche current forces the parasitic bipolar transistor intoconduction. The second, or passive mode, results when theinstantaneous chip temperature reaches a critical value.[1]Atthis elevated temperature, a mesoplasma* forms within theparasitic npn bipolar transistor and causes catastrophicthermal runaway. In either case, the MOSFET is destroyed.

The passive mechanism is, therefore, identified as that failuremode not directly attributed to avalanche currents.

Symbols and Definitions

Whenever possible, symbols and definitions established bythe JEDEC Committee, JC-25, are used in this article. To clearup any discrepancies, however, the following list describessymbols used frequently in this article.

IO the peak current reached during avalanche

tAV the time duration of the avalanche phenomenon

L the value of inductance

V(BR)eff the breakdown voltage in avalanche

What is Unclamped Inductive Switching?

Whenever current through an inductance is quickly turned off,the magnetic field induces a counter electromagnetic force(EMF) that can build up surprisingly high potentials across theswitch. Mechanical switches often have spark-suppressioncircuits to reduce these harmful effects that result when currentis suddenly interrupted. However, when transistors are used

as the switches, the full buildup of this induced potential mayfar exceed the rated breakdown (V(BR)DSS) of the transistor,thus resulting in catastrophic failure.

If we know the size of the inductor, the amount of current beingswitched, and the speed of the switch, the expected potentialmay be easily calculated as

V = L di/dt + VDD (1)

where

L = the inductance (H)

di/dt = rate of change of current (A/s)

VDD = the supply voltage (V)

*A mesoplasma, according to Ghandhi, takes the form of a glowing red spot having an average temperature in excess of 650_C and a peak

core temperature in excess of 1000_C. This mesoplasma is a result of regenerative thermal runaway.


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L

I

+

VDD

D.U.T.

FIGURE 1. UIS Test Circuit

V(BR)eff

V(BR)DSS

IO

VDD

tav

0

FIGURE 2. UIS Waveform during Switching

The classic UIS test circuit in widespread use* is shown inFigure 1. Using this circuit, the energy absorbed by the powerMOSFET may be calculated using

(2)E + 12 lo2L V(BR) effV(BR) eff VDD

An alternate circuit removes VDD (i.e., VDD= 0) just prior toswitching the device off, thus eliminating the last term inequation (2).

Reviewing the switching waveform shown in Figure 2, thegate remains on long enough to ramp the current to IO, at whichtime the gate switches off, resulting in an abrupt break in thedrain current. Since the magnetic field of the inductor cannotinstantaneously collapse, a voltage is induced on the drain ofthe MOSFET in accordance with equation (1). This inducedpotential may easily exceed the (avalanche) breakdownvoltage shown on the data sheet.** During avalanche, thevoltage is clamped at a value of V(BR)eff, and the current storedin the inductor decays linearly from IO to zero. This decay timemay be determined by rearranging equation (1).

(3)tAV +L lo

V(BR) eff

Theories Pertaining to Stress Failures

The Bipolar Excitation Effect The Active Mode. Theclassic reason for failure when a MOSFET is stressed focuseson the activation and subsequent secondary breakdown of theparasitic bipolar transistor. The intrinsic diode of a DMOS FETis actually the collector-base junction of this parasitictransistor. Whether the stress is a form of dv/dt[2,3] or UIS,current cascading laterally through the p+ region is consideredresponsible for transistor failure when the voltage drop,IORp+,activates this bipolar transistor.[4,5,6] The accepted modelrepresenting this failure mode in the vertical MOSFETstructure is offered in Figure 3.

The initial avalanche current at breakdown is heavilyconcentrated within the MOSFETs inherent Zener diode(afforded by the deep p+ well situated centrally in each cell, asshown in Figure 3). However, as the avalanche currentcontinues to increase, it also spreads across the p/n barrier.The lateral resistance (Rp) is much greater than the verticalresistance (RB) of the heavily-doped p

+ region. Avalanchecurrent concentrated in the p+ (Zener) region does notnormally initiate bipolar action. As the avalanche currentincreases in intensity, it spreads along the p/n barrier, and thescenario follows the classic reasoning. If the avalanchecurrents cascading laterally through the p-doped region(pseudobase region) develop sufficient forward bias across Rp

to offset VBE, the normal forward base current, +IB, inconjunction with the beta of the parasitic npn bipolar transistor,will result in a local breakdown voltage equal to BVCEO (whichis approximately half of V(BR)DSS). The resulting mesoplasmacauses thermal runaway and the destruction of the powerMOSFET.

*Recommended by JEDEC Committee JC25.

**Avalanche breakdown, V(BR)DSS, offered in the typical data sheet is generally rated at the zero gate voltage drain current (IDSS) of the MOSFET.

Avalanche breakdown during UIS (V(BR)eff) is, as shown in Figure 2, at substantially higher drain currents. V(BR)eff is much greater than

V(BR)DSS.


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DRAIN

GATE

SOURCE

Rb

DRAIN

GATE SOURCE

RP

n+

RP

RPRB

P p+

epi n IA IA

SUBSTRATE n+

FIGURE 3. Equivalent Circuit and Cross Section

Examination of Figure 3 suggests that the current necessaryto trigger this series of events might be closely approximatedif both the VBE of the parasitic npn bipolar transistor and Rpwere known.[7]Test patterns available on the semiconductorwafer during manufacture make it possible to examine suchparameters of the parasitic npn bipolar transistor.Measurement results of VBE, beta, and Rp

+ from the testpattern are shown in Figure 4. Because of the deep p+

diffusion that forms the Zener structure, the region beneath then+ diffusion where Rp is criticalresembles a graded

junction. Thisin concert with the dramatic temperature risethat together reduces VBE, raises Rp, and increases

betacom- complicates any effort to calculate the criticalavalanche current required to excite the parasitic bipolartransistor. Blackburn[8] derived a worst-case calculation;however, the actual performance is substantially better thanpredicted due to second-order effects.

Todays MOSPOWER devices can safely withstand over twotimes the 25_C rated current even at junction temperaturesapproaching 150_C. The active form of failure is no longer theprevalent mode under normal operating conditions. Thelimiting mechanism is now usually a thermal failure caused bythe large temperature increase during avalanche.

The Thermal Effect The Passive Mode. During UIS, as theMOSFET is subjected to increasing energy, the internal chiptemperature rises dramatically (equation 4) and is thought togenerate a mesoplasma. Such mesoplasmas (regenerativeheating) lead to the irreversible damage generally associatedwith thermal runaway.[1]* The swiftness of this temperature

rise, see equation (3), tends to make heat sinks irrelevant forUIS testing.

0 50 100 150 200 250

0.6

0.5

0.4

0

0.3

0.2

0.1

900

800

700

300

600

500

400

120

100

80

0

60

40

20

BETAVBEW/V

Temperature (_C)

(BETA) (VBE)(W/V)

FIGURE 4. Parasitic Bipolar Transistor Characteristics

During this avalanche period, as defined by equation (3),energy is dissipated in the device equation (2), resulting in adramatic increase in chip temperature. Blackburn[8] derivedthe following one-dimensional thermal model to calculate themaximum temperature rise, DTM.

*The increasing temperature during mesoplasma formation results in a decreasing thermal conductivity of silicon (see Figure 5a) which, in turn,

results in a further increase in the localized temperature. Thermal runaway is thus encouraged.


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Po = IOV(BR)eff

where

(4)

DTM = maximum instantaneoustemperature rise (_C)

and

DTM +2

3PoK tAV

K + 2A (rpkc)

+ 2 RpC

A = the active chip area (where heat originates)

r = the density of silicon

k = the thermal conductivity (very temperature

dependent (see Figure 5a)

c = the specific heat of silicon (also

temperature dependent (see Figure 1b)

R = effective thermal resistance of chip (_C/W)

C = effective thermal capacitance of chip (J/ _C)

Equation (4) can be further manipulated to relate thetemperature rise, DTM, to

(5)DTM +2

3K loV(BR)eff

Llo

V(BR)eff

Although V(BR)eff is temperature sensitive, for simplicity weassume it is a constant. Therefore,

(6)

(7)

DTM a lo L lo

or

DTM a l32

oL

1400

0 200 400 600 800 1000

1200

1000

800

0

600

400

200

Temperature (K)

1.4

40 40 120 200 280 360

1.2

1.0

0.8

0

0.6

0.4

0.2

Temperature (_C)

Figure 5a. Conductivity of Silicon vs. Temperature

([Physics Review, Vol. 130 (6/63)] (W/cm_)

Figure 1b. Specific Heat of Silicon vs. Temperature(W sec/gm_)

If we assume L is constant, equation (7) is further reduced to

(8)DTM a l 32o

which further identifies that

(9)DTM a E

34

If the parasitic bipolar transistor is notexcited, equation (9)relates the peak temperature rise to the avalanche energydissipation. This temperature rise then becomes the cause ofthe other failure mode referred to as passive.


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Test Results

The Siliconix avalanche-rated SMP30N10 is one of a family ofdense-cell MOSPOWER FETs. Cell density for this family is1.6M/in.2(248K/cm2). The overall chip area is 0.17 cm2.

UIS avalanche breakdown was examined at a variety ofinductance values (0.01 to 10 mH) at starting temperaturesfrom ambient (25_C) to 150_C in 25_C increments. A samplesize of 20 pieces for each inductance and at each temperatureinvolved over 760 MOSFETs. All MOSFETs were from thesame wafer lot.

The test method used the alternate circuit which removed VDDimmediately prior to switching. The equipment used, a ITC UISTester,* Model 5510E, allowed an increase of current, IO, in

0.1-A increments to 26 A and thereafter in 1.0-A increments.A fixed gate-drive impedance of 25 W drove the device undertest. A temperature-controlled heater was used to sink thepower MOSFET (mounted in the TO-220 package) to providea precise starting temperature throughout the UIS tests.

Temperature (_C)

I(A)

80

50

0

0 25 175

30

20

50 75 150125100

70

60

40

10

FIGURE 5. Avalanche Failure Current vs. StartingTemperature for the SMP30N10

L = 0.05 mH

L = 0.1 mH

L = 0.3 mH

L = 1.0 mH

L = 3.0 mH

L = 10 mH

Figure 5 shows avalanche current versus startingtemperature for six values of inductance, ranging from 0.05 to10 mH. These data represent single-event UIS failures andfurther identify that the device ratings, in particular theabsolute maximum ratings of IAR and TJ, are conservative.For any given inductance, the avalanche failure currentdecreased as the starting temperature increased, although not

as dramatically nor with the tight convergence described byStoltenburg.[4]Since Figure 5 represents the culmination ofincremental increases in avalanche current, these dataconclusively show that if Siliconix avalanche-rated powerMOSFETs are operated within data sheet limits, they can enterinto avalanche without fear of failure. Furthermore, these datatend to confirm that absolute maximum ratings are not soabsolute as once thought. At the 150_C starting temperatureand switching 32 A (at 1 mH), the calculated chip temperature,see equation (4), is 322_C!

The typical 2.2 mV/_C decay of VBE and the increasingresistance of the p-doped region with increasing temperaturesuggests that the parasitic npn bipolar transistor becomesmore susceptible to turn-on with increasing temperature.Although a rapid fall-off of avalanche current at highertemperatures might be anticipated because of this increasedsusceptibility, Figure 5 shows a reasonably slow decline. Thisbehavior is attributed to the slow lateral spreading of thecurrent along the p/n junction as the avalanche currentincreases. The dense cell design diminishes lateral spreadingof avalanche current beyond the heavily doped p+ (Zener)region and, thus, enables more avalanche current thanMOSFETs with less dense cell structures.

The measured data (see Figure 5) may be manipulated, withthe help of equation (2), to identify interesting details of UISphenomenon. Figure 6 plots avalanche failure current versusinductance across a temperature range from ambient to150_C.

100

1

0.01 0.1 1.0 10

10

25_C

150_C

Inductance (mH)

FIGURE 6. Avalanche Failure Current vs. Inductancefor the SMP30N10

AvalancheCurrent(A)

*Integrated Technology Corporation, 1228 N. Stadem Drive, Tempe, Arizona 85281


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L = 3 mH

0 350

2.0

1.2

0

0.8

100 200 250150

0.4

50 300

TO Initial Temperature (_C)

400

1.6

E34

(AvalancheEnergy)

J

/

34/

34/

L = 10 mH

L = 1 mH

FIGURE 7. (Avalanche Energy)3/4vs. Starting Temperature for the SMP30N10

L =0.3 mH

As shown in Figure 7, avalanche energy raised to the 3/4power, representing equation (9), was plotted against thestarting temperature. The x-axis intercepts are centeredaround 375_C. This, combined with the extraplation of VBE vs.temperature (Figure 4) appears to identify a maximuminstantaneous chip temperature beyond which aheavily-doped (low on-resistance) silicon power MOSFETcannot go!

Equation (4) suggests that the increase in temperature varieswith the square root of the time in avalanche, tAV. Plotting theactual results showed that temperature rise in practice varied

with 2.2

tAV , a relationship confirmed by Stoltenburg.[4]This

deviation is probably due to multidimensional heat spreadingand gives a slightly modified version of equation (4):

(10)DTM +2

3PoK

2.2 tAV

An Explanation for UIS Failure

A common misconception is that the absolute maximumtemperature excursion for silicon transistors must be limited to150_C. Although undoubtedly a good design rule,instantaneous chip temperatures canand do rise toappreciably higher levels under certain stressfulenvironments. No detrimental effects were observed in thesurviving power MOSFETs because of this swift temperatureexcursion.

The data confirms two failure modes: active (bipolar) andpassive (thermal).

Low inductances provide little energy (equation (2) and Figure8) to dissipate within the MOSFET chip, thus limiting theinstantaneous temperature excursion. The higher avalanchecurrents associated with these low inductances tend to

cascade laterally through the p-doped region of the MOSFET,increasing the probability of bipolar action from IARpexcitation.This active failure occurs at currents much higher than therated current of 30 A, proving the ruggedness of the cellstructure used to manufacture the Siliconix SMP30N10.

0.01 0.1 10.0

10 K

10

1 K

1.0

100

VG = 10 V

25_C

150_C

L (mH)

E

(mJ)

FIGURE 8. Avalanche Energy vs. Inductanceforthe SMP30N10


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At high inductances (i.e., at high energy levels), the extendeddecay time for the avalanche current dramatically raises thechip temperature. The silicon reaches its critical/intrinsictemperature, resulting in a mesoplasma and thermal runaway.

As mentioned earlier, Ghandhi[1] attributes secondarybreakdown of bipolar transistors to mesoplasma formations atlocalized regions on the semiconductor, which in turn, will leadto thermal runaway. The data tends to confirm a criticaltemperature at which MOSFETs can no longer withstandavalanche current. For example, the 100-V, avalanche-ratedSiliconix SMP30N10 exhibits a nominal epi doping ofapproximately 2.5 x 1015 a/cm3, and the theoretical intrinsic

temperature is360_C,[1] which is believed to be close to thecritical temperature. For power MOSFETs, it appears that thecritical and intrinsic temperatures are synonymous. Above thiscritical/intrinsic temperature, current increases rapidly, forminga localized hot spot that quickly becomes a destructive

mesoplasma.

Rating Power MOSFETs for Ruggedness

Most manufacturers of power MOSFETs rate avalanchecurrent equal to the maximum drain current specification of theparticular device. This is somewhat misleading sinceavalanche current does not pass through the gate-enhancedchannel as does the drain current. As shown in this paper andas the name implies, it is an avalanche condition that

completely bypasses the channel and is more a function of thejunction area and quality of the p/n (Zener) diode[9] that bridgesthe MOSFET.

There is, however, some rationale for rating the avalanchecurrent of power MOSFETs equal to the maximum draincurrent. During UIS breakdown, the avalanche current willnever exceed the operating drain current; it will only decayfrom this point (see Figure 2). A reasonable approach toensure MOSFET reliability would be to collectively identify 1)a safe avalanche current, 2) an operating junctiontemperature, and 3) a value of inductance.

For thermal (passive) failures, the data suggests that to ensuresafe operation, the data sheet need only give the constants foruse in equation (10) (or a graphical plot of it) and a maximumavalanche junction temperature.The user could then verify ifthe device is in the safe operating area under any conditions.

Figure 9 graphically shows the temperature rise, calculatedusing equation (10) for devices taken to failure. The tightgrouping and linear relationship proves the validity of this formof rating.

Avalanche energy ratings alone do not provide sufficientinformation to ensure against catastrophic failures becausetime in avalanche is also important. Furthermore, it is easilyderived from the critical parameters of avalanche current andinductance, see equation (2). Consequently, it does not needto be specified on the data sheet.

0 350

400

300

0

200

100 200 250150

100

50 300

To Starting Temperature (_C)

400

L = 10 mH

L = 3 mH

FIGURE 9. Temperature Increase vs. Starting Temperatures

PeakIncreaseinTemperature(

mT

_C)

D

L = 1 mH

L = 0.3 mH


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References

Sorab K. Ghandhi, Semiconductor Power Devices(Wiley-Interscience: New York, 1977).

Edwin S. Oxner, Static and Dynamic dV/dt Characteristics of Power MOSFETs, PCI Proceedings, 13242, Atlantic City (1984).

D. S. Kuo, C. Hu, and M. H. Chi, dV/dt Breakdown in Power MOSFETs, IEEE Electron Device Letters, EDL4, No. 1 (Jan. 1983).

Rodney R. Stoltenburg, Boundary of Power MOSFET Unclamped Inductive Switching (UIS), Avalanche-Current Capability, IEEEApplied Power Electronics Conference Proceedings, 35964, (Mar. 1989).

David L. Blackburn, Turn-off Failure of Power MOSFETs, IEEE Power Electronics Specialists Conference, 42935 (June 1985).

John W. Worman, Using Power MOSFETs in Unclamped Inductive Switching Applications, Powertechnics(Oct. 1988).

Chenming Hu and Min-Hwa Chi, Second Breakdown of Vertical Power MOSFETs, IEEE Transactions on Electron Devices,ED29, 128793 (Aug. 1988).

David L. Blackburn, Power MOSFET Failure Revisited, IEEE Power Electronics Specialists Conference, Kyoto, Japan (Apr.1988).

Alford L. Ward, Calculations of Second Breakdown in Silicon Diodes, U.S. Army ERDC Harry Diamond Laboratories,HDLTR1978 (Aug. 1982).

70572-AN601-Unclamped Inductive Switching Rugged MOSFETs for Rugged Environments

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