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INTRODUCTION TO MC 68HC11

MICROCONTROLLER

Dr. V.Jeyalakshmi.,Ph.D.,

Department of ECE

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INTRODUCTION

Motorola Inc ,one of the pioneers inmicrocontroller manufacturing has introducedthis 8-bit microcontroller M68HC11 in the

year 1985 and it is descended from theMotorola 6800 microprocessor. Now it isproduced by Freescale Semiconductors.

It is a CISC microcontroller , optimized forlow power consumption and high-performanceoperation at bus frequencies up to 4 MHz.

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Contd..

The 68HC11 chip has built-in

EEPROM/OTPROM, RAM, digital I/O,

timers, A/D converter, PWM generator, and

synchronous and asynchronous

communications channels (RS232 and SPI).

Typical current draw is less than 10mA.

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Contd..

The 68HC11 devices are more powerful andmore expensive than the 68HC08

microcontrollers, and are used in barcode

readers, hotel card key writers, amateur

robotics, and various other embedded

systems. The MC68HC11A8 was the first

MCU to include CMOS EEPROM.

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Series of M68HC11The 68HC11 is available in various series as below

A series - basic model.

D series - economical alternative, less

memory, peripherals.

E series - has wide range of I/O capabilities.

F series - higher speed, extra I/Os.

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Contd

G series - 10-bit ADC and better timer systems.

K series - high speed, larger memories, MMU, and

PWM.

L series - high speed, low power, static design.

M series - has math coprocessor and four channel

DMA.

P series - power-saving PLL and 3 SCI ports.

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OPERATING MODES

The 6811 can operate in one of the four modes: Mode0: Bootstrap mode: used to load programs

into RAM.

Mode1: Single-chip mode: uses internal memoryfor program & data.

Mode2: Test mode : used by Motorola to test the

chip is operation

Mode3: Expanded mode :allows for use of

external memory.

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Bootstrap (MODA=MODB=0)

i. On power up or reset, the program in the bootstrap

ROM is executed

ii.CPU waits for a 256-byte program segment to be

downloaded through the serial link and stored

starting at address #0000

iii.Execution then begins at address $0000

iv.Permits wide variety of programs to be

downloaded

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Single chip (MODA=0, MODB=1)

i. No external address and data bus functions

CPU can only access on-chip memory

ii.Ports B and C are general purpose parallel I/Oiii.All software needed to control MCU must be

in internal memory

iv. On reset, execution begins at address #E000

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Test Mode(MODA=1, MODB=0)

i. Primarily used to test the chip by the

manufacturerii. Overrides some automatic protection

mechanisms

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Expanded multiplexed (MODA=MODB=1)

i. External memory and peripheral devices can beaccessed by time-multiplexed address-data bus

ii.Port B used for high byte of address (output)

iii.Port C provides low byte of address (output)

and 8- bit data (bi-directional)

iv.External address latch is required

v.Execution begins at address #E000

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SALIENT FEATURES

The HCMOS MC68HC11 is an advanced 8-bitMCU with numerous on-chip peripheralcapabilities.

Up to 10MIPS Throughput at 10MHz

256 Bytes of RAM , 512 Bytes of In-SystemProgrammable EEPROM and ProgrammingLock.

Eight channel 8-bit Analog to Digital Convertor One serial peripheral interface, with a speed up

to 1M

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Contd

The MC68HC11 is available in two packages .

One is 48-pin dual inline package (DIP) and the

other is the 52 Pin Plastic Leaded Chip

Carrier(PLCC) known as Lead quad pack.

In the 48 pin DIP package 38 pins are available

for I/O functions.(34 I/O lines+ 2 interrupt lines

+ 2 hand shake control lines).

Similarly in a 52 PLCC pack 42 pins are meant

for different I/O functions, and the remaining are

used for interrupt and handshake signals.

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Contd..

MC68HC11 has one universalAsynchronous Serial CommunicationsInterface (UART)

One Watchdog Timer

One 16-Bit free running timer, with 3capture functions and 5 comparefunctions

One Pulse Accumulator and Powerful bit-manipulation instructions

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Contd..

Six powerful addressing modes(Immediate, Extended, Indexed, Inherent

and Relative)

Power saving STOP and WAIT modes

Memory mapped I/O and special

functions

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68HC 11 ARCHITECTURE

It is based on HCMOS Technology and has a

common internal bus for the address and data

of 8-bits.

It has an MCU clock whose frequency can be

educed to zero. As the MCU is completelyMOSFET based the power dissipation is

negligible in stop or start states. So,this is

optimized for lowpower consumption andhigh performance operation.

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CPU FEATURES An 8M.Hz XTAL(external clock) with 2 M.Hz

clock related operations. A 16-bit program counter that loads a powerup

value from a reset vector address 0xFFFE 0xFFFF

Two 8- bit Accumulators A and B work as generalpurpose registers. They can be concatenated as a16-bit double accumulator [D].

Two 16-bit Index registers Ix and Iy can be usedas pointers to memory locations and hold the 16bit addresses of memory locations .

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Contd..

It has a multiplexed address and data bus.

One 16bit stack pointer ,which decreases by

1 after the push of each byte.

Two external interrupts IRQ ,XIRQ .One of

the is can be configured as non-maskable

external interrupts like NMI in 80196.

Although this is an 8-bit processor ,it has some

16-bit instructions.(ADD,Sub,shift and rotate)

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68HC11 Registers

The MC68HC11 microcontroller has a rich set of

registers and they are classified into two categories: CPU registers and I/O registers.

The CPU Registers are shown in the next slide.

A and B are the two 8-bit registers called generalpurpose accumulators which are used to performmost of the arithmetic operations. These twoaccumulators can be concatenated to form a 16-bitaccumulator which is known as double

accumulator D. This accumulator is used for 16bit operations.

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Contd..

Index registers (IX and IY).Two 16-bit

registers used mainly in addressing memoryoperands. They normally used to hold

addresses of 16-bit memory locations. These

registers are also , some times used for themfor 16-bit computation also.

Stack Pointer (SP):Stack is a first in first out

data structure. This 16-bit stack pointerregister hold the address of the stack top.

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REGISTER ORGANISATION

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Program Counter(PC): It is a 16-bit register which

stores the address of the next instruction to be

executed. The 68HC11fetches the instruction one

byte at a time and increments the PC by 1 after

after fetching each instruction byte. After the

execution of an instruction the PC is incremented

by the number of bytes of the executed

instruction.

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Condition Code Register (CCR)

This is an 8-bit register used to keep track ofthe program execution status , control the

execution of conditional branch instructions

and enable/disable the interrupt handling .

This register contains five status indicators,

two interrupt masking bits, and a STOP disablebit. The register is named for the five status

bits since that is the major use of the register.

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Contd..

These status flags reflect the results of arithmetic and

other operations of the CPU as it performs

instructions. The five flags are half carry (H),negative

(N), zero (Z), overflow (V), and carry/borrow (C).

The half-carry flag, which is used only for BCD

arithmetic operations is only affected by the add

accumulators A and B (ABA), ADD, and add with

carry (ADC) addition instructions

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Contd.. The N, Z, V, and C status bits allow for branching

based on the results of a previous operation.Simple branches are included for either state ofany of these four bits. The H bit indicates a carryfrom bit 3 during an addition operation. This

status indicator allows the CPU to adjust theresult of an 8-bit BCD addition so it is in correctBCD format, even though the add was a binaryoperation. This H bit, which is only updated by

the ABA, ADD, and ADC instructions, is used bythe DAA instruction to compensate the result inaccumulator A to correct BCD format.

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Contd..

The N bit reflects the state of the mostsignificant bit (MSB) of a result. For twos

complement, a number is negative when the

MSB is set and positive when the MSB is 0.

The N bit has uses other than in twos-

complement operations. By assigning an often

tested flag bit to the MSB of a register or

memory location, the user can test this bit byloading an accumulator.

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Contd

The Z bit is set when all bits of the result are0s. Compare instructions do an internal

implied subtraction, and the condition codes,

including Z, reflect the results of thatsubtraction. A few operations (INX, DEX,

INY, and DEY) affect the Z bit and no other

condition flags.

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Contd

The C bit is normally used to indicate if a carryfrom an addition or a borrow has occurred as a

result of a subtraction. The C bit also acts as an

error flag for multiply and divide operations.Shift and rotate instructions operate with and

through the carry bit to facilitate multiple-word

shift operations.

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Contd..

The STOP disable (S) bit is used to allow ordisallow the STOP instruction. Some users

consider the STOP instruction dangerous

because it causes the oscillator to stop;

however, the user can set the S bit in the CCRto disallow the STOP instruction. If the STOP

instruction is encountered by the CPU while

the S bit is set, it will be treated like a no-operation (NOP) instruction, and processing

continues to the next instruction.

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Contd.. The interrupt request (IRQ) mask (I bit) is a global mask that

disables all maskable interrupt sources. While the I bit is set,

interrupts can become pending and are remembered, but CPU

operation continues uninterrupted until the I bit is cleared.

After any reset, the I bit is set by default and can be cleared

only by a software instruction.

When any interrupt occurs, the I bit is automatically set afterthe registers are stacked but before the interrupt vector is

fetched. After the interrupt has been serviced, an RTI

instruction is normally executed, restoring the registers to the

values that were present before the interrupt occurred. The XIRQ mask (X bit) is used to disable interrupts from the

XIRQ pin. After any reset, X is set by default and can be

cleared only by a software instruction

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Addressing Modes

Addressing modes are used to specify the operandsneeded in an instruction.

The M68HC11 CPU supports SIX addressingmodes. They are

Immediate addressing mode Direct addressing

Extended addressing

Indexed (with either of two 16-bit index registers

and an 8-bit offset) Inherent and

Relative addressing mode.

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Contd

Each of the addressing modes (except

inherent) results in an internally generated,double-byte value referred to as the effective

address.This value appears on the address bus

during the external memory reference portionof the instruction

All bit-manipulation instructions use

immediate addressing to fetch a bit mask, and

branch variations use relative addressing mode

to determine a branch destination.

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Immediate (IMM)

In the immediate addressing mode, the actualargument is contained in the byte(s) immediatelyfollowing the instruction in which the number ofbytes matches the size of the register. These

instructions are two, three, or four (if pre byte isrequired) bytes.

In this case, the effective address of theinstruction is specified by the character # sign andimplicitly points to the byte following the opcode.The immediate value is limited to either one ortwo bytes, depending on the size of the registerinvolved in the instruction.

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Examples

LDAA #22 ; loads the decimal value 22 into theaccumulator A.

ADDA #@32 ; adds the octal value 32 toaccumulator A.

LDAB #$17 ; loads the hex value 17 intoaccumulator B.

LDX #$1000 ; loads the hex value 1000 into the

index register X, where the upper byte of Xreceives the value of $10 and the lower byte of Xgets the value of $00.

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Character prefixes

Prefix Definition

None Decimal

$ Hexadecimal@ Octal

% Binary

Single ASCII character

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Direct Mode (DIR)

In the direct addressing mode, the least

significant byte of the effective address of the

instruction operand appears in the byte

following the opcode

The high-order byte of the effective address is

assumed to be $00 and is not included in the

instruction. This limits use of the direct mode

to operands in the $0000-$00FF area of thememory.

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Examples ADDA $00 ; adds the value stored at the memory

location with the effective address $0000 toaccumulator A.

SUBA $20 ;subtracts the value stored at thememory location whose address is $0020 fromaccumulator A.

LDD $10 ; loads the contents of the memorylocations at $0010 and $0011 into double

accumulator D, where the contents of the memorylocation at $0010 are loaded into accumulator Aand those of the memory location at $0011 areloaded into accumulator B.

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Extended Mode (EXT)

In the extended addressing mode, the effectiveaddress of the operand appears explicitly in the

two bytes following the op code

EX: LDAA $1003 ; loads the 8-bit valuestored at the memory location with effective

address $1003 into accumulator A.

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Indexed Mode (INDX, INDY)

In the indexed addressing mode, one of the indexregisters (X or Y) is used in calculating theeffective address.

So, the effective address is variable and depends

on the current contents of the index register X (orY) and a fixed, 8-bit unsigned offset contained inthe instruction. Because the offset byte isunsigned, only positive offsets in the range from 0

to 255 can be represented. If no offset is specified,the machine code will contain $00 in the offsetbyte.

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Examples

ADDA 10,X ; adds the value stored at the

memory location pointed to by the sum of 10and the contents of the index register X toaccumulator A.

Each of the following instructions subtracts thevalue stored at the memory location pointed toby the contents of index register X fromaccumulator A

SUBA 0,X

SUBA ,X

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Inherent Mode (INH)

In the inherent mode, everything needed to

execute the instruction is encoded in theopcode. The operands are CPU registers andthus are not fetched from memory. Theseinstructions are usually one or two bytes.

Exs: ABA ; adds the contents of accumulator Bto accumulator A.

INCB ; increments the value of accumulator B

by 1. INX ; increments the value of the index register

X by 1.

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Relative Mode (REL)

The relative addressing mode is used only forbranch instructions. Branch instructions, otherthan the branching versions of the bit-manipulation instructions, generate two

machine-code bytes, one for the opcode andone for the branch offset.

The branch offset is the distance relative to thefirst byte of the instruction immediately

following the branch instruction. The branchoffset has a range of 128 to 127 bytes.

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Example

BEQ $e164

$e100 ADDA #10

...

$e164 DECB...

The 68HC11 will branch to execute the

instruction DECB if the Z bit in the CCRregister is 1, when the instruction BEQ $e164

is executed.

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Parallel I/O PORTS

There are 5 on chip I/O ports. They are

Port A , Port B , Port C, Port D and Port E

Port A (8 bits)

1 bidirectional pin, 4 output pins, 3 input pins , Also usedfor timer

Port B (8 bits)

8 output pins with optional handshaking , Also usedas address in expanded mode (replaced by PRU)

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Contd..

Port C (8 bits)

8 bidirectional pins with optional handshaking andwired-or mode Also used as data/address inexpanded mode (replaced by PRU)

Port D (6 bits)6 bidirectional pins (controlled by direction

register), Also used for asynchronous (SCI)and synchronous serial (SPI) I/O

Port E (8 bits)

8 input pins , Also used for A/D converter

d

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Contd..

Port A has three fixed-direction input pins,

four fixed-direction output pins, and onebidirectional pin. The direction of the PA7 pin

is controlled by the data direction register A

bit 7 control bit (DDRA7) in the pulseaccumulator control (PACTL) register. Port A

data is read from and written to the PORTA

register.

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Ports B & PORT C

Port B is a general-purpose, 8-bit, fixed-

direction output port. Writes to the port B

register (PORTB) cause data to be latched and

driven out of the port B pins.

Port C is a general-purpose, 8-bit, bidirectional

I/O port. The primary direction of data flow at

each port C pin is independently controlled by

a corresponding bit in the data directioncontrol register for port C (DDRC).

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PORT D Port D is a general-purpose, 6-bit, bidirectional data

port . Two port D pins are alternately used by theasynchronous serial communications interface (SCI)

subsystem. The remaining four port D pins are

alternately used by the synchronous serial peripheral

interface (SPI) subsystem . The primary direction of data flow at each of the port

D pins is selected by a corresponding bit in the data

direction register for port D (DDRD).Port D can be

configured for wired-OR operation by setting the portDwired-OR mode control bit (DWOM) in the SPI

control register (SPCR).

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PORT E

Port E is an 8-bit, fixed-direction input portPE7-PE0. Port E pins alternately function as

analog-to-digital (A/D) converter channel

inputs. Port E input buffers are speciallydesigned so they will not draw excessive

power-supply currents when their inputs are

driven by intermediate levels.

The features of these ports are given in a table

in the next slide

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Features of I/O Ports

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RESETS AND INTERRUPTS

Reset is used to force the microcontroller unit(MCU) to assume a set of initial conditionsand to begin executing instructions from apredetermined starting address.

For most practical applications, the initialconditions take effect almost immediatelyafter applying an active-low level to the RESETpin. Some reset conditions cannot take effectuntil/unless a clock is applied to the externalclock input (EXTAL) pin.

C td

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Contd..

Once the reset condition is recognized, internal

registers and control bits are forced to an initialstate. These initial states, in turn, control on-chip

peripheral systems to force them to known start-

up states. Most of the initial conditions are

independent of the operating mode.

After reset, the CPU fetches the restart vector

from locations $FFFE,FFFF ($BFFE,BFFF if in

special test or bootstrap mode) during the firstthree cycles and begins executing instructions.

C td

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Contd.. The stack pointer and other CPU registers are indeterminate

immediately after reset; however, the X and I interrupt mask

bits in the CCR are set to mask any interrupt requests. Also,the S bit in the CCR is set to disable the stop mode.

After reset, the RAM and I/O mapping (INIT) register is

initialized to $01, putting the 256 bytes of random-accessmemory (RAM) at locations$0000$00FF and the control

registers at locations $1000$103F. The8-Kbyte read-only

memory (ROM) and/or the 512-byte EEPROM may or may

not be present in the memory map because the two bits thatenable them in the configuration control (CONFIG) register

are EEPROM cells not affected by reset or power-down.

C d

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Contd..

During reset, the timer system is initialized toa count of $0000. The prescaler bits are

cleared, and all output-compare registers are

initialized to $FFFF. All input-capture registers

are indeterminate after reset.

The timer overflow interrupt flag and all eight

timer function interrupt flags are cleared. All

nine timer interrupts are disabled since their

mask bits are cleared.

C td

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Contd..

The real-time interrupt flag is cleared, andautomatic hardware interrupts are masked. The

rate control bits are cleared after reset and may

be initialized by software before the real-time

interrupt system is used.

The pulse accumulator system is disabled at

reset so that the pulse accumulator input (PAI)

pin defaults to being a general-purpose inputpin.

C td

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Contd

The computer operating properly (COP)

watchdog system is enabled if the NOCOPcontrol bit in the CONFIG register (EEPROMcell) is clear and disabled if NOCOP is set. TheCOP rate is set for the shortest duration timeout.

The reset condition of the SCI system isindependent of the operating mode. At reset, theSCI baud rate is indeterminate and must beestablished by a software write to the BAUDregister. All transmit and receive interrupts aremasked, and both the transmitter and receiver aredisabled so the port pins default to being general-purpose I/O lines.

Contd

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Contd..

The SPI system is disabled by reset. The portpins associated with this function default to

being general-purpose I/O lines.

The A/D converter system configuration is

indeterminate after reset. The conversion

complete flag is cleared by reset. The A/D

power-up (ADPU) bit is cleared by reset,

disabling the A/D system.

C td

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Contd..

The EEPROM programming controls are all

disabled so the memory system is configured for

normal read operation.

A few registers are not forced to a startup

condition as a result of reset. Since these registersdo not affect the starting conditions at MCU pins.

One such register is the main-timer input-capture

register. Since these registers are not useful untilafter an input capture occurs, it is not important to

force them to a startup state during reset.

P O R t (POR)

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Power-On Reset (POR) The POR is only intended to initialize internal

MCU circuits. As VDD is applied to the MCU,the POR circuit triggers and initiates a resetsequence. POR triggers an internal timing circuitthat holds the RESET pin low for 4064 cycles ofthe internal PH2 clock. The MCU does not

advance past this reset condition until a clock ispresent at the EXTAL pin long enough for these4064-cycle PH2 clocks to be detected.

The internal POR circuit will not retrigger unless

VDD has discharged to 0 V; therefore, theinternal POR circuit is not suitable as a power-loss detector.

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COP Watchdog Timer Reset

The COP watchdog timer system is intended to

detect software processing errors. When the

COP is being used, software is responsible for

keeping a free-running watchdog timer from

timing out. If the watchdog timer times out, itis an indication that software is no longer

being executed in the intended sequence; thus,

a system reset is initiated.

E t l R t

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External Reset

In addition to the internal sources, reset can be

forced by applying a low level to the RESETpin. The resulting reset sequence is identical to

the internal causes. Upon recognition of the

reset request, internal logic turns on aninternal N-channel device, which actively

holds the RESET pin low for about four

cycles.

I t t P

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Interrupt Process

The CPU in a microcontroller sequentiallyexecutes instructions. In many applications, it isnecessary to execute sets of instructions inresponse to requests from various peripheraldevices. These requests are often asynchronous tothe execution of the main program. Interruptsprovide a way to temporarily suspend normalprogram execution so the CPU can be freed to

service these requests. After an interrupt has beenserviced, the main program resumes as if therehad been no interruption

Contd

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Contd..

The instructions executed in response to an

interrupt are called the interrupt service routine.These routines are much like subroutines exceptthat they are called through the automatichardware interrupt mechanism rather than by a

subroutine call instruction, and all CPU registersare saved on the stack rather than just saving theprogram counter.

Interrupts can be enabled or disabled by mask bits

(X and I) in the CCR and by local enable maskbits in the on-chip peripheral control registers.

R t f I t t

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Return from Interrupt When an interrupt has been serviced as needed, the

return-from interrupt(RTI) instruction terminatesinterrupt processing and returns to the program that wasrunning at the time of the interruption. During servicingof the interrupt, some or all of the CPU registers willhave changed. To continue the former program as if it

had not been interrupted, the registers must be restoredto the values present at the time the former programwas interrupted. The RTI instruction accomplishes thisby pulling (loading) the saved register values from the

stack memory. The last value to be pulled from thestack is the program counter, which causes processingto resume where it was interrupted.

Contd

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Contd..

The MC68HC11 has 21 independent

interrupts . In this,6 are non- maskable and 15

are maskable . The three high priority

interrupts are RESET , HIRQ and IRQ .

TIMERS

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TIMERS

The MC68H11 has one 16-bit free-running 16-

bit counter with a 4-stage programmable pre-scaler. A timer overflow function allows softwareto extend the timing capability of the systembeyond the 16-bit range of the counter.

Three independent input-capture functions areused to automatically record (latch) the time whena selected transition is detected at a respective

timer input pin. Five output-compare functionsare included for generating output signals or fortiming software delays.

Contd

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Contd..

The timer subsystem involves more registers

and control bits than any other subsystem onthe MCU. Each of the three input-capture

functions has its own 16-bit time capture latch

(input-capture register) and each of the fiveoutput-compare functions has its own 16-bit

compare register. All timer functions,

including the timer overflow and RTI, have

their own interrupt controls and separate

interrupt vectors.

SELF PROTECTION

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SELF PROTECTION

All pins of M68HC11 have internal inherent

diode clamps to Vss .This MCU has certainspecial internal circuit arrangements such that

the MCU can operate at VDD7 volts with out

damage . The COP watch dog timer willalways provide protection from any

malfunction. The watch dog timer also

provides self protection to the MCU from

damage.

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REFERENCES

1.M68HC11 Microcontrollers Data sheet ,MOTOROLA.COM/SEMICONDUCTORS.

2.Design With Microcontrollers

John B. Peatman ,McGraw Hill Intl.Ed

3. Introduction to Motorola 68HC11 -HUANG

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GOOD LUCK !!