608�

IEEE TRANSACTIONS ON COMPUTER-AIDEDDESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,VOL. 18, NO. 5, MAY 1999

An Efficient Approachto Multilayer LayerAssignmentwith anApplicationto Via Minimization

Chin-Chih�

Changand Jason(JingSheng)Cong, Senior�

Member,IEEE

Abstract—In this paper we presentan efficient heuristic algo-rithm for the post-layout layer assignmentand via minimizationpr� oblem of multilayer gridless integrated circuit (IC), printedcir� cuit board (PCB), and multichip module (MCM) layouts. Weformulate the multilayer layer assignmentproblem by intr oduc-ing�

the notion of the extendedconflict-continuation (ECC) graph.When�

the formulated ECC graph of a layer assignmentproblemis�

a tree,we showthat the problem can be solvedby an algorithmwhich� is both linear time and optimal. When the formulated ECCgraph� is not a tree, we present an algorithm which constructsa sequenceof maximal induced subtreesfr om the ECC graph,then

applies our linear time optimal algorithm to each of theinduced�

subtreesto refinethe layer assignment.Our experimentsshow� that, on average, the number of vertices of an inducedsubtr� ee found by our algorithm is between 12% and 34% ofthe

total number of vertices of an ECC graph. This indicatesthat

our algorithm is able to refine a large portion of the layoutoptimally� on each refinement, thus, producing highly optimizedlayer assignmentsolutions. We applied this algorithm to the viaminimization problem and obtained very encouragingresults.Weachieved 13%–15% via reductionon the routing layout generatedby

the V4R router [1], which is a router known to havelow usageof� vias. Our algorithm has been successfullyapplied to routingexamples� of over 30000 wir e segmentsand over 40000 vias.Finally,�

we outline how our layer assignmentalgorithm can alsobe

usedfor delayand crosstalkminimization in high-performanceIC,�

PCB, and MCM designs.

I. INTRODUCTION�

A S�

very large scale integration (VLSI) technology ad-vances,� interconnectionandpackagingtechnologieshave

become�

bottlenecksin system performance.For advancedintegrated circuit (IC) designs, four to six routing layersare� commonly used in high-performanceand high-densitydesigns.�

Multichip module(MCM) technologywasdevelopedto�

increasepackingdensities,eliminatethepackaginglevel ofinterconnections,andprovidemorelayersfor routing. In boththe�

multilayerIC andMCM designs,thedesigneror automaticlayout�

toolsmayusevariablewidthsandspacingsto optimizeperformance.� This often resultsin multilayer gridlesslayouts.

Becausemultilayer gridless routing is a complex three-dimensional�

generalarearouting problem, it is not easy to

Manuscript�

receivedFebruary11,1998.Thiswork wassupportedin partbyDARPA/ETO underContractDAAL01-96-K-3600managedby theU.S.ArmyResearchLaboratory,anda grant from Intel underthe 1996–1997CaliforniaMICRO�

program.This paperwas recommendedby AssociateEditor C.-K.Cheng.

C.-C. Chang is with the Computer ScienceDepartment,University ofCalifornia,Los Angeles,CA 90095USA (e-mail: cchang@cs.ucla.edu).

J.�

Congis with theComputerScienceDepartment,Universityof California,Los�

Angeles,CA 90095USA (e-mail: cong@cs.ucla.edu).Publisher�

Item Identifier S 0278-0070(99)02968-1.

design�

a router which can simultaneouslyoptimize manydif�

ferent designobjectives,suchas wire length, area,delay,crosstalk,� numberof vias, etc. Therefore,it is important toperform� certain post-layoutoptimizationsto help the routermeet� various design constraintsand producebetter routingsolutions.

One!

of the important post-layoutoptimization techniquesis"

layer assignment,in which wire segmentsin a routingsolution are reassignedto appropriatelayers to achievecer-tain�

optimization objectives.Layer assignmenthas becomean� interesting topic for the following two reasons:first, itpreserves� thewire lengthsandtopologiesduringoptimizations;second, it providesconsiderableflexibility for optimizationsof# vias, crosstalk,and delays. In this paper,we presentanef$ ficient multilayer layerassignmentalgorithmfor bothgridedand� gridless layout with focus on its application to the viaminimization� problem.

The via minimization problem is that of minimizing thenumberof vias in a VLSI layout. A via is a hole filled withconductive� materialsto connectwire segmentson differentlayers�

in a VLSI layout.Becausevias often reducethe manu-facturing%

yield, degradethe circuit performance,and increaselayout area(more difficult to compactrouting solutions,e.g.,refer to [2]), it is desirableto minimize the numberof viaswithout& affecting routability.

The via minimization problem was first studied for two-layerVLSI layouts.Therearetwo approachesfor thetwo-layervia� minimizationproblem:unconstrainedvia minimization(ortopological�

via minimization) [3], [4] and constrainedviaminimization[5]–[13]. Topologicalvia minimizationcomputesboth�

the topologiesand the layer assignmentsof all the netsbefore�

detailed routing to minimize the overall via count.However,'

topologicalvia minimizationmay affect routabilityconsiderably� andis usuallynot usedin practice.Moreover,thetwo-layer�

topological via minimization problem was shownto�

be NP-hard [4]. On the other hand, the constrainedviaminimization� problemoptimizesan existing( routing) solutionby�

only changingthe layer assignmentsof the wire segments.It is also referredto as the layer

*assignmentproblem.�

For the two-layerconstrainedvia minimizationproblemforManhattan+

layoutswith junctiondegreeslessor equalto three,polynomial� time optimal algorithmshavebeendeveloped[6],[8], [9], [12]. Thesealgorithmstransformtheprobleminto theplanar� maximumcut problem,which is solvablein polynomialtime.�

However, if the layout is not Manhattanwith junctiondegrees�

lessor equal to three, the two-layer constrainedviaminimizationproblemwasshownto be NP-hard[13]–[15].

0278–0070/99$10.00 1999 IEEE

CHANG,

AND CONG: MULTILAYER LAYER ASSIGNMENT WITH AN APPLICATION TO VIA MINIMIZA TION 609

There-

is also a considerableamount of researchworkdone�

on the multilayer constrainedvia minimizationproblem.Chang.

and Du first proved that the three-layerconstrainedvia� minimization problem on Manhattanrouting is NP-hard[16]. They also proposeda heuristicalgorithm which checksvias� one by one and conductsa local searchup to levelson# the via-crossinggraphto eliminatethe via being checked(in/

their implementation, was& set to be two). Fang et(al0 . [17] proposeda two-phaseheuristicalgorithm. They useheuristic1

ordering and backtrackingto assignthe layers ofwire& segmentsoneby one and then do local perturbationstoeliminate$ vias greedily.However,whenonevia is eliminated,other# viasmightbeintroduced.Ahn andSahni[15] provedthatthe�

three-layerconstrainedvia minimizationproblemremainsto�

be NP-hardfor Manhattanrouting even if the routing isrestricted) to HVH channelrouting. They proposeda track-by-track�

heuristicalgorithmfor layer assignmentin the HVHconstrained� via minimization problem.

The-

existing methodsfor multilayer constrainedvia mini-mizationsuffer from oneor moreof the following problems:

• handlesonly a fixed numberof layers;• assumesa grid-baserouting solution;• cannotproducegoodsolutionsdueto very limited range

of# local search;• cannotscaleto large designsefficiently.

All2

the experimentalresultson constrainedvia minimizationreportedin the literatureare on small test caseswith only afew%

hundredvias.In3

this paper, we introduce the notion of the extendedconflict-continuation� (ECC) graph that abstractsthe connec-tivity�

relations of a given layout for the layer assignmentproblem.� TheECC graphis generalenoughto handlegridlesslayoutswith anynumberof routinglayers.Whena formulatedECC graph is a tree, we show that the layer assignmentproblem� canbe solvedin linear time optimally by a dynamicprogramming� technique.For the general case of the layerassignment� problemwhere the ECC graph is not a tree, ouralgorithm� constructsa sequenceof inducedsubtreesfrom theECC graphand appliesour linear time optimal algorithm toeach$ inducedsubtree.Our experimentsshowthat the averagenumber of vertices of the induced subtreesconstructedbyour# algorithm is very large, containing 12%–34% of thetotal�

numberof verticesof the ECC graph. It indicatesthatour# algorithm is able to r4 efinea large portion of the layoutoptimally5 each time,6 which leads to highly optimized layerassignment� solutions.The applicationof our layer assignmentalgorithm� to theconstrainedvia minimizationproblemis verysuccessful. We haveachieved13%–15%via reductionon therouting solutionsgeneratedby the V4R router [1], which isa� router known to have low usageof vias. Our algorithmscales well for handlinglargedesigns;it hasbeensuccessfullyapplied� to routing examplesof over 30000 wire segmentsand� over 40000 vias. An extendedabstractof this work waspresented� at the 1997DesignAutomationConference[20].

The-

applicationsof our algorithm are not limited to thevia� minimization problem becauseour formulation is verygeneral7 and can consideroptimization objectivesother than

Fig.8

1. Wire segmentation.

via� minimization.At the endof this paper,we will showthatour# layerassignmentalgorithmcanalsobeusedfor delayandcrosstalk� minimizationin high-performanceIC, printedcircuitboard�

(PCB) and MCM designs,when propercost functionsare� used.

II.3

PROBLEM9 F

:ORMULATION

Given;

a valid -layer layout solution,eachnet is dividedinto"

a set of wire segments.We assumeno vias are allowedwithin& a wire segment.Therefore,eachwire segmentmustbe�

assignedto a single layer, while vias can only be usedto�

connect different wire segmentsof the same net. Thedesigner�

may specify the segmentationof wires to imposecertain� layout constraintsandcontrol the tradeoff betweentheflexibility<

and complexity of the layer assignmentproblem.For:

example,Fig. 1 showsa simple layout. Assumethat thewires& connectingpoints – are� of thesamenet;all theothervertical� linesareof differentnets.A naturalwayof segmentingthe�

wiresis to breakthenetsat thepointswherethehorizontaland� vertical wires meet(cf. [6]). In this case,we will breaknet into segments ,6 and . Anotherpossible� choiceis to breakthe netswheneverthereis enoughspace to insert vias (cf. [9]). Supposethat there is enoughspace at point to

�put a via between and� . In this case,

we& will further break into"

and� . Inthe�

first case,we havelessflexibility to insertvias,but smallerproblem� sizebecausewe havefewer segmentsto consider.Inthe�

secondcase,we havelessrestrictionon insertingvias,butmore� wire segmentsfor the optimizationproblem.Therearealso� otherpossiblewaysto breaknets.For example,we mightwant& to restrictthemaximumlengthof a singlewire segment.It3

is alsopossiblethatwe want to restricttheminimumlengthsuch thatwe do not to breakwirestoo often.All thesechoiceswill& haveimpactson theflexibility andcomplexity.Dependingon# the design,the designermay preferoneoption to anotherbased�

on the considerationof flexibility they want and thecomplexity� they can handle.Our algorithm can handleanygiven7 wire segmentationwithout any restrictions.

After the wire segmentationis done, it is not difficult tosee that therearebasicallytwo kinds of relationsamongwiresegments in the layer assignmentproblem:wires that cannotbe�

put in the samelayer andwires that mustbe connectedto

610�

IEEE TRANSACTIONS ON COMPUTER-AIDEDDESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,VOL. 18, NO. 5, MAY 1999

each$ other. The first is called the conflict= relation; it occursamong� wire segmentsof differentnetsoverlappingwith eachother# (when layers are ignored). The secondis called thecontinuation= relation; it occurs among wire segmentswithcommon� end points of the samenet.

Pinter [9] proposedthe conflict-continuationgraph whichcaptures� the aboverelationshipsamongwires during his for-mulation of the two-layer via minimization problem. In hisformulation,a fr

>eerun is a maximal pieceof wire that does

not? overlapanyotherwire, andcanaccommodateat leastonevia.� A “wir e segment”is a pieceof wire connectingtwo freeruns. Eachvertex representswire segment . Theedgeset representstwo kindsof relationshipsamongwire& segments.The set is

"the set of continuation= edges.

An edge exists$ betweenvertices and� if, andonly# if, and� are� in the samenet and are connectedtoeach$ other.Assigning and� to

�different layerswill require

a� via to be inserted.The set is the set of conflict= edges;an� edge exists$ betweenvertices and� if, andonly# if, and� are� in different netsand cannotbe assignedto�

the samelayer.The conflict-continuationgraph is sufficient for the repre-

sentation of the two-layervia minimizationproblem,but it isnot suitablefor multilayer representationwhen stackedviasare� allowed.1 For example,considera layout which consistsof# three wire segments:wire segments and� are� of thesame netandconnectedby a continuationedge;wire segment

is from a different net and overlapswith the intersectionof# and� ,6 thus, conflicting with and� . Becausestackedvias� are allowed, it is legal to assign to

�layer 1, and to

�layer 3. In this case,if we assign to

�layer 2, it canpassthe

conflict� checkingimposedby the conflict-continuationgraphbecause�

it is assignedto a layer differentfrom thoseof and�. However,thereis a conflict between and� the stackedvia

which& connects and� .W@

e addresstheaboveproblemsby extendingtheconceptofconflict-continuation� graphssothatit canhandlethemultilayerlayer assignmentproblem properly. In our ECC graph, thevertex� set containsviaA vertices in addition to wirB e segmentverticesA .2

CEachD

via vertex is a possiblelocation to insert avia.� It connectstwo or more wire segmentsof the samenetin the given layout. It may overlap with some wires, butour# formulation can representtheseconflicts. A via vertexcan� also have a layer assignment.The layer assignmentfora� via is a pair of integers ,6 indicating thata� via spans from layer to

�layer . Note that we can

easily$ representvias connectingmorethanonelayer (stackedvias)� underthis representation.If no stackedviasareallowed,we& restrict . For the sakeof simplicity in laterexplanation,$ anintegerpair is

"encodedinto oneinteger.

When@

we say that we assignthe via vertex to somelayer ,6we& meanthat will& be decodedback into the integer pair.

1However,we canshowthat this graphcanbe usedif no stackedvias areallowed,andthe layout will not put two vias too close.

2Our definition of wire segmentis somewhatdifferent than Pinter’s. InPinter’s�

definition,wire segmentsareseparatedby “free runs,”which arealsowires.A via canbeinsertedin a “free run,” but thelocationis not determined.In our definition,wire segmentsareconnectedendto end,andvias canonlybeE

insertedin the endpointsof wire segments.

Fig. 2. (a) A given layout and(b) the correspondingECC graph.

For a -layer layer assignmentproblem,we encode to�

. It iseasyto showthatthisencodingfunction forms a one-to-onemappingbetweeninteger pairs

with& to�

integersin .An simpleexampleon theencodingfor is shownbelow

W@

e use to�

denotethe numberof possibleassignmentsthat�

can� beassigned.If is"

awire segmentvertex, .If is a via vertex that can span up to layers,

.In3

the ECC graph formulation, the continuationedgesetcontains� only via-to-segmentcontinuationedges.A continua-=tionF edgebetween

�two verticesexistsif it connectsavia vertex

and� a wire segmentvertex of the samenet (and the via andwire& segmentare adjacent).The conflict edgeset, however,contains� segment-to-segment,segment-to-via,and via-to-viaconflict� edges.A conflict= edge exists$ if the two vertices itconnects� cannotbeassignedto thesamelayer.A conflict edge

between�

the wire segmentvertex and� anothervertexis redundantand can be removedif connects� througha

continuation� edgeto a via vertex ,6 and has1

a conflict edgeto�

. This is because and� are� connectedby a continuationedge,$ the layerswhich via vertex spans must contain thelayer assignedto . Since the conflict edge puts� theconstraint� that the layer(s) which spans will not overlapwith& the layer(s)occupiedby ,6 the constraintbetween and�

is"

also implied.T-o give an examplefor our representation,let us consider

the�

layoutshownin Fig. 2(a).Wire segmentsarelabeled1–12;via� candidatesare labeled – . Note that is a stackedviaconnecting� to

�. ThecorrespondingECCgraphis shown

in"

Fig. 2(b). The solid lines are continuationedgesand thedotted�

lines areconflict edges.We assumethat wire segments7G

and12 aretoo closeto be put in the samelayer.Therefore,there�

areconflict edges ,6 ,6 and . Note thatwe didnot put an edgebetweenvertices7 and 12, as it would be aredundantconflict edgeandcanbe eliminatedbecauseof theexistence$ of the continuationedgebetweenvia vertex and�

CHANG,

AND CONG: MULTILAYER LAYER ASSIGNMENT WITH AN APPLICATION TO VIA MINIMIZA TION 611

segment vertex 12. If vertex does�

not havea conflict layerassignment� with vertex7, nor doesvertex12. We alsoassumethat�

via vertex and� are� too close to be put in the samelayer, e.g., if connects� layers and� ,6 and connects�layers and� at� the sametime, therewill not be enoughroutingspaceon layer . In this situation,we needa conflictedge$ . For the casethat they may sharesomelayersbutnot? all layers,we will still introducea conflict edgebut usethecost� function to distinguishthe differentcases(seethe detailsof# cost functions below).

In3

our algorithm,we usecostfunctionsto representthecon-cepts� of conflict andcontinuation.We shall first describehowto�

usethe cost functionsfor the via minimizationprobleminthis�

section.It is alsopossibleto definesuitablecostfunctionsto�

solvethelayerassignmentproblemsfor crosstalkanddelayminimization,which will be explainedin SectionVI.

W@

e define the cost functions for the via minimizationproblem� as follows: For each edge ,6 we associateacost� matrix ; an entry gives7 the cost forassigning� to

�layer and� to

�layer at� thesametime. The

cost� matrix will& capturethe penaltyon the conflictinglayer assignmentbetweenvertices and� . If there is aconflict� for the assignment,the entry will be ,6 otherwise,it will be zero. The conflicts may be characterizedby thespacing rule violation, overlappingof wires of differentnets,or# disconnectof wires or vias of the samenet which shouldbe�

connected.This schemeis very general;for thecaseswhentwo�

verticesconflict only on somelayers,we set the matrixentries$ correspondingto the conflict assignmentsto ,6 andthe�

remainingentriesto zero.For:

eachvertex ,6 we also associatea cost array of#size ; an element of# the array specifiesthe costsof# assigningvertex to

�layer . Clearly the costarray for a

via� canbeusedto specifywhetherstackedviasareallowedornot, how manylayerscanbe stacked,etc. For example,if nostacked viasareallowed,for eachvia vertex ,6if ,6 one if , o6 r if . We canalso� allow stackedviasup to layersandcounteachstackedvia� spanning layers

�with cost ,6 by assigningcost for

if"

, o6 r if"

.W@

e may alsoreplacethe costfunctionswith morecomplexones.# Forexample,wecanput layerconstraintsonacertainnetor# partof it suchthatit cannotbeassignedinto theseforbiddenlayers.�

Our representationcan also handlevia minimizationfor gridlessroutingwherewire segmentshavevariablewidthsand� spacingrequirementson the sameor different layers.Wesimply modeldifferentpossibleconflicts on eachlayer usingthe�

cost matricesderivedfrom the designrules.Pleasenote that the formulation of ECC graph is very

general7 andcanhandlemultilayer gridlesslayout in advancedIC and MCM designs.It accommodatesdifferent widths ofwires& and vias in the samelayer or different layers as wellas� differentwire-to-wire,wire-to-viaandvia-to-viaspacinginthe�

samelayer or differentlayers.It alsohandlesstackedviaswhen& allowedby technology.Multiway splittingwiresarealsohandledelegantlyby this formulation.

W@

e definethe cost for a layer assignment which& assignseach$ vertex into

"layer to

�be

the�

summationof all the edgecostsand via costs,which iscomputed� by

COST

Our!

goal for the layerassignmentproblemis to find a layerassignment� with& the minimum cost, i.e., COSTCOST for any .

III. OPTIMAL ALGORITHM FOR TREES

Although2

all the vertex and edge costs are defined forthe�

layer assignmentof adjacentvertices, our objective isto�

minimize the summationover all the costs of verticesand� edges.It is possiblethat greedylocal changesof layerassignments� may restrict the assignmentsof remotevertices.A simple-mindedlocal refinementalgorithm,which doesnothave1

a global view of the problem,may producepoor results.W@

e would like to find an efficient algorithm which can takeadvantage� of the locality of the cost computationand alsoprovide� an efficient way to computethe impactson the totalcost� whena local optimizationof layer assignmentis made.

Becausethe multilayer layer assignmentis NP-hard,we donot expectto find an algorithm which can solve the generalproblem� optimally. A special case,however,can be solvedoptimally:# if an ECC graph is a tree, we can employeethedynamic�

programmingparadigmto form an algorithm whichoptimally# solves the multilayer layer assignmentproblemin linear time. Furthermore,we can apply this algorithmto�

a large portion of the entire ECC graph with a slightmodification� of the algorithm. This enablesus to form anef$ ficient heuristicalgorithm which can refine a large portionof# the layoutoptimally, thus,providinga moreglobalview onthe�

optimizationproblemandhavinga betterchanceto avoidbad�

local decisionsand obtain bettersolutions.Beforewe proposethe optimal layer assignmentalgorithm

for%

trees,we needto definesomenotations.For a vertex inthe�

tree,we definech= to�

be the setof the child verticesof. For a layerassignment on# a tree,we definethecostfor a

layer assignment on# a subtreerootedat as� COST

chH COST . Thiscost� containsthreeparts:the layer assignmentcost for ,6 theedge$ costsof edgesbetween and� its children,andthe costsof# subtreesrootedat the childrenof . When is the root ofthe�

tree, COST computed� by the abovedefinition is thesame as COST defined

�in the previoussection.We define

MCI

COST ; i.e., it gives theminimum� cost for the subtreerootedat underJ the conditionthat�

is assignedto layer . Note thatMC for a leaf vertexis simply . For a nonleafvertex ,6 it canbe computed

as� follows:

MC COST (1)/

chHCOST (2)

/

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IEEE TRANSACTIONS ON COMPUTER-AIDEDDESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,VOL. 18, NO. 5, MAY 1999

Fig.8

3. K -layer layer assignmentfor trees ( L -LAT) algorithm.

chHCOST (3)

/

chHCOST

(4)/

chH(5)/

The deductionfrom (1) to (2) is basedon definitions ofCOST . In (2), becausethe layer assignmentof is fixed,the�

layer assignmentsfor its childrenareindependentof eachother,# andcanbe optimizedindependently.Therefore,we cantransform�

the minimization of the summationover severalindependentterms into a summationover the minimizationof# each term, which leads to (3). In (4), we itemize theminimization over all possiblevaluesof . After pulling outthe�

constantterm and� applying the definition ofMCI

,6 we get (5).The aboveequationsshow how to computethe MC re-

cursively� from the layer cost array ,6 the edgecost matrixand� the MC

Iof# eachchild of# . Clearly, to compute

the�

MCI

,6 we only needto minimize the summationof thecost� of a subtreerootedat and� the edgecostbetween and�

for%

eachchild of# .Basedon this formula, our algorithm consistsa bottom-

upJ cost computationand a top-down layer assignment.Forthe�

bottom-upcost computation,we needto makesure thatwhen& MC

Iis"

beingcomputed,for eachchild of# MCI

has1

been�

computed.To satisfythis condition,we chooseto usethepostorder� traversalof the tree(otherordersarealsopossible).

DuringM

the bottom-up cost computation,we also use anauxiliary� array on# eachvertex to

�storethe optimal layer

assignments� for all thepossiblelayerassignmentsof theparentof# . Whena minimum costMC of# vertex is found, weset to

�,6 where is the correspondinglayer number

of# which& gives MCI

the�

minimum cost.After2

the cost array MCI

is"

computedfor the root , w6 eknow the minimum cost for the whole treeandthe bestlayerassignment� of by

�checkingtheminimumcostin MC . For a

nonrootvertex ,6 when its parent’soptimal layer assignmentis"

known,we know to what layervertex should beassignedin"

order to give the minimum costbecausewe haverecordedthis�

informationin the array.� Clearly,we cancomputetheoptimal# layer assignmentof eachvertex in the treeby a top-down�

traversalwhich simply assignslayers to�

vertexif the parentis known to be assignedto layer .

W@

e summarizeour optimal layer assignmentalgorithm inFig. 3.

TheorN

em1: Given;

an ECC graph which&is"

a tree, the -LAT algorithm finds an optimal -layerassignment� in .

Proof: The optimality follows by induction. First, it istrivial�

to seethat thesubtreecostsat the leavesareminimum.For:

theinductionpart,we canseethatour algorithmcomputesMCI

by�

(5), which only requiresto know MCI

for%

ch= ;since the cost array MC

Ifor%

eachchild of# is"

optimallycomputed� by the induction hypothesis,we know that MCis also optimally computed.Therefore,we can concludethatthe�

MC is optimally computedby the -LAT algorithm.Becausethe top-downlayer assignmentwill realizethe layerassignment� for the optimal cost, it gives us an optimal layerassignment� of the tree.

CHANG,

AND CONG: MULTILAYER LAYER ASSIGNMENT WITH AN APPLICATION TO VIA MINIMIZA TION 613

For:

the complexity of this algorithm, we first discussthenumber of possible layers per� vertex . For a wiresegment vertex, . For a via vertex ,6 the number

depends�

on how many layersthe via can be stacked.Inthe�

most restrictedcase,vias can connectonly two adjacentlayers, . For the least restrictedcase,therecan� be possible� layer assignmentsfor the viavertex.�

For Step 1, each edge requiresexaminingedge$ costs for the computationof MC

I. Since the number

of# edgesin the tree is ,6 the complexity of Step1 isfor the most restrictedcaseand for the

leastrestrictedcase.Step2 takes for themostrestrictedcase� and for

%the leastrestrictedcase,andStep3 takes

time.�

So, this algorithm runs in for themost� restrictedcaseand for

%the least restricted

case.� Since is"

anintegerconstantin our algorithm,we havelinear time algorithmfor optimal layerassignmentfor

trees.�

In practices, to�

for modernIC’s, andis usuallyless�

thanten for mostPCB/MCM designs.

IV.3

AN� ED

FFICIENT8 H

'EURISTICO

FOR G;

ENERALO G

;RAPHS9

In general,the formulatedECCgraphof a layerassignmentproblem� may not be a tree. In this section, we shall firstshow that the -LAT algorithmis alsoapplicableto inducedsubtrees in a generalECC graph. Then we shall use it asthe�

basisfor our heuristicalgorithmto optimizea sequenceofinducedsubtreesin a generalECCgraph.Let usfirst introducethe�

conceptof inducedsubtrees.DefinitionP

1: A2

subgraph is"

a (vertex)Q

inducedR

subgraphof# if,"

and only if,and� ,6 and . When aninduced"

subgraphof is"

a tree,it is calledaninducedsubtree.Definition2: Given

;an ECC graph and� a layer assign-

ment ,6 thelayerassignmentproblemfor aninducedsubgraphis to find a layerassignment s.t.

,6 and COST is"

minimum.If we choosea subset of# the verticesin the ECC graphand� fix the layer assignmentsfor the verticesoutsideof ,6

the�

original layer assignmentproblemis reducedto the layerassignment� for . Since we need to considerall the edgesamong� verticesin which& are originally in ,6 we needtoconsider� the subgraphinducedby . To utilize our optimalalgorithm� -LAT, we are interestedin an inducedsubgraphwhich& is a tree.

A. Extensionof the -LAT Algorithmto InducedSubtrees

The extensionof the optimal -LAT algorithmfor treestoinduced"

subtreesis quite simple.For a vertex in"

an inducedsubtree, we only needto increasethe layer costsof by

�the

edge$ costs between and� its adjacentnontreevertices, sothat�

the layer costsfor eachtree vertex will also include thecosts� dueto its relationswith its nontreeneighbors.After suchmodificationof the vertex cost arrays,we can apply the -LAT algorithm directly. Our optimal algorithm for inducedsubtrees can be summarizedin Fig. 4.

Fig. 4. S -LATI algorithm.

Because -LAT is optimal, -layer layer assignmentforinduced"

trees( -LATI) is alsooptimal.Wehavethefollowingcorollary:�

Corollary 1: Given;

anECCgraph ,6 a feasibleassignment,6 and an inducedsubtree of# ,6 the -LATI

algorithm� finds a minimum cost layer assignmentof in"

CUT time,�

wherethe CUTis the setof edgesconnecting and� .PrT

oof: The-

optimality follows becausewe have intro-duced�

thecostsof theedgesto thenontreeverticesin thecostarray� for each tree vertex, and because -LAT is optimal.The time complexity of -LATI is derivedas follows. Step1 takes CUT for

%the most restricted

case� on stackedvias and CUT for theleast�

restrictedcase,as we only needto visit every edgeinCUT once# andeachvisit requires operations.#Step�

2 takes time�

asshownin Theorem1. Therefore,-LATI runsin CUT time.

�T-o illustratethe -LATI algorithm,we usethe examplein

Fig.:

5(f), which showsthe ECC graphof the layout showninFig. 2(a).Thegreynodesform aninducedsubtree.We assumethe�

numberof layers is four and stackedvias are allowed.Suppose�

vertex1 is the root, thenthe setare� the leaf verticeswith no children.Let us focuson a smallsubtree rootedat vertex9. It hastwo children,vertex11 andvertex� . Vertex has

1two children, vertex 4 and vertex 10.

VU

ertex9 hasa nontreeneighbor12 in thegraphandvertex11hasa nontreeneighbor in the graph.So the layer costarrayfor%

vertex9 is after� weaddthecostsof theedges$ to nontreevertices,becausevertex12 is in layer 3 andconflicts� with vertex9. Similarly, thelayercostarrayfor vertex11 is ,6 becausevertex is in layerand� is connectedto vertex11 by a continuationedge.Now webegin�

the bottom-upcost computation.Since vertices4, 10,11 areleaf vertices,their subtreecostsareequalto their layercost� arrays.So MC

IMCI

,6and� MC . Now we computethe cost forvertex� . Assumethat thecostfor a stackedvia is theheightitspans, andrecall thatwe encodethe layerpair for a via vertexin"

the following sequence:. The layer cost array for via

vertex� is"

. Becausewe canalways� assignthelayersfor vertices4 and10 to bethesameas

and� thecostsfor subtreesrootedat 4 and10 areall zero,theMC is thesameas MC .The-

correspondingassignmentarrays for vertices 4 and

614�

IEEE TRANSACTIONS ON COMPUTER-AIDEDDESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,VOL. 18, NO. 5, MAY 1999

Fig. 5. Example of finding a maximal induced subtree VXWZY\[^]`_badcfe .

10 are: and�. Note that can� beeither1 or 2

as� eitherlayers1 or 2 for vertex4 givesthe samecostfor thesubtree rootedat . Whenthereareseverallayer assignmentsfor a vertexwith the sameminimum cost,we simply pick theone# with a smallerlayernumber.This is why . Nowwe& cancomputethe costof the subtreerootedat vertex9. Ifwe& assignvertex9 to layer 1, the minimum sum of MC

I

and� is"

zero with or# . So we have. The minimum sum of MC and� is

zero with . We add thesetwo minimum coststoand� get MC

I. The computationof the minimum

cost� of assigningvertex9 to otherlayersis similar.Eventually,we& will get MC ,6 and

.Given;

the above optimal layer assignmentalgorithm -LATI, our algorithmfinds a sequenceof inducedsubtreesandapplies� -LATI algorithm to them one by one. In order totake�

advantageof the -LATI algorithm, we needto find asequence of large inducedsubtrees.

B.g

Finding Maximal InducedSubtreesIn3

general, we are interestedin forming large inducedsubtrees. However,findinganinducedsubtreeof themaximumsize is NP-hard[18]. In addition,we wish to find a seth of# large

CHANG,

AND CONG: MULTILAYER LAYER ASSIGNMENT WITH AN APPLICATION TO VIA MINIMIZA TION 615

Fig. 6. FMIST algorithm.

inducedsubtreesto coverthe graph,ratherthana singlelargetree.�

For our purpose,we find that growing maximal inducedsubtrees (i.e., inducedsubtreeswhich arenot containedin anyinducedsubtrees)from different startingverticesis effective.On!

average,themaximalinducedsubtreescover12%–34%ofthe�

ECC graph.Our!

induced-subtree-findingalgorithm startswith an arbi-trary�

vertex and� finds a maximal induced subtreerootedat . It is basicallya graphtraversalalgorithm

with& proper labeling. Each vertex in"

the graph is initiallylabeledwith label

*. We maintain a queue for the

vertices� which are adjacentto some vertex in the inducedsubtree underJ construction.Initially, is

"empty.We choose

a� vertex as� theroot, labelit with one,andaddit to . Onceavertex� is addedto ,6 we increasethelabelof all its neighborsby�

one.Oncea vertexhaslabel 1 after the label increase,weput� it into . Thenwe extracttheverticesfrom one# by one.If the extractedvertex hasa label larger thanone,we knowthat�

is"

aneighborfor two or moreverticesin . In thiscase,vertex� is discardedbecauseif we add it to ,6 we wouldcreate� cycle(s)in . If label

*,6 we know hasexactly

one# connectionto . In this case,we add to�

,6 increasethelabels�

of ’s neighborsby one,andinsertanyof its neighborswith& label 1 into . We repeatthis processto extractanothervertex� from again,� andstop when is empty.

W@

e summarizeour algorithm for finding maximal inducedsubtrees in Fig. 6.

Fig. 5 shows how this marking process in the findingmaximalinducedsubtrees(FMIST) algorithmworks.Thegreynodes? aretheverticeswe put in the inducedsubtree,theblacknodesare the nontreenodeswith labels larger than one,andthe�

hashnodesare the nodescurrently labeledas one. Notethat�

in Fig. 5(c), when both the vertices7 and 2 are addedto�

,6 the label of vertex increasestwice andbecomestwo,which& makesit a nontreevertex.Similarly, and� 12 becomenontree? verticeswhen eight is addedto .

TheorN

em2: Given;

an ECC graph ,6 the FMISTalgorithm� computesa maximal inducedsubtreein"

CUT time.�

Proof: W@

e provethecorrectnessby induction.It is trivialthat�

a single vertex in the graph is an induced subtree.Assume is an inducedsubtree.Whenwe adda� vertex to

�,6 the labeling processguaranteesthat there

is"

exactlyonevertex in with& an edgeto . Therefore,theinducedsubgraphgeneratedby is both connectedand� without cycles,thus,it is still a tree.Whenthe algorithmstops, we cannotaddin any othervertexin the graphwithoutforming%

a cycle.Therefore,the subtreefound is maximal.Forthe�

time complexity,we needto traverseeachtreeedgetwiceand� the edgein the cut set CUT once.# The runtime�

is CUT .

C. An EfficientAlgorithm for Layer Assignment

Nowi

we are ready to presentour heuristic algorithm forthe�

generallayer assignmentproblem.Given a feasiblelayerassignment� solution with& the ECC graph, we refine to

�minimize� the layer assignmentcost through severalpasses.In3

each pass,we cover with& a set of maximal inducedsubtrees computedby theFMIST algorithm,andapply the -LATI algorithmto get the optimal layer assignmentfor thesemaximal� inducedsubtreesoneby one.If the costreductioninthe�

currentpassis larger than a specifiedstoppingthreshold,6 we startanotherpass.Otherwise,we stopthe program.The

algorithm� is summarizedin Fig. 7.Pleasenote that each vertex will appearin at least one

induced subtreein each pass.Although we start from anunmarkedJ vertex to grow an inducedsubtreeat each time,the�

inducedsubtreemight also contain a vertex which waspart� of anotherinducedsubtree.The run time of the -LAGis CUT ,6 whereis numberof passesand is the set of subtreesfound ineach$ pass.In practice,we observedthat is

"usuallya small

number? less than ten.In3

our implementation,our schedulerrandomlyselectsanunmarkedJ vertex as the root of an induced subtree.Otherheuristicsmay also be used.

V.U

EXPERIMENTAL RESULTS

The-

experimentsareconductedon a SUN SPARC ULTRA-2(168j

MHz) work station with 256 megabytesof memory.W@

e testedour algorithmswith the following testcases:testF 1,testF 2, testF 3,

kmccl 1, mccl 2, fract

>,6 andstructh . The routing results

of# testF 1, testF 2,j

testF 3,k

mccl 1 and mccl 2j

are generatedby theV4RU

router [1]. Test casestestF 1, testF 2,j

testF 3,k

and mccl 1 areroutedin four layers;mccl 2 is in six layers.Test casesmccl 1and� mccl 2 are industrial MCM designsprovided by MCC[also availableat the CollaborativeBenchmarkingLaboratory(CBL)]./

In particular, mccl 2 is a supercomputerwith 37 ICchips.� For further information on theseV4R test examples,please� refer to [1]. The testcasesfract

>and� structh are� standard

cell� designsalso availableat CBL. The layoutsof fract>

and�structh are� gridlesslayoutsroutedby an industrialrouterusingthree�

routing layers.They areroutedwith 0.6-, 0.6-, and1.2-umJ minimum widths and 0.8-, 0.8-, and 1.2-um minimumspacings on METAL1, METAL2, andMETAL3 respectively.Theroutingareafor fract

>is 181.4um 183.3um andthearea

for structh is 638.3 um 599.6m

um.It is forbidden to drop vias on the terminal locations in

fract>

and� structh . Stackedvias are not allowed exceptfor thedistribution�

vias in theV4R testcases,in which they areusedto�

bring the terminalsto their properrouting layers.

616�

IEEE TRANSACTIONS ON COMPUTER-AIDEDDESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,VOL. 18, NO. 5, MAY 1999

Fig.8

7. n -layer layer assignmentfor ECC graph ( o -LAG) algorithm.

Tp

ABLE IEO

XPERIMENTq

AL R9

ESULr

TS OF s -LAG ALGORITHMt (WITH

u Dv

EFr

AULT P�

ARAMETERw SETTING

r )

A. Impactsof MultiLayer Via Minimization

TableI shows the experimentalresults of the test casesby�

-LAG algorithm. Theseexperimentsare donewith thedefault�

parametersettingswhich will be explainedlater.EachD

entry in the tableis the averageof ten experimentsofthe�

samedataandparameters.The nondeterministicnatureofthe�

programcomesfrom randomselectionof startingverticesfor%

growing induced subtreesand random tie-breaking forchoosing� verticesto beaddedto theinducedsubtree.Althoughwe& couldeasilymaketheprogramdeterministic,we foundthatrandomization) usuallyimprovesrun time andsolutionquality.

Some�

columns in TableI may need further explanations.The third column showsthe numberof vias in the originallayout�

beforewe apply the -LAG algorithm. For the V4Rtest�

cases,we countall theviason therouting layers.3x

For thetest�

casesfract>

and� structh ,6 which arestandardcell designs,wecount� all the vias of the interconnectsamongcells,but we donot? count vias inside any cell. The fourth column showsthetotal�

numberof verticesin the ECC graphfor eachtestcase.Thefifth columnshowsthe total numberof edgesin the ECCgraph.7 The sixth column showsthe averagetotal numberofmaximal inducedsubtreesconstructedin eachrun of -LAGalgorithm.� The seventhcolumnshowsthe averagenumberofvertices� in a maximalinducedsubtree;theaverageis takenon

3yThep

via numbersshownhereare different from thosereportedin [1]. InV4R,z

thedistributionviascanbestackedto bring theinput–outputpinson thesurfaceto anyroutinglayer.Eachdistributionvia is countedasone,no matterwhetherit is stackedor not. Also, due to an oversight,the distribution viasin{

a multiterminal net are over-counted[19] (as eachmultiterminal net wasbrokenE

asa setof independenttwo-terminal-nets).In our via countingrouting,we count eachdistribution via by the numberof layers it spansexcludingthe|

surfacelayer. Moreover,we correctedthe via over-countingproblemformultiterminalnets.The samevia countingprocedureis usedto reportthe vianumbers} in all the tables.

all� the subtreesgeneratedin all runs.In the samecolumn,thenumbers? in theparenthesesaretheratio of theaveragenumberof# verticesin themaximalinducedsubtreesto thetotal numberof# verticesin the ECC graph.The eighth column showsthenumberof vias reducedand the ratio of via reductionto thetotal�

numberof vias.The-

averagesize of maximal induced subtreesshown inTableI is from 12% to 34% of the total numberof vertices.This-

indicatesthatour algorithmcanoptimally refinethelayerassignment� of a large portion of the entiregraphon eachrunof# -LATI algorithm,which leadsto highly optimizedlayerassignment� solutions.

The resultsfrom fract>

and� structh are� modestcomparedtothe�

resultsfrom theV4R testcases.Fract~

and� structh are� routedin three layers using an industrial router, and no vias areallowed� in terminallocations;this leaveslittle opportunityforimprovement"

throughlayer assignment.This industrial routerhas also beenintegratedwith somepost-layoutoptimizationprocedures� for via minimization. The via reduction in theV4RU

testcasesarefrom 12.6%to 15.1%.This is a significantreductionsinceV4R is a router known to havelow usageofvias.� The V4R testcasesareroutedin four or six layers;viasare� also allowed in thoseterminal locations.As a result, wehave1

considerablefreedomto do thevia minimizationin thesetest�

cases,andobtain muchbettervia reductions.

B. Algorithm Options

Our!

-LAG algorithm for multilayer gridlesslayoutshasseveral options. We shall explain theseoptions here. Theirimpactsto solutionquality and run time will be evaluatedinSections�

V-C to V-E.1) Wire Segmentation:W

@e assumethe input layouts of

our# programare given as collectionsof wire segmentsand

CHANG,

AND CONG: MULTILAYER LAYER ASSIGNMENT WITH AN APPLICATION TO VIA MINIMIZA TION 617

TABLE IIEO

FFECTS�

ON W�

IRE� SEGMENT

rATION

vias.� Our programhas an option to further break eachlongwire& segmentinto a set of smaller wire segmentsand viacandidates.� The breakingpoints are chosenfrom the middlepoints� betweenlocations where this wire segmentcrossesother# wire segments.Furthermore,only thosemiddle pointsof# segmentswhich are longer than a certain length will&be�

consideredas breaking points. The length is"

usuallydetermined�

by theminimumspacerequiredby designrule fora� via insertion.However,we canspecifysomelarger numberto�

reducethe numberof breakingpoints.Let�

us consider the wire segment in"

Fig. 1 toillustratehow to do the wire segmentation.The wire segment

crosses� otherwire segmentsat points,6 and . Assumethe lengthsof wire segments

,6 and are� all smaller than ,6 thus,they�

will not be broken.Becausethe length of wire segmentis larger than ,6 we havea breakingpoint ,6 which

is"

themiddlepoint of . In this case, is"

brokento�

and� .Our!

programcanalsorestrictthenumberof breakingpointsto�

be lessor equalto by�

iteratingthroughall feasiblebreaking�

pointsandselectingonly oneout of every of#them,�

where is"

anuser-specifiednumberand is"

thenumberof# verticesof the ECC graph.This givesus somecontrolsonthe�

degreeof wire segmentation.2)�

InducedSubtreeGrowingStrategies: DuringM

the run-ning of FMIST algorithmto grow a maximalinducedsubtree,there�

are usually more than one vertex which can be addedto�

the inducedsubtreeat the sametime. Choosingdifferentvertices� may endup with differentmaximal inducedsubtrees.Since�

different maximal inducedsubtreesmay give differentvia� reductions,we experimentedwith different strategiestogrow7 maximal inducedsubtrees.

Recall�

the procedureFMIST, which grows a maximalinducedsubtree(describedin SectionIV-B). It usesa queueto�

storetheverticeswhich areadjacentto the inducedsubtree.It3

repeatedlyextractsa vertex from the queueto determineif it can be addedto the induced subtree.When insertinga� vertex to

�the inducedsubtree,it increasesthe labels of

all� the neighborsof by�

one. If there are someneighborsof# with& label 1 after the increments,it insertsthem to thequeue.� Becausewe extractandchecktheverticesof thequeuein a first-in-first-out order, the order of insertionsdeterminesthe�

order of vertices being added to the induced subtree.W@

e have the following two strategiesto decidethe order ofinsertions."

Strategy�

A: When@

adding vertex to�

the inducedsub-tree,�

we first insertneighborverticeswhich areconnectedto

by�

continuationedges,thenthe verticesconnectedby conflictedges.$

Strategy�

B: W@

e first separatethe neighborverticesthatneedto be addedinto the queueinto two groups.The firstgroup7 consistsof the verticeswhich havenot beenincludedin any maximal inducedtree in the currentpass.The secondgroup7 consistsof the rest.The verticesin the first groupwillbe�

addedbeforethe secondgroup.We then usethe orderingin"

StrategyA to determinethe orderingin both groups.The-

reasonthat we want to use StrategyA to grow theinducedsubtreeis that we wish to give somepreferencetothe�

continuationedgesbecausevia reductioncanonly happenin"

reassigningverticesconnectedby the edges.The reasonwhy& we have StrategyB is that we want to avoid growingsubtrees which aresimilar (havinga lots of verticesandedgesin"

common)to other inducedsubtreesgeneratedbefore.In both strategies,there may be vertices with the same

priority.� Our programrandomlybreakties, and this explainswhy& multiple runsof our programmay give differentresults.

If3

wire segmentationis applied,we will grow the inducedsubtree usingtheoriginal wire segments,andthenbreakwiresaccording� to the wire segmentation.

3)�

StoppingThresholds: Our!

program usually obtainsmostof the improvementsfrom thefirst few maximalinducedsubtrees. The reductionin later passesalso tendsto be small.Our!

programhas an option to stop earlier when it seestheimprovementin onepassis lessthanan adjustablefraction ofthe�

total numberof vias (thedefaultvalueis setto 0.5%).Wecall� this option “quick stopping.”

C. Impactsof Wire Segmentation

T-ableII showsthe effectson wire segmentation.4 The

-data

are� obtainedby using tree growing StrategyB and no quickstopping. All the numbersin this tableare the averageof tenexperiments$ of the samesetting.

W@

e have three setsof experimentson the samedata: nosegmentation, mediumsegmentation,and maximumsegmen-tation.�

In the maximumsegmentation,we useall the possiblebreaking�

points defined in the subsectionV-B.1 to breakthe�

wires (exceptfor mccl 2, which would require more than300k

megabytesof memory to do so. To limit the numberof# breakingpoints in mccl 2,

jwe have doubledthe minimum

length required to break a wire segment.)In the mediumsegmentation, we limit the number of breaking points toroughly) thesameastheoriginalnumberof verticesin theECC

4W�

e do not includetestcasesfract�

andstruct� in TableI becausetherearenot} manylong wire segmentsto be brokenin thesetwo testcases.

618�

IEEE TRANSACTIONS ON COMPUTER-AIDEDDESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,VOL. 18, NO. 5, MAY 1999

TABLE IIIEO

FFECTS�

ON Dv

IFFERENT� SUBTREE

� GROWING� STRA

�TEGIES (WITH

� QUICK� ST

�OPPING)

TABLE IVEO

FFECTS�

ON Dv

IFFERENT� SUBTREE

� GROWING� STRA

�TEGIES (WITHOUT

� QUICK� ST

�OPPING)

Tp

ABLE VEO

FFECTSON QUICK� STOPPING (WITH

� STRATEGY B)

graph,7 thus, limiting the incrementof the numberof verticesto�

roughly threetimes the original size.This-

experimentshowsthat doing segmentationis alwayshelpful to getbettervia reduction,but at thecostof generatinglar�

gerECCgraphs,which meanshighermemoryrequirementsand� longer run times. In most of the examples,the improve-mentby maximumsegmentationis lessthan0.7%of the totalvias,� while the run time increasesby six to 29 times.We haveobserved# similar resultsby usingdifferentcombinationsof treegrowing7 strategiesand stoppingthresholds.

D. Impactsof Different SubtreeGrowing Strategies

T-ablesIII andIV showtheeffectson differenttreegrowing

strategies with differentstoppingthresholds.No wire segmen-tations�

areusedto obtainthesedata.Thecolumn“# of subtreesof# size %”

�is to showthe total numberof subtreeswhich

is larger than20% of the total numberof verticesof the ECCgraph.7 Again, all the numbersin the tablesare the averageover# ten experiments.

TablesIII and IV show that the differenceon the solutionquality� is not significantwhenapplyingdifferentstrategies(allwithin& 0.2% of total numberof vias). The differenceon runtime�

is caseby case.In mostof the testcases,the differencesare� within 1.5 times. However, the run time may have bigdif�

ferencesin sometestcases.In testcasestructh ,6 the run timeof# StrategyA is 17 timeslarger thanthe run time StrategyB.In this case,both thenumberof subtreesperpassandaveragesubtree sizesare reducedby using StrategyB. Sincethereisstill considerableamountof “large” subtrees(subtreeslargerthan�

20%of theECCgraph)generatedin this case,we do notsee much impact on the solution quality.

E.�

Impactsof Different StoppingThresholds

T-ableV showsthedataondifferentstoppingthresholdswith

Strategy�

B andno segmentation.Theresultson StrategyA arequite� similar, so we do not show them. If quick stoppingisused,J theprogramwill stopwhenthevia reductionin onepass

CHANG,

AND CONG: MULTILAYER LAYER ASSIGNMENT WITH AN APPLICATION TO VIA MINIMIZA TION 619

is"

less than 0.5% of total numberof vias. Our experimentaldata�

show that the programstops roughly at two passesinevery$ testcasewhenquick stoppingis used.If quick stoppingis not used, the programmay require more passesto stop.For example,on average,it requiresas many as 6.9 passesin mcc2l . The sacrificeon the solutionquality by usingquickstopping is almostnegligible(all within 0.2%comparedto thetotal�

numberof vias).However,the improvementon run timemay up to a factor of three.

F. RecommendedParameterSettings

In conclusion,whentherun time andmemoryusageis con-cerned� anda slight sacrificeon solutionquality is acceptable,we& recommendrunning our program without segmentation,but�

using quick stoppingand using StrategyB to grow theinducedsubtree.In fact, this is the default parametersettingof# our program(The resultsin Table I areobtainedunderthisparameter� setting). If we wish to maximize via reductionatany� cost, maximum segmentationshould be used,and bothStrategy�

A andStrategyB shouldbetried.Theprogramshouldbe�

run repeatedlyand the bestresult selected.

VI.U

LAYER ASSIGNMENT FOR DELAYS

AND� C

.ROSST9

ALK M+

INIMIZA�

TION

As we mentionedin the previoussections,the ECC graphis"

a very generalmodel of the layer assignmentproblem.W@

ith properdefinitionsof costfunctions,our layerassignmentalgorithm� can also be used to further reducecrosstalkanddelay�

after routing.In fact, our algorithmwill work on any costfunction on an

ECC graphwith the following properties.

1) The costsaredistributedon verticesandedges,andthetotal�

cost is the summationof weightedcostsover allvertices� and edges.

2) The cost of a vertex is determinedonly by its layerassignment.�

3)k

The cost of an edge is determinedonly by the layerassignment� of the two verticesit connects.

For the layer assignmentproblemin VLSI layout, we canalways� representthe penaltiesfor conflict and discontinuityby�

a cost matrix for eachedge.We assumethat we havethecost� matrix as� definedpreviouslyto representsuchpenalties.� All we needis to addextracost functionsto modelthe�

problemwe want to solve.For the crosstalkminimization problem,we could add in

the�

crosstalkpenalty for wire segmentspairs with crosstalkconcern.� Assumingthat for eachpair of wire segmentsin"

which we needto considercrosstalk,thereis a preallocatedslack CB on# the amountof crosstalkallowed for that pairof# wire segments.Let us denoteCSK as� the crosstalkbetween�

and� when& they are assignedto layer and�respectively.We candefineour cost for crosstalkas

CM

CSK CB if"

CSK CBMAXI

otherwise#

where& is"

a preassignedweightingcoefficient.

This-

functionmakesanyassignmentwith crosstalkexceed-ing"

theallocatedslackto havea largepenaltycost.Otherwise,the�

costis just the differencebetweenthe actualcrosstalkandallocated� slack times the correspondingcoefficient constant.The-

weight coefficient allows� us to put priority ondif�

ferent pairs accordingto their importance.The-

costfor vertices and� to�

be assignedto layers and�is CM . Thereis no vertexcost for this

problem� if only crosstalkminimization is considered,andtheoptimization# objectivebecomesto minimize the total costonall� the edges.If we want to optimizeboth vias andcrosstalk,these�

objectivesmay conflict eachother. However, we canincludeeachvertexcostwith a suitableweight,andminimizethe�

weightedsumof thecostson all verticesandedgesto findthe�

tradeoffs betweentheseobjectives.W@

ecanalsoapplythis layerassignmentformulationto delayoptimization.# In VLSI layout, wires routedin different layersmay havedifferentwidths, spacingsandRC constants,so thedelay�

of awire maybedifferentwhenit is assignedto differentlayers.�

Assumethatwe havea delayboundDBP

for%

eachwiresegment and� thedelayfor on# layer is

". Wecandefine

cost� DA as� the costof eachsegmentvertex as� follows:

DAP DB

Pif"

MAXI

otherwise#

where& is a preassignedweightingcoefficient to adjustthepriority� of minimization delay on vertex .

The-

costfunctiongivesthemaximumvalueif thedelayex-ceeds� the delayboundallocated,otherwiseit is the differencebetween�

thedelayandthedelayboundtimesthecorrespondingcoef� ficient constant.Thetotal costis thesumof thecostsoverall� vertices(DA

Parrays)� and edges( matrices).�

Given;

thesedefinitionsof cost functions,we canapply the-LAG algorithm to solve the multilayer layer assignment

problem� with optimization objectivesas weightedcombina-tions�

of via, crosstalk,and delay minimization.

VII.U

CONCLUSION

W@

e have introduced the notation of an ECC graph torepresent) the layer assignmentproblemin multilayer gridlesslayout. We showedhow to use the ECC graph to representthe�

layer assignmentproblemfor via minimization,crosstalkminimization, and delay minimization.

W@

e havepresenteda linear time optimal layer assignmentalgorithm� -LAT that solvesthe casewhenan ECC graphisa� tree. After a slight modificationon the -LAT algorithm,we& obtainedthe -LATI algorithm which optimally solvesthe�

layer assignmentproblem for induced subtreesin anECC graph. Our -LAG algorithm is an efficient heuristicalgorithm� for the layer assignmentfor a generalECC graph.The-

-LAG algorithm utilizes the -LATI algorithm asthe�

optimization engine and can handle very large designsef$ ficiently, with very goodsolutions.Our experimentalresultsshow that the -LAG algorithmconsistentlyfindsmanylargeinducedsubtreesin the ECC graph,and achievessignificantvia� reductioncomparedto theresultsof theV4R router,whichis"

known to have low usageof vias.

620�

IEEE TRANSACTIONS ON COMPUTER-AIDEDDESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,VOL. 18, NO. 5, MAY 1999

A2

CKNOWLEDGMENT

The-

authors would like to thank R. Helzermanand P.Madden+

for their comments.Theywould alsolike to thankK.-Y. Khoo for providing V4R routing solutionsand test cases,and� assistancethroughoutthis research.

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Computer-AidedDesign of Integrated Circuits Syst., vol. 12, pp.273–282,Feb. 1993.

[16] K. C. ChangandH. C. Du, “Layer assignmentproblemfor three-layerrouting,”� IEEE

�Trans.Comput., vol. 37, pp. 625–632,May 1988.

[17] S.-C. Fang, K.-E. Chang,W.-S. Feng, and S.-J. Chen, “Constrainedvia minimizationwith practicalconsiderationsfor multilayerVLSI/PCBrouting problems,”in Proc. 28th ACM/IEEEDesignAutomationConf.,1991, pp. 60–65.

[18] M. R. GareyandD. S. Johnson,ComputersandIntractability: A Guideto theTheoryof NP-Completeness. New York: Freeman,1979.

[19] K. Y. Khoo, private communications,1996.[20] C.-C. Changand J. Cong, “An efficient approachto multi-layer layer

assignmentwith an application to via minimization,” in Pr�

oc. 34thACM/IEEE�

DesignAutomationConf., 1997,pp. 600–603.

Chin-Chih Chang received� theB.S.degreein com-puter� sciencefrom NationalTaiwanUniversity,Tai-wan, in 1989 and the M.S. degreein computersciencefrom the State University of New Yorkat Stony Brook in 1993. Currently, he is a Ph.D.degreestudentin theComputerScienceDepartmentof University of California, Los Angeles.

His researchinterestsinclude VLSI CAD algo-rithms on performance-drivenlayout synthesis.

Jason�

Cong (S’88–M’90–SM’96)for a photographandbiography,seep. 420of the April 1999 issueof this TRANSACTIONS

� .