8/10/2019 604RFDF4

1/3

46 www.rfdesign.com April 2006

Software Radio

High-speed ADC combines with FPGA toenable single-slot SDR solutions

The software-defined radio (SDR) concept has enabled designers to reinvigorate classicaldesigns in a compact form. One of the areas where SDR-based designs have immense

advantage is in the development of multichannel receivers. This article describes an example

implementation that can handle an FM bandwidth of 300 kHz having a 40 kHz message

bandwidth and 105 kHz FM deviation. The implementation presented easily handles a wide

range of applications including sonobuoy and tactical communication applications.

By Angsuman Rudra and Alexis Bose

High-speed analog to digital converters (ADC) and large field-programmable gate arrays (FPGA) have allowed designers to

design compact solutions that were unthinkable a few years ago.This article discusses how a 16-channel frequency modulation (FM)demodulator operating in the intermediate frequency (IF) region maybe implemented in a single slot, and builds on two articles previouslypublished inRF Design[1,2]. The system implemented here is capableof digitally tuning to 16 separate FM bands, downconverting the signalto produce complex baseband outputs and performing a multichannelFM demodulation in a FPGA core.

This article describes an example implementation that can handle anFM bandwidth of 300 kHz. This supports an FM with 40 kHz messagebandwidth and 105 kHz FM deviation. The implementation presentedhere easily handles a wide range of applications including sonobuoyand tactical communication applications. The 16-channel demodulatoris implemented in a modular fashion as two eight-channel demodulatorblocks. The eight-channel FM demodulator uses less than than 4700slices, seven 18 x 18 multipliers and 16 18 kbit random access memory(RAM) blocks found in a Xilinx FPGA[3].

Market needsClassic designs are being migrated to SDR-based implementa-

tion, and requirements for reconfigurability, space and size reductionare becoming crucial. SDR offers the most benefit in multichannelscenarios where high-speed signal-processing modules can processmultiple channels without duplication of expensive processing mod-ules. FPGAs are also playing a significant role for baseband process-ing and offer reconfigurability and space saving that is crucial for avariety of applications. This multichannel receiver can be used as, forexample, a sonobuoy receiver, a tactical communication receiver or anext-generation wireless communication receiver. The FPGA-basedimplementation allows the user to reconfigure the same hardware into

multiple profiles, resulting in significant space savings for multimodeapplications. Moreover, logistics support and spare parts inventoryare greatly reduced.

System descriptionThe entire multichannel receiver can be delivered in a single-slot

implementation with capacity to spare as shown in Figure 1. The single-slot receiver comprises two PMC modules: a high-speed ADC modulewith 16 digital downconverters (DDC) [ICS-554] and a FPGA-basedPMC module [ICS-1580]. The ICS-554 allows the user to digitize upto four IF signals and digitally tune up to 16 frequency-division mul-tiplexed (FDM) channels. The DDCs in the ICS-554 are programmedfor a decimation factor of 64, which produces a complex output datarate of 1.5625 Msamples/s at a 100 MHz ADC sampling rate. Notethat the data rate is four times higher than the Nyquist data rate of390 ksamples/s (complex) for a 300 kHz RF bandwidth. These FDMchannels (FM-modulated complex baseband signal) are then sent tothe ICS-1580 module for FM demodulation (Figure 2). For ease ofimplementation, the 16-channel FM demodulator is implemented astwo eight-channel demodulators.

The FM demodulation process can be characterized as:m(t) = d()/dt, where phi is the phase of the received signal.With a complex baseband representation (I, Q), = atan(Q/I).

Substituting this in the equation above and expanding out d(atan(Q/I)),the baseband message signal may be recovered as:

(I*dQ QdI)/(I^2 + Q^2).This is the heart of the FM demodulation function implemented in

FPGA as shown in Figure 3. The automatic scaling function ensuresthat the output of the divider is a full-scale 16-bit number. This pro-duces near full-scale baseband output for a wide range of RF signalpower, in effect implementing a digital automatic gain control (AGC)functionality. The various settings are summarized in Table 1.

Figure 1. Multichannel IF receiver in a single slot.

ADC 1

ADC 4 DDC 16

DDC 1

Dataformat

Dataformat

PCIinterface

8-ch FM

demod

8-ch FM

demod

FPGA

PMC: ICS-554 PMC: ICS-1580

To host

Figure 2. A 16-channel FM demodulator describes the system blockdiagram.

8/10/2019 604RFDF4

2/3

48 www.rfdesign.com April 2006

A detailed description of the hardware used and the variousfunctional blocks programmed in the FPGA follows.

Hardware modulesThe ICS-554 and the ICS-1580 PMC modules that enable the build

up of the system are described here. ICS-554. A four-input high-speed ADC card capable of

sampling at rates up to 105 MHz. Up to 16 onboard narrowbanddigital tuners enable users to implement a compact multichannelreceiver solution. The maximum bandwidth per channel is 2.5 MHzfor the 16 narrowband channels. Multiple channels may be combinedto provide up to four channels at 10 MHz each. The onboard DDCsallow the user to digitally downconvert the signal and reduce theeffective data rate for each channel. Digital tuning is achieved bywriting a tuning word for the numerically controlled oscillator(NCO). Digital retuning is thus an extremely fast process and enablesthe receiver to serve as a very fast frequency-hopped system. Moreinformation regarding the ICS-554 is available from[4]. ICS-1580. A PMC module with a Virtex-II Pro device

(XC2VP70). The FPGA is directly connected to 64 Mbytes ofsynchronous dynamic random access memory (SDRAM) arranged

as four independent banks and 16 Mbytes of QDR-II SRAM arrangedas four independent banks. Four multi-Gigabit Tx/Rx links fromthe FPGA are available on the front panel and enable high-speeddata movement in a multiboard scenario. This would allow multipleICS-1580s to be interconnected to increase effective FPGA resources.The 64 user I/O lines of the PMC module are also connected tothe FPGA and are used to transfer data from the ICS-554 to this module.More information regarding the ICS-554 is available from[5].

Digital phase discriminatorThis block is the heart of the FM demodulation process and is

implementing the differentiation of the phase of the received signal.The DDCs produce a complex baseband (I,Q) representation of thereceived signal. The implementation of the (I*dQ QdI)/(I^2 + Q^2)is carried out in two steps. In the first step, the numerator (I*dQ QdI)and the denominator (I^2 + Q^2) are first computed. The differentiation

function is approximated by the difference operator. Thus:dI = I(n) I(n-1) & dQ = Q(n) Q(n-1). After algebraic manipula-

tion the numerator becomes:I(n-1) * Q(n) I(n) * Q (n-1).The denominator is calculated in a straightforward fashion. The

multipliers are implemented using the 18 x 18 hardware multipli-ers available in the Xilinx FPGA. The division is performed using

a Xilinx LogiCORE divider block. The availability of dividers thatcan be easily and economically implemented in a FPGA has madepossible implementation of a much wider variety of DSP algorithmsin FPGA. A fixed point divider is implemented in this example.

The design targets a system with approximately 300 kHz RFbandwidth with about 40 kHz baseband signal bandwidth. Thus,an FM system with 105 kHz frequency deviation and 40 kHz messagebandwidth will be easily accommodated as the bandwidth of sucha system is about 290 kHz (= 2*(105+40)). The Nyquist data ratefor carrying this bandwidth is about 390 ksamples/s (complex), whichtranslates to a DDC decimation of 256 at a 100 MHz sampling rate.However, at this reduced sampling rate, the approximation of thedifferentiation reduces the distortion performance. To alleviate theproblem, a 4x oversampling ratio has been selected as compared with

the Nyquist rate.

Baseband filterThe output of the phase discriminator is the baseband message

signal (40 kHz bandwidth in this example). However, the outputdata rate is about 1.56 MHz, which is much more than required.Having a very high data rate causes an undue burden on the hostsystem, which has to transfer and process the data. To reduce thedata rate, a decimating multiply-accumulate (MAC) low-pass finiteimpulse response (FIR) filter is used. The decimation factor for theFIR is chosen to be 16, which produces a baseband data rate of97.65 kHz, sufficient to handle the message bandwidth of 40 kHz.The low-pass FIR has a passband of 42 kHz and a stopband of48 kHz. As the input data rate (1.56 Msamples/s per channel) is

significantly lower than the 100 MHz clock used in the FPGAfabric, multichannel operation is possible without consumingadditional FPGA resources.

FPGA implementation and occupancyFM systems are typically narrowband applications. This allows

multichannel implementation in relatively small FPGAs. FPGAstypically run at very high speed. In the example shown here, theFPGA was a Xilinx Virtex II Pro device (XCV2P70) running at100 MHz. The relative occupancy is shown in Table 2.

The compact design is achieved by running the FPGA at a muchhigher frequency than the input data rate. Thus, the same resources(multipliers, slices, etc.) may be used to process multiple channels.This allows the developer to implement additional functionality in thedesign. Other FPGAs are now available that run at faster clock ratesenabling more functionality to be packed in the same device.

Output Data Rate

ADC Sampling Rate 100 MHz

DDC Decimation Factor 641.5625 Msamples/s

(complex)

DDC Programmable Filter 17%

DDC RF Bandwidth 265 kHz

Digital Phase Discriminator1.5625 Msamples/s per

channel (real)

Decimating MAC FIR Filter(Decimation = 16)

97.65 ksamples/s(real) per channel

Table 1. Summary of the settings.

Ch 1

Ch 2

Ch 3

Ch 4

Ch 5

Ch 6

Ch 7

Ch 8

I*dQ - Q*dI

I2

+ Q2

16

16

I

Q

97.65 ksps/chx 8 channels

To PCI interface

1.5625Msps/ch32

2n(I*dQ - Q*dI)

2 (-m)* (I2+ Q2)

32

32

32

Decimate by 16,361-tap MAC

FIR (8-ch)

16

16

Automaticscaling

Figure 3. An eight-channel FM demodulator module implemented in FPGA.

8/10/2019 604RFDF4

3/3

50 www.rfdesign.com April 2006

Distortion reductionThe approximation dQ = Q(n) Q(n-1) causes non-linear distortion.

A simple way has been used to reduce the distortion by oversamplingas described earlier. The higher complex baseband output data ratefrom the DDCs allows greater granularity in the differentiation,reducing the distortion. Software-based floating-point implementationhas shown that 4x oversampling (as compared with the Nyquist rate)reduces the harmonic distortions by about 30 dB (compared to thecase when the outputs are at the Nyquist rate). Additional improvementsmay be obtained with a higher oversampling factor.

Performance characterizationThe test setup used to characterize the multichannel receiver

is shown in Figure 4. The FM demod data is collected and a FFT(using a flat-top window) is used to analyze the performance.Figure 5 and Figure 6 show the performance at two input levels:-10 dB and -20 dB below the full scale of the ADC input. The ADCfull-scale value is about 5 dBm. It can be seen from the plots thatthe demodulated output signal level is preserved. The estimatedSINAD for the -10 dBFS input case (Figure 5) is 28.0 dB, while thatfor the -20 dBFS input case is 23.2 dB.

ConclusionThis article describes a single-slot multichannel receiver that is

ideal for multimode SDR-based reconfigurable solutions. As anexample, a multichannel FM demodulator core has been implementedwith extremely low FPGA resource utilization demonstrating the

power of todays high-speed FPGA devices in communicationssystems.RFD

References1.RF Design, May 2004, FPGA-based Application for Software

Radio, Angsuman Rudra.2.RF Design, July 2003, Multichannel Multiband VHF Software

Radio-based Receiver Eliminates RF Downconversion, AngsumanRudra.

3. Xilinx Virtex-II Pro Data Sheet (www.xilinx.com).4. Tech Note No. 45: ICS-554 4-Channel, 105 MHz ADC PMC

Module with DDCs, Xilinx FPGA and PCI 64/66 Interface (http://www.ics-ltd.com/TechNotes.cfm).

5. Tech Note No. 54: The ICS-1580 FPGA DSP Board withHigh-Speed Inputs in PMC Format, (http://www.ics-ltd.com/Tech-Notes.cfm).

Total AvailableUsed in 8-chFM demod

Percent Used

Slices 33,088 4700 14.2%

18 x 18 Multiplier 328 7 2.1%

18 kbit Block RAM 328 16 4.9%

Table. 2 Relative occupancy.

Signal generator

Multichannel IF receiver

PCI

Demod dataanalysis (off-line)

FM at 21.4 MHz105 kHz deviation8 kHz message

Figure 4. Test setup for characterizing the system.

Figure 6. Spectrum of the demodulated signal with IF input at 20 dB fullscale (dBFS) at the ADC.

Figure 5. Spectrum of the demodulated signal with IF input at 10 dB fullscale (dBFS) at the ADC.

ABOUT THE AUTHORS

Angsuman Rudra obtained a B. Tech degree from IIT

Kharagpur in India in 1992, a Masters degree in Electronicsand Electrical Communications Engineering from CarletonUniversity in 1996, and an MBA from the University ofOttawa in 2001. Previously with Nortel, he joined ICSSensor Processing in 2001, where he is currently director,systems. He is a Professional Engineer in the state of Ontarioand a member of IEEE.

Alexis Bose holds a BASc in Systems Design Engineeringfrom the University of Waterloo. He has five years ofexperience in software and hardware systems related tocommunications, biomedical and defense. He joined ICSSensor Processing in 2003 as an FPGA systems engineer,and has worked on numerous software-defined radio andradar projects.

FFT (Flattop Window) of Demod Signal

Frequency (kHz)

Amplitud

e(dB)

0

-10

-20

-30

-40

-50

-60

-70

-800 5 10 15 20 25 30 35 40 45 50

FFT (Flattop Window) of Demod Signal

Frequency (kHz)

Amplitude(dB)

0

-10

-20

-30

-40

-50

-60

-70

-800 5 10 15 20 25 30 35 40 45 50