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Infineon 167 Interrupts

The C167CS provides 56 separate interrupt sources that may be assigned to 16 priority levels.

The C167CS uses a vectored interrupt system. Each interrupt source is controlled through a

control register that contains the interrupt request flag interrupt enable bit interrupt priority level

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167 Interrupts

System specific vector locations in the memory space are reserved for the reset, trap, and interrupt service functions

Whenever a request occurs, the CPU branches to the location that is associated with the respective interrupt source. This allows direct identification of the source that caused the request.

The only exceptions are the class B hardware traps which all share the same interrupt vector.

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167 Interrupts

The jump table is made up of the appropriate jump instructions that transfer control to the interrupt or trap service routines, which may be located anywhere within the address space. The entries of the jump table are located at the lowest address space.

Each entry occupies 2 words, except for the reset vector and the hardware trap vectors, which occupy 4 or 8 words.

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Hardware Trap Summary

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Interrupt Vectors

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Processor Status Word (PSW)

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Saving the Program Environment

IP - Instruction Pointer (same as PC)

PSW - Processor Status Word

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Interrupt Processing

An interrupt service routine should save all the registers it uses on the stack, and restore them before returning.

The more registers a routine uses, the more time is wasted with saving and restoring.

The C167CS allows switching the complete bank of CPU registers with a single instruction, so the service routine executes within its own, separate context. (Context switch)

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Interrupt Control Registers

All interrupt control registers are organized identically.

The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source, which is required during one round of prioritisation

The upper 8 bits of the respective register are reserved.

Each interrupt source has its own Interrupt control register ,xxIC , where xx stands for the mnemonic for the respective source. Example: T2IC, ADCIC etc.

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Interrupt Control Registers

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Interrupt Techniques

For input interrupts Process data in the ISR or Process data in main program :-

In ISR store data in a buffer( a single variable or an array) Set a flag Main program polls the flag periodically, processing data

when flag is set, and resetting flag

Use of "Circular Buffers" to provide optimum buffer usage.

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Interrupt Processing

For output interrupts Process data in the ISR or Process data in main program :-

In main program store data in a buffer Enable the interrupt if the interrupt is disabled In ISR output data from buffer and disable interrupt if this is

last data item.

Use of "Circular Buffers" to provide optimum buffer usage.

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Keil C166 'C' Language Extensions

Compiler allows designation of a 'C' function as an ISR:-void ISR( ) interrupt A using B

A is the vector number associated with the device causing the interrupt

using B is optional and will cause a register bank switch which can save time if many registers need to be stored and later restored. But can be slower if only a few registers need to be saved.

Note return type MUST be void

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Interrupt Service Routine

ISR and local variables local variables a created on each ISR invocation use static keyword to preserve value between ISR

invocations

Communicating with main program – use shared variables I.e. global variables. Problems!! Need mutual exclusion Could use simple variables ensuring atomic access Or simply disable interrupt during access to shared

variable.