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Project ReportPhysical Design Implementation of

Torpedo Sub-system

By

N. Achyuth

K. Pramod Kumar Reddy

Under the guidance of

Mr. Srinath B K

senior Physical Design engg.



Project Report - Revision history

Version Name Date Comments

V1.0

ii



Table of Contents

1 -Physical Design Flow.......................................................................................................................1

2 -DESIGN PLANNING......................................................................................................................2

3 -Floor-Planning..................................................................................................................................3

The goals of floor -Planning.............................................................................................................3

Power Planning.................................................................................................................................

Firs! Floor "lan # PNS $e!ails%&'ori(on!al)....................................................................................

Analysis............................................................................................................................................*

-Place+en!.......................................................................................................................................1,

DFT Se!"......................................................................................................................................11

-/loc0 Tree Syn!hesis......................................................................................................................1

-o!ing...........................................................................................................................................2

* -Design For 4anfac!ra5ili!y &DF4)............................................................................................3,

-Physical 6erifica!ion......................................................................................................................32

Design le /hec0.........................................................................................................................33

Layo! 6s Sche+a!ic......................................................................................................................3

7 -Sign off STA...................................................................................................................................3

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% " D&S'(N P)ANN'N(

n the design planning contet< floor-planning is the process of si%ing and placing hierarchical cellsand functional #loc) in a !anner hat !a)es later physical design steps !ore effective. *loor -planning in hierarchical flos provides a #asis for esti!ating the ti!ing of the top level. = ti!ing

#udget allocates the cloc) cycle ti!e to each #loc) according to the top-level ti!ing esti!ation.

=n effective floor-plan helps ensure ti!ing closure in !any ays<such as placing #loc)s to !a)ecritical paths short<preventing routing congestion that ould lead to longer paths< and eli!inatingthe need for over-the top routing for noise-sensitive #loc)s. The challenge is to create a floor-planith good area efficiency hile leaving sufficient area for routing.

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* " #loor"lanning

The (oals of floor"lanning +

1.Defining the core area 29,50@9,504.

9.(reating Ports 2Ports. Tcl4.

/.Design a floor-plan A Poer netor) of hori%ontal !etal layer such that the total R Drop !ust #e lessthan 562VDD 3 V&& 4 *or a poer Budget of /00 C.

,.Defining the Place!ent and Routing Bloc)ages.

Define core area and ' core spacing<source the verilog file i.e.<Torpedo.v after reading all !acros andstandard cells are placed outside the core area as shon in #elo figure.

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Placing the acros inside the core area i.e.<the floor-planning. During the floor-planning e haveto follo the steps and techni+ues to co!e up ith a good floor-plan

• Eept the acros hich are co!!unicating ith sa!e type of the acros close together

ith the help of fly lines<(olour #y hierarchy and data flo diagra!.

• =voided the place!ent of acros in front of ports.

• =rranged the acros to get contiguous core area .

• Reduce the narro channels #eteen the acros and provided proper place!ent.

• Placed the acros ith pins toards the core < acros spacing of 0.9 2, in &pacing4.

P,-&R P)AN +

Poer planning is very i!portant stage in physical design during hich e synthesi%e thepoer netor) in order to provide poer to all !acros and standard cells ith in given R drop i.e.56 of 2VDD3V&&4.&tudy state R drop is caused #y the resistance of the !etal ires co!prisingthe poer distri#ution netor). By reducing the voltage difference #eteen the local poer andground<study state ur drop reduces #oth the speed and noise i!!unity of the local cells and!acros.

=s vertical poer straps are fied 2!>;poer.tcl4 only e have to !odify the hori%ontal !etalsi.e. !etal;5 to achieve target ir drop of 70 !v and the poer #udget of /00!.

nitial poer plan su!!ary .r.t floor-plan fig 1

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#'RST #),,R"P)AN PNS D&TA')S +/0,R'1,NTA)2

•

etal 5 strap count :• etal 5 idth /.5

• etal 5 offset >::

• etal 5 pitch /.:>

• &tep &i%e 97.09>

&ince the actual place!ent is not done the tool uses the average poer consu!ed #yeach standard cell and !acros hich is characteri%ed in .li# for this calculation and also

#ased on the virtual place!ent it did to find the location of the standard cells.

• Placed poer hungry !acros near to the periphery.

• Reduced the stac)ing level.

• Used the !acro periphery affectively.

• "ocated hot spot and provided ith !ore than one poer straps #y adjusting the offset and

step si%e of !etal 5 layer is used.

&o !odified floor-plan is shon in #elo figure

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• The !odified floor-plan gave an R-DR'P of 71.5!v analyse;fp;rail ith the P8&

constraints of

• etal 5 strap count 5

• etal 5 idth /./

• etal 5 offset 9,,.00

•etal 5 pitch /.5>

• &tep si%e 979.9

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3DD 'R DR,P MAP

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3SS 'R DR,P MAP

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Analysis +

During the poer planning e got the floating shape and floating pin errors and are eplained#elo

#loating"shaes + During poer planning if !etal 1 VDD overlaps ith !etal5 V&& then tool ill not connect !etal1 to !etal> so that entire !etal 1 #eco!es floating . &ince it is not connected to any straps .f incase e put a via that lead to short #eteen VDD and V&& and are shon #elo

Ce too) proper offset and step si%e as !ultiples of standard cell height so that !etal 5 straps#eingg placed in #eteen the !etal 1 pre;routes . =fter that e did not got any floating shapeerrors.

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#loating"ins+

During poer planning so!e !acros not got connection to poer i.e < tool not connected its VDDor V&& ring ith !etal 5 straps through via. &ince !acro is not connected to VDD or V&& sothose are called as floating pins shon #elo.

=s shon in the figure since !etal , of !acro is overlapped ith !etal / i.e< VDD of !acro if in case tool put via that lead to short e just rearranged !acros in order to get poer connection.

B),CKA(& CR&AT',N +

During poer planning in so!e region !etal 1 rail is discontinued so during place!ent tool !ayplace standard cell over there since those cells ill not get poer connection in order to preventstandard cell place!ent over there create place!ent #loc)age as shon #elo .

#),,R 4 P)AN S5MMAR6

*loor-plan Run1 Run9

8o. of Frrors fro!verify;PG;nets

9 *loating shapes and pins 8o errors

a voltage Drop2VDD 3 V&&4 .7 79.,

8o. of standard cells ,/9:5 ,/9:5

Place!ent utili%ation >:6 >:6

8o. of ?ori%ontal &traps > 5

Cidth of ?ori%ontal &traps /.5 /./

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7 "P)AC&M&NT

Design Status before Placement

synthesis is co!piled second pass netlist is generated. Data setup is co!pleted. *loor -plancell is ready .=ll the errors related to floating shapes and floating pins should #e fied.

1ero 'nterconnect Timing Sanity Chec8

Before starting Place!ent !a)e sure that Hero interconnect delay is !ade false .To !a)e H(Delay false set .&et;%ero;interconnect;delay;!ode false.

Place!ent setup and chec)s

'C Comiler Placement #lo$

'nuts to Placement

• Gate "evel 8etlist

• &ynopsys Design (onstraints

• T"U 3 2in<!a4

• *loor -plan

• Bloc)ages

• (o!!on 'pti!i%ations 2donIt use < area or poer critical range 4

•Routing "ayers

• (ritical Range 'pti!i%ation

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,ututs of Placement

• Design ith all &tandard cells placed in core area

• Ti!ing reports after Place!ent

• "ogs

Placement Set"u and Chec8s

*i all !acros #efore place!ent .f !acros are not fied place!ent tool ill !ove !acros duringti!ing or congestion opti!i%ation. To fi the !acros the folloing co!!and

icc;shellJset;dont;touch;place!ent all;!acro;cells

chec) for place!ent Readiness

icc;shellJchec);physical;design -stage pre;place;opt

a#ove co!!and chec)s the readiness of K

• *loor -Plan

• 8etlist

• Design (onstraints

Fna#le ultiple (loc)s per register

icc;shellJset;false;path -fro! get;cloc)s (9 -to get;cloc)s (1

ith the a#ove settings ti!ing analysis considers #oth (1 and (9 uses faster cloc) for setupti!ing opti!i%ations.

D#T Setu

f your design flo includes DF&G8 *'R TF&T< the netlist ill contain &can;chains< group of

scan;registers that they are serially connected through &&' pins< and inserted during synthesis.&can;chain paths are active only during LTest;!odeM < not during L*unctional;!odeM. Registersare typically connected in alphanu!eric order during synthesis -irrelevant for D*T< #ut not opti!alfor routing.

&can chain infor!ation is given to ( co!piler using scandef file and for place;opt if e given-opti!i%e;dft the ( co!piler ill reorder the scan chain #ased on the functional opti!i%ation toreduce the routing congestion.

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P)AC&M&NT C&)

To etend flei#ility< &(=8DF* also supports reordering ith partitions across !ultiple #uc)etsa P=RTT'8 is a group of &(=8DF* chains that !ay echange flip-flops during reordering.

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P)AC&M&NT S5MMAR6

Place!ent Run1 Run9

C8&2setup Khold4 -1.:/K0.00 -1.:5K00

T8&2setup Khold4 -17>9/K0.000 -1795>K0.00

Total area of standard cells 59>9> sites 59>9:9

8o. of standard cells ,:79 ,:70>

Place!ent NUtili%ation :>.:6 :>.506

s place!ent congestion o) 'E 'E

=re all ti!ing paths fia#le forti!ingN

8' 8'

Note+ Run9 C8& and T8& are less co!pared to Run1 #ecause after first pass place!ent eused critical range to opti!i%e su#;critical paths.

Results and Analysis

'R Dro +

R drop in place!ent increases co!pared floor -plan stage. n Place!ent all high fanout netsecept cloc) netor) to #alance and to fi DR( 2Design Rule (onstraints4 and ( co!piler illresi%e so!e standard cells during opti!i%ation <#y resi%ed cells R drop increases.

=fter place!ent VDD !a R drop increased fro! ,5.> to ,:.00 and V&& !a R dropincreased fro! ,>.9 to ,:.0 .Ce have to ta)e care of the increased R drop in second iteration of PD #y decreasing accepta#le R drop .*olloing figures sho the R drop !ap of VDD and V&&.

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3DD 'R DR,P MAP

3SS 'R DR,P MAP

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C,N(&ST',N

(ongestion occurs hen the nu!#er of ires going through a region eceeds the capacity of that region. This condition is detected #y glo#al routing. = congestion !ap can help you visuali%ethe +uality of place!ent ith respect to the avoidance of routing congestion .The congestion !apshos the #orders #eteen glo#al congestion cells highlighted ith different colours that respect

different levels of overflo. The overflo values shon in congestion !ap are deter!ined #yco!#ing the overflo and underflo of all selected layers . *or Fa!ple < in #elo figure the light#lue colour highlighted on the edge of the glo#al routing cell shos 107.This !eans there are 7ire trac)s availa#le< #ut 10 trac)s are needed.

C,N(&ST',N MAP

Timing Analysis +

• During first run e got 99) violations ith !ost violations in RFG8 paths due to over

constraining of input to reg paths.• Ce have analysed so!e paths hich are false paths and reported the! to synthesis

Fngineer.

• Ce have o#served so!e paths in hich !acro delays is !ore than cloc) period and

reported the! to project !anager.

• During initial design setup e have segregated all ti!ing path to RFG8<RFG'UT and

("'(E groups for #etter opti!i%ation of su#;critical paths.

• Ce gave critical range just greater than C8& to opti!i%e all su#-critical paths and gave

another run o#served that T8& reduced.

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9 4 C),CK TR&& S6NT0&S'S

/loc0 Tree Syn!hesis is a "rocess of $is!ri5!ing cloc0 Signals !o !he cloc0 sin0 "ins of each

flo" in !he Design accor$ing !o !he infor+a!ion gi8en 5y !he Logic syn!hesis. 9" !o !his s!e" !he

cloc0 Signals are consi$ere$ as i$eal !ha! is (ero s0ew: la!ency: ncer!ain!y an$ Transi!ion !i+es. In!his s!e" !he /TS will syn!hesi(e !he cloc0 !ree 5y sing cloc0 in8er!ers or cloc0 5ffers an$ will

5alances !he s0ew an$ i! !ries !o +ini+ise !he s0ew !arge!s: la!ency an$ !ransi!ion !i+es gi8en 5y !he

s"ecifica!ions. The difference #eteen ?*8 synthesis during place!ent and (T& is that the ?*8

ill #alance the load this is not good at #alancing s)e. =nd hence cloc) netor)s are consideredideal during place!ent stage in PD flo.

CTS #),-

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CTS Secifications

Meet the buffering constraints

• ai!u! transition delay

• ai!u! load capacitance

• ai!u! fan out

Meet the cloc8 tree targets

• ai!u! s)e

• ina insertion delay

Meet all Cloc8 tree Design Rule Constraints / DRC 2

f the targets are not !et no violations are reported.

Results And Analysis+

The analysis shos the hold fiing after psyn using cloc);opt co!!and

:,R Reort before hold fi;ing

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?old C8& K -19.955

?old T8& K-19>5

8o of ?old violations K 1,9,:

:,R Reort after hod fi;ing

?old C8& K -19.097

?old T8& K-5>.50>

8o of ?old violations K /1>

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'nserting ort rotection diodes +

=ntenna FffectK During !anufacturing process in the (P 2(he!ical echanical Polishing4

ill produce high te!peratures hich ill lead long running !etal layers ill collect the chargesand discharge the! through gate of '& transistor hich can destroy the gate of the transistor this is called as =ntenna Fffect.

To avoid this e have to add port protection diodes during (T& stage using the co!!andinsert;port;protection;diodes. &o that those diodes can protect the ports fro! =ntenna Fffect.

ort rotection diodes

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S6S<C)K

SCAN<C)K

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S6S<RC)K

5ART<C)K

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(lobal Routing+

GR assigns nets to specific !etal layers and glo#al routing cells 2G cells4. GR tries to avoidcongested Gcells hile !ini!i%ing route at congestion areas. (ongestion eist if no of trac)savaila#le is less than the re+uired.

The glo#al router divides a design into glo#al routing cells. By default the idth of a glo#al

routing cell is sa!e as the height of a standard cell and is aligned ith the standard cell ros.

#'(+ ( C&))

Glo#al routing done in to phase

• The initial routing phase 2 phase 0 4< in hich the tool routes the unconnected nets and

calculate the overflo for each glo#al routing cells ith overflos

• the routing phases< in hich the tool tries to reduce congestion #y ripping up and rerouteing

nets around glo#al routing cells ith overflos.

• The si%e of GR( is e+ual to the height of the average standard cell.

Trac8 assignment+

This process assigns each net to specific trac) and lays don the actual !etal traces. tatte!pts to !a)e long< straight traces. =nd reduces no of vias. t does not follo DR( rules.

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Detailed routing+

nput channels and approi!ate routing fro! the glo#al routing phase Deter!ine the eactroute and layers for each net

,b>ecti?e+

valid routing< !ini!i%e area 2congestion4< !eet ti!ing constraints !ini!u! via< poer.

search and reair+

This step in the flo ill fies the re!aining DR( violations through !ultiple loops usingprogressively larger &-#o si%es

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R&S5)TS AND ANA)6S'S +

C),CK R,5T&

S'(NA) R,5T&

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D&TA')&D R,5T'N( C,N(&ST',N

TRACK ASS'(NM&NT C,N(&ST',N

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@ 4 D&S'(N #,R MAN5#ACT5RAB')'T6

DF4 or DF; & Design for ;iel$ ) is nee$e$ !o increase !he yiel$ing while !a"e o! an$ !o $ecrease !he

$efec!s in !he +anfac!ring "rocess. The DF4 s!e"s incl$es

• Gate 'ide integrity O antenna fiing

• Via resistance and relia#ility O etra contacts

• Rando! Particle defect O Cire spreading

• etal erosion O !etal slotting

• etal lift-off O !etal slotting

• etal over etching O !etal fill

Antenna ?iolation+

The antenna ill #e violated hen long running !etal can collect the charge during (P

2 che!ical !echanical polishing 4 and can destroy the gate of '& transistor 2or4 if the antennaratio is violated hich is given #y the fa#. The antenna ratio is defined as

=ntenna ratio =! =g here

=! area of !etal connected to gate =g total area of the gate

Antenna fi;ing

=ntenna can #e fied in to ays

1. etal jog 2 !etal ju!ping 4

9. nserting reverse #iased diode near gate of '&

!.Metal >og+

The figures belo$ sho$s antenna ?iolation and fi;ing it by metal >og

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%.#i;ing antenna $ith diode+

The figures #elo shos antenna violation fiing it ith inserting diode.

There are !wo ways !o fi< an!enna.

1. *irst !ethod is to insert;diode -no;auto;cell;selection -diode;cells antenna -nets Qget;netsnet na!eJS

9. &econd !ethod

• create;cell desired instance na!e of antenna cell. FK antenna1J scgp;ssantenna

• connect;net net na!e failing antenna chec)J antenna1=

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ANT&NNA 3',)AT',NS 'N 0'(0)'(0T&D N&TS

ANT&NNA #''N( 5S'N( D',D&S

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3ia doubling+

Replacing one via ith !ultiple vias can i!prove yield A ti!ing 2 series R reduction 4. thetool inserts !ultiple vias ithout re-routing. insert;redundant;vias is used to create !ultiple vias .

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" P06S'CA) 3&R'#'CAT',N

Design Rule Chec8

Design rules are series of para!eters provided #y se!iconductor !anufactures that ena#les thedesigner to verify the correctness of a !as) set. Design rules are specific to a !anufacturingprocess. = design rule set specifies certain geo!etric and connectivity restrictions to ensure

sufficient !argins to account varia#ility during !anufacturing process so that !ost of the designparts or) correctly.

n PD e can chec) only su#set of rules there in DR( rule dec)< these su#set of rules arerelated tp !etal layers and vias. The rules are present in technology file. The rules include!ini!u! spacing< !ini!u! area< !ini!u! idth etc. &o!e of the errors e have encountered inour #loc) are given #elo.

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)ayout ?s Schematic

= successful design rule chec) ensures the layout confir!s to the rules re+uired for faultless fa#rication. ?oever it does not guarantee is it really represent the circuit you desire tofa#ricate. This is here an "V& chec) is used.

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"S'(N ,## STA

( (o!piler is an i!ple!entation engine< &tarR( and Pri!e Ti!e are sign off engines. n general< the i!ple!entation engine and the sign-off engine are ell correlated ith each other.?oever<s!all variations can occur #ecause of the folloing K

• Pri!e Ti!e and &tarR( < as sign-off tools are !ore accurate.

• Pri!e Ti!e has reduced &ignal ntegrity pessi!is!.

• ( (o!piler !ight have i!ple!entation !argin

• ( (o!piler !ight have feer corners

These differences can cause ti!ing violations during final sign-off. Pri!e Ti!e supports the use ofti!ing !odels to represent chip su#-!odules. = ti!ing !odel contains infor!ation a#out the ti!ingcharacteristics< #ut not the logical functionality of a su#-!odule.

Pri!e Ti!e can generate a ti!ing !odel fro! a su#-!odule netlist < and then use that !odel inplace of the original netlist for ti!ing analysis at higher levels of hierarchy. This techni+ue !a)eshole chip analysis run !uch faster.

To perfor! stage delay calculation accurately and efficiently< Pri!e Ti!e uses !odels to representthe driver< R( 8etor) and capacity load on the net. =n ideal !odel ould produce eactly thesa!e delays and sles as a &P(F si!ulation at the output of the driver and at the input of eachreceiver.

To perfor! &tatic Ti!ing =nalysis< Pri!eTi!e !ust accurately calculate the delay and sle2transition ti!e 4 at each stage of each ti!ing path. = stage consists of a driving cell< the annotated

R( netor) at the output of the cell and the capacitive load of the netor) load pins. The goal is toco!pute the response at the driver output and at the netor) load pins< given the input sle oravefor! at the driver input using the least a!ount of runti!e necessary to get accurate results.

To perfor! stage delay calculation accurately and efficiently< Pri!eTi!e uses !odels to representthe driver< R( netor) and (apacitive load on the net. =n ideal !odel ould produce eactly thesa!e delays and sles as a &P(F si!ulation at the output of the driver and at the input of eachreceiver.

The driver !odel is intended to reproduce the response of the driving cellIs underlying transistorcircuitry hen connected to an ar#itrary R( netor) given for a specific input sle. The reducedorder netor) !odel is a si!plified representation of the full annotated netor) that has really the

sa!e response characteristics as the original netor). Pri!eTi!e uses the =rnoldi reduction!ethod to create this !odel.

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