5.2 Mathematical Power, Convenience, and Cost

• The set of operations represents a tradeoff among the cost of the hardware, the convenience for a programmer, and engineering considerations such as power consumption.

5.3 Instruction Set and Representation

• Two key consideration– The set of operations– The instruction format

5.4 Op-codes, Operands, and Results

• Each instruction contains three parts:– Op-codes– Operands– Results

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

Variable-Length Vs. Fixed-Length instructions

• Fixed length instructions can make processor hardware less complex and faster

5.7 General-Purpose Registers

• General purpose registers act as a temporary storage facility.

5.9 Programming with Registers

• The process of choosing which values the registers contain is known as register allocation.

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

5. 10 Register Banks

• Conflict occurs sometimes– R X + Y – S Z – X– T Y + Z

– The programmer must either reassign registers or insert an instruction to copy values

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

5.11 Complex and Reduced Instruction Sets

• CISC– Complex Instruction Set Computer– Intel 80X86 processors

• RISC– Reduced Instruction Set Computer– MIPS processor

5.12 RISC Design and the Execution Pipeline

• Several stages– Fetch the next instruction– Examine the OP-code– Fetch operands– Perform operation– Store the result

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

5.13 Pipelines and Instruction Stalls

• The instruction pipeline is transparent to programmers

• A stage of the pipeline stalls to wait for the operand to become available

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

5.14 Other Cause of Pipeline Stalls

• Access external storage

• Invoke a coprocessor

• Branches to a new location

• Calls to a subroutine

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

5.16 Programming, Stalls, and No-OP Instruction

• Insert a comment that explain the reason for a stall

• Insert no-op instructions to document an instruction stall

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

5.18 Types of Operations

• Arithmetic instructions

• Logical instructions

• Data access and transfer instructions

• Branch instructions

• Floating point instructions

• Processor control instructions

5.19 Program Counter, Fetch-Execute, and Branching

• Assign the program counter an initial address, Repeat forever {– Fetch: access the next step of the program

• Set an internal register to the next instruction

– Execute : perform the step of the program• Copy the content of the internal register to the

program counter

• }

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.

5.23 The Principle of Orthogonality

• An instruction set is orthogonal if each instruction performs a unique task.

5.24 Condition Codes and Conditional Branch

• The ALU sets a condition code.

• A conditional branch instruction can test one or more of the flag bits, and use the result to determine whether to branch.

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.