512K x 8 LOW VOLTAGE, NOVEMBER 2016 ULTRA LOW POWER … · 2016-11-16 · CS1 = VIh, f = 1 MHz ISB2...

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Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. E1 11/1/2016 IS62WV5128ALL IS62WV5128BLL ® Long-term Support World Class Quality 512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby TTL compatible interface levels Single power supply 1.65V – 2.2V VDD (IS62WV5128ALL) 2.5V – 3.6V VDD (IS62WV5128BLL) Fully static operation: no clock or refresh required Three state outputs Industrial temperature available Lead-free available DESCRIPTION The ISSI IS62WV5128ALL / IS62WV5128BLL are high- speed, 4M bit static RAMs organized as 512K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. When CS1 is HIGH (deselected) the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV5128ALL and IS62WV5128BLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), 32-pin sTSOP (TYPE I), 32-pin TSOP (Type II), 32-pin SOP and 36-pin mini BGA. FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2016 A0-A18 CS1 OE WE 512K x 8 MEMORY ARRAY DECODER COLUMN I/O CONTROL CIRCUIT GND VDD I/O DATA CIRCUIT I/O0-I/O7

Transcript of 512K x 8 LOW VOLTAGE, NOVEMBER 2016 ULTRA LOW POWER … · 2016-11-16 · CS1 = VIh, f = 1 MHz ISB2...

Page 1: 512K x 8 LOW VOLTAGE, NOVEMBER 2016 ULTRA LOW POWER … · 2016-11-16 · CS1 = VIh, f = 1 MHz ISB2 CMOS Standby Vdd = Max., Com. 15 µA Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V,

Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com 1Rev. E111/1/2016

IS62WV5128ALL IS62WV5128BLL

®Long-term SupportWorld Class Quality

512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

FEATURES

• High-speedaccesstime:55ns,70ns

• CMOSlowpoweroperation

36 mW (typical) operating

9µW(typical)CMOSstandby

• TTLcompatibleinterfacelevels

• Singlepowersupply

1.65V–2.2VVdd (IS62WV5128ALL)

2.5V–3.6VVdd (IS62WV5128BLL)

• Fullystaticoperation:noclockorrefresh required

• Threestateoutputs

• Industrialtemperatureavailable

• Lead-freeavailable

DESCRIPTION

TheISSIIS62WV5128ALL/IS62WV5128BLLarehigh-speed,4MbitstaticRAMsorganizedas512Kwordsby8 bits. It is fabricated using ISSI's high-performanceCMOStechnology.Thishighly reliableprocesscoupledwith innovative circuit design techniques, yields high-performance and low power consumption devices.

When CS1 is HIGH (deselected) the device assumesa standby mode at which the power dissipation can be reduceddownwithCMOSinputlevels.

Easy memory expansion is provided by using Chip Enable andOutputEnableinputs.TheactiveLOWWriteEnable(WE) controls both writing and reading of the memory.

TheIS62WV5128ALLandIS62WV5128BLLarepackagedin the JEDEC standard 32-pinTSOP (TYPE I), 32-pinsTSOP(TYPEI),32-pinTSOP(TypeII),32-pinSOPand36-pinminiBGA.

FUNCTIONAL BLOCK DIAGRAM

NOVEMBER 2016

A0-A18

CS1

OE

WE

512K x 8MEMORY ARRAYDECODER

COLUMN I/O

CONTROLCIRCUIT

GND

VDD

I/ODATA

CIRCUITI/O0-I/O7

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PIN DESCRIPTIONS

A0-A18 AddressInputs

CS1 Chip Enable 1 Input

OE OutputEnableInput

WE Write Enable Input

I/O0-I/O7Input/Output

NC No Connection

Vdd Power

GND Ground

1 2 3 4 5 6

A

B

C

D

E

F

G

H

A0

I/O4

I/O5

GND

VDD

I/O6

I/O7

A9

A1

A2

OE

A10

NC

WE

NC

A18

CS1

A11

A3

A4

A5

A17

A16

A12

A6

A7

A15

A13

A8

I/O0

I/O1

VDD

GND

I/O2

I/O3

A14

36-pin mini BGA (B) (6mm x 8mm)(Package Code B)

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Integrated Silicon Solution, Inc. — www.issi.com 3Rev. E111/1/16

IS62WV5128ALL, IS62WV5128BLL

® Long-term SupportWorld Class Quality

32-pinTSOP(TYPEI),(PackageCodeT)32-pinsTSOP(TYPEI)(PackageCodeH)

32-pinSOP(PackageCodeQ)32-pinTSOP(TYPEII)(PackageCodeT2)

PIN DESCRIPTIONS

A0-A18 AddressInputs

CS1 Chip Enable 1 Input

OE OutputEnableInput

WE Write Enable Input

I/O0-I/O7Input/Output

Vdd Power

GND Ground

PIN CONFIGURATION

12345678910111213141516

32313029282726252423222120191817

A11A9A8

A13WEA18A15VDD

A17A16A14A12A7A6A5A4

OEA10CS1I/O7I/O6I/O5I/O4I/O3GNDI/O2I/O1I/O0A0A1A2A3

12345678910111213141516

32313029282726252423222120191817

A17A16A14A12

A7A6A5A4A3A2A1A0

I/O0I/O1I/O2

GND

A15A18WEA13A8A9A11OEA10CS1I/O7I/O6I/O5I/O4I/O3

VDD

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IS62WV5128ALL, IS62WV5128BLL

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DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter TestConditions Vdd Min. Max. Unit

Voh OutputHIGHVoltage Ioh = -0.1mA 1.65-2.2V 1.4 — V Ioh = -1mA 2.5-3.6V 2.2 — V

VoL OutputLOWVoltage IoL = 0.1mA 1.65-2.2V — 0.2 V IoL = 2.1mA 2.5-3.6V — 0.4 V

VIh InputHIGHVoltage 1.65-2.2V 1.4 Vdd + 0.2 V 2.5-3.6V 2.2 Vdd + 0.3 V

VIL(1) InputLOWVoltage 1.65-2.2V –0.2 0.4 V 2.5-3.6V –0.2 0.6 V

ILI InputLeakage GND≤ VIn ≤ Vdd –1 1 µA

ILo OutputLeakage GND≤ Vout ≤ Vdd, OutputsDisabled –1 1 µANotes:1. VIL (min.) = –1.0V for pulse width less than 10 ns.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter Value Unit

Vterm TerminalVoltagewithRespecttoGND –0.2toVdd+0.3 V

Vdd VddRelatedtoGND –0.2toVdd+0.3 V

tStg StorageTemperature –65to+150 °C

Pt PowerDissipation 1.0 WNote:1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.Thisisa

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-ability.

OPERATING RANGE (Vdd)

Range AmbientTemperature IS62WV5128ALL IS62WV5128BLL

Commercial 0°Cto+70°C 1.65V-2.2V 2.5V-3.6V

Industrial –40°Cto+85°C 1.65V-2.2V 2.5V-3.6V

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Integrated Silicon Solution, Inc. — www.issi.com 5Rev. E111/1/16

IS62WV5128ALL, IS62WV5128BLL

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AC TEST LOADS

Figure1 Figure2

CAPACITANCE(1)

Symbol Parameter Conditions Max. Unit

CIn Input Capacitance VIn = 0V 8 pF

Cout Input/OutputCapacitance Vout = 0V 10 pFNote:1.Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.

AC TEST CONDITIONS

Parameter IS62WV5128ALL IS62WV5128BLL (Unit) (Unit)

InputPulseLevel 0.4VtoVdd-0.2V 0.4VtoVdd-0.3V

InputRiseandFallTimes 5ns 5ns

InputandOutputTiming Vref Vref andReferenceLevel

OutputLoad SeeFigures1and2 SeeFigures1and2

IS62WV5128ALL IS62WV5128BLL

1.65-2.2V 2.5V-3.6V

r1(Ω) 3070 3070

R2(Ω) 3150 3150

Vref 0.9V 1.5V

Vtm 1.8V 2.8V

R1

30 pFIncluding

jig andscope

R2

OUTPUT

VTM

R1

5 pFIncluding

jig andscope

R2

OUTPUT

VTM

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6 Integrated Silicon Solution, Inc. — www.issi.com Rev. E111/1/16

IS62WV5128ALL, IS62WV5128BLL

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POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

62WV5128ALL (1.65V - 2.2V) Symbol Parameter TestConditions Max. Unit 70ns ICC VddDynamicOperating Vdd = Max., Com. 25 mA Supply Current Iout = 0 mA, f = fmAx Ind. 30

ICC1 OperatingSupply Vdd = Max.,CS1=0.2VCom. 10 mA Current We = Vdd-0.2V Ind. 10 f=1mhz

ISB1 TTLStandbyCurrent Vdd = Max., Com. 0.35 mA (TTLInputs) VIn = VIh or VIL Ind. 0.35 CS1 = VIh, f=1MHz

ISB2 CMOSStandby Vdd = Max., Com. 15 µA Current(CMOSInputs) CS1≥ Vdd – 0.2V, Ind. 15 VIn ≥ Vdd – 0.2V, or VIn ≤ 0.2V, f = 0

Note:1. At f = fmAx, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

62WV5128BLL (2.5V - 3.6V) Symbol Parameter TestConditions Max. Unit 55ns ICC Vdd DynamicOperating Vdd = Max., Com. 40 mA Supply Current Iout = 0 mA, f = fmAx Ind. 45

ICC1 OperatingSupply Vdd = Max.,CS1=0.2V Com. 15 mA Current We = Vdd-0.2V Ind. 15 f=1mhz ISB1 TTLStandbyCurrent Vdd = Max., Com. 0.35 mA (TTLInputs) VIn = VIh or VIL Ind. 0.35 CS1 = VIh, f=1MHz

ISB2 CMOSStandby Vdd = Max., Com. 15 µA Current(CMOSInputs) CS1≥ Vdd – 0.2V, Ind. 15 VIn ≥ Vdd – 0.2V, or VIn ≤ 0.2V, f = 0

Note:1. At f = fmAx, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

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IS62WV5128ALL, IS62WV5128BLL

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AC WAVEFORMS

READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, WE = VIh)

DATA VALIDPREVIOUS DATA VALID

tAA

tOHAtOHA

tRC

DOUT

ADDRESS

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

55ns 70ns Symbol Parameter Min. Max. Min. Max. Unit

trC ReadCycleTime 55 — 70 — ns

tAA AddressAccessTime — 55 — 70 ns

tohA OutputHoldTime 10 — 10 — ns

tACS1 CS1AccessTime — 55 — 70 ns

tdoe OEAccessTime — 25 — 35 ns

thzoe(2) OEtoHigh-ZOutput — 20 — 25 ns

tLzoe(2) OEtoLow-ZOutput 5 — 5 — ns

thzCS1 CS1toHigh-ZOutput 0 20 0 25 ns

tLzCS1 CS1toLow-ZOutput 10 — 10 — nsNotes:1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4to

Vdd-0.2V/Vdd-0.3VandoutputloadingspecifiedinFigure1.2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.

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AC WAVEFORMS

READ CYCLE NO. 2(1,3) (CS1, OE Controlled)

Notes:1. WEisHIGHforaReadCycle.2. Thedeviceiscontinuouslyselected.OE,CS1=VIL. We=VIh.3. AddressisvalidpriortoorcoincidentwithCS1LOWtransition.

tRC

tOHAtAA

tDOE

tLZOE

tACS1

tLZCS1

tHZOE

HIGH-ZDATA VALID

tHZCS

ADDRESS

OE

CS1

DOUT

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Integrated Silicon Solution, Inc. — www.issi.com 9Rev. E111/1/16

IS62WV5128ALL, IS62WV5128BLL

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WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

55ns 70ns Symbol Parameter Min. Max. Min. Max. Unit

tWC WriteCycleTime 55 — 70 — ns

tSCS1 CS1toWriteEnd 45 — 60 — ns

tAW AddressSetupTimetoWriteEnd 45 — 60 — ns

thA AddressHoldfromWriteEnd 0 — 0 — ns

tSA AddressSetupTime 0 — 0 — ns

tPWe WEPulseWidth 40 — 50 — ns

tSd DataSetuptoWriteEnd 25 — 30 — ns

thd DataHoldfromWriteEnd 0 — 0 — ns

thzWe(3) WELOWtoHigh-ZOutput — 20 — 20 ns

tLzWe(3) WEHIGHtoLow-ZOutput 5 — 5 — ns

Notes:

1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4VtoVdd-0.2V/Vdd-0.3VandoutputloadingspecifiedinFigure1.

2. TheinternalwritetimeisdefinedbytheoverlapofCS1LOWandWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthewrite.

3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.

AC WAVEFORMS

WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)

DATA-IN VALID

DATA UNDEFINED

tWC

tSCS1

tAW

tHA

tPWE

tHZWE

HIGH-Z

tLZWEtSA

tSD tHD

ADDRESS

CS1

WE

DOUT

DIN

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WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

DATA-IN VALID

DATA UNDEFINED

tWC

tSCS1

tAW

tHA

tPWE

tHZWE

HIGH-Z

tLZWEtSA

tSD tHD

ADDRESS

OE

CS1

WE

DOUT

DIN

DATA-IN VALID

DATA UNDEFINED

tWC

tSCS1

tAW

tHA

tPWE

tHZWE

HIGH-Z

tLZWEtSA

tSD tHD

ADDRESS

OE

CS1

WE

DOUT

DIN

Page 11: 512K x 8 LOW VOLTAGE, NOVEMBER 2016 ULTRA LOW POWER … · 2016-11-16 · CS1 = VIh, f = 1 MHz ISB2 CMOS Standby Vdd = Max., Com. 15 µA Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V,

Integrated Silicon Solution, Inc. — www.issi.com 11Rev. E111/1/16

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DATA RETENTION SWITCHING CHARACTERISTICS

Symbol Parameter TestCondition Min. Max. Unit

Vdr VddforDataRetention SeeDataRetentionWaveform 1.2 3.6 V

Idr DataRetentionCurrent Vdd=1.2V,CS1≥Vdd –0.2V — 15 µA

tSdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — ns

trdr RecoveryTime SeeDataRetentionWaveform trC — ns

DATA RETENTION WAVEFORM (CS1 Controlled)

VDD

CS1 ≥ VDD - 0.2V

tSDR tRDR

VDR

CS1GND

Data Retention Mode

Page 12: 512K x 8 LOW VOLTAGE, NOVEMBER 2016 ULTRA LOW POWER … · 2016-11-16 · CS1 = VIh, f = 1 MHz ISB2 CMOS Standby Vdd = Max., Com. 15 µA Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V,

12 Integrated Silicon Solution, Inc. — www.issi.com Rev. E111/1/16

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ORDERING INFORMATION

IS62WV5128ALL(1.65V-2.2V)

IndustrialRange:–40°Cto+85°C Speed(ns) OrderPartNo. Package

70 IS62WV5128ALL-70BI miniBGA(6mmx8mm)

ORDERING INFORMATION

IS62WV5128BLL(2.5V-3.6V)

IndustrialRange:–40°Cto+85°C Speed(ns) OrderPartNo. Package

55 IS62WV5128BLL-55TLI TSOP,TYPEI,Lead-free

55 IS62WV5128BLL-55QLI SOP,Lead-free

55 IS62WV5128BLL-55T2LI TSOP,TYPEII,Lead-free

55 IS62WV5128BLL-55HLI sTSOP,TYPEI,Lead-free

55 IS62WV5128BLL-55BI miniBGA(6mmx8mm)

55 IS62WV5128BLL-55BLI miniBGA(6mmx8mm),Lead-free

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Integrated Silicon Solution, Inc. — www.issi.com 13Rev. E111/1/16

IS62WV5128ALL, IS62WV5128BLL

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Page 14: 512K x 8 LOW VOLTAGE, NOVEMBER 2016 ULTRA LOW POWER … · 2016-11-16 · CS1 = VIh, f = 1 MHz ISB2 CMOS Standby Vdd = Max., Com. 15 µA Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V,

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Page 15: 512K x 8 LOW VOLTAGE, NOVEMBER 2016 ULTRA LOW POWER … · 2016-11-16 · CS1 = VIh, f = 1 MHz ISB2 CMOS Standby Vdd = Max., Com. 15 µA Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V,

Integrated Silicon Solution, Inc. — www.issi.com 15Rev. E111/1/16

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Integrated Silicon Solution, Inc. — www.issi.com 17Rev. E111/1/16

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