5 Memory and Storage

8/10/2019 5 Memory and Storage

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MEMORY AND STORAGE

Stanley L. Aquino


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Outline

.Basics of Semiconductor Memory

.Random-Access Memories (RAMs)


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Objectives

.Define the basic memory characteristics

.Explain what a RAM is and how it works

.Explain the difference between static RAMs(SRAMs) and dynamic RAMs (DRAMs)


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Memory Units

.Memoriesstoredatainunitsfromonetoeightbits.Themostcommonunitisthebyte,whichbydefinitionis8bits..Bitis the smallest unit of binary data..Byte is a unit for group of 8 bits..Data can be stored in 9-bit groups which consist of a byteplus a parity bit.

.Nibble is a group of 4 bits

.One byte can be split into two nibbles.


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Memory Units

.Computermemoriesareorganizedintomultiplesofbytescalledwords.Generally,awordisdefinedasthenumberofbitshandledasoneentitybyacomputer.Bythisdefinition,awordisequaltotheinternalregistersize(usually16,32,or64bits)..Forhistoricalreasons,assemblylanguagedefinesawordasexactlytwobytes.Inassemblylanguage,a32bitentityiscalledadouble-wordand64bitsisdefinedasaquad-word.


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Memory Units

.Each storage element in amemory can retain either a1 or a 0 and is called a cell..Memories are made up ofarrays of cells..Each block in the memoryarray represents onestorage cell, and itslocation can be identifiedby specifying a row and acolumn.

8x8 ARRAY

16x4 ARRAY

64x1 ARRAY

A64-cell memory array organized inthree different ways.


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Memory Units

.Amemoryisidentifiedbythenumberofwordsitcanstoretimesthewordsize.

.Example:

16kx8memory

Numberofwords=16,000words

Wordsize=8bits

.16kx8memorycanactuallystore16,384wordsofeightbitseach.

.Theactualnumberofwordsisalwaysapowerof2.

214=16,384


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Memory Units

.Thelocationofaunitofdatainamemoryarrayiscalleditsaddress.Itdependsonhowthememoryisorganizedintounitsofdata.

The address of the bluebit is row 5, column 4

The address of theblue byte is row 3

Memory address in 2-dimensional array


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Memory Address and Capacity

.A3-dimensionalarrayisarrangedasrowsandcolumns.Eachbytehasauniquerowandcolumnaddress.

a)How many bytes areshown?b)What is the location of theblue byte?

b) Row 5, column 8

a) 64 B


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Memory Address and Capacity

.The capacityof a memory is the total number ofdata units that can be stored.

.Computer memories typically have 256 MB (MBis megabyte) or more of internal memory.

The capacity is 64 bits

The capacity is

8 bytes = 64 bits

The capacity is 64 bytes


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Basic Memory Operations

.Thewriteoperationputsdataintoaspecifiedaddressinthememory.

.Thereadoperationcopiesdataoutofaspecifiedaddressinthememory.

.Theaddressingoperationselectsthespecifiedmemoryaddressandispartofboththewriteandthereadoperations.


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.Inordertoreadorwritetoaspecificmemorylocation,abinarycodeisplacedontheaddressbus.Internaldecodersdecodetheaddresstodeterminethespecificlocation.Dataisthenmovedtoorfromthedatabus.

RowaddressdecoderAddress busData busWriteMemory arrayReadColumn address decoderThe address bus is a group ofconductors with a commonfunction. Its size determinesthe number of locations thatcan be accessed. A 32 bitaddress bus can access 232locations, which isapproximately 4G.


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.Inadditiontotheaddressbusanddatabus,semiconductormemorieshavereadandwritecontrolsignalsandchipselectsignals.Dependingonthetypeofmemory,othersignalsmayberequired.

Chip Select(CS) or Chip Enable(CE) is used as part of addressdecoding. All other inputs are ignored if the Chip Select is notactive.

ReadEnable(RE) and WriteEnable(WE) signals are sent fromthe CPU to memory to control data transfer to or from memory.

Output Enable(OE) is active during a read operation,otherwise it is inactive. It connects the memory to the databus.


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1.The address is placedon the address bus.2.Data is placed on thedata bus.3.A write command isissued.


.Asimplifiedwriteoperationisshowninwhichnewdataoverwritestheoriginaldata.Datamovestothememory.

1

2

3


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1.The address is placedon the address bus.2.A read command isissued.3.A copy of the data isplaced in the data busand shifted into thedata register.


.Thereadoperationisactuallyacopyoperation,astheoriginaldataisnotchanged.

1

2

3

0

0

1


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Semiconductor Memories

.Semiconductormemoriesaredevicesforstoringdigitalinformationthatisfabricatedbyusingintegratedcircuittechnology..Theyareclassifiedaccordingtothetypeofdatastorageandthetypeofdataaccessmechanism.RAM-random-accessmemory.ROM-read-onlymemory


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Semiconductor Memories: RAM

.RAM(random-accessmemory)isatypeofmemoryinwhichalladdressesareaccessibleinanequalamountoftimeandcanbeselectedinanyorderforareadorwriteoperation..AllRAMshavebothreadandwritecapability..Volatilememoriesarememoriesthatlosestoreddatawhenthepoweristurnedoff..RAMisavolatilememory.


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Semiconductor Memories: ROM

.ROM (read-only memory) is a type of memory inwhich data are stored permanently or semipermanently..Data can be read from a ROM, but there is nowrite operation as in the RAM..Nonvolatile memories are memories that retainstored data even if power is turned off..ROM is a nonvolatile memory.


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Random Access Memories (RAMs)

.RAMs are read/write memories in which data can be writteninto or read from any selected address in any sequence..When a data unit is written into a given address in the RAM,the data unit previously stored at that address is replaced bythe new data unit..When a data unit is read from a given address in the RAM, thedata unit remains stored and is not erased by the readoperation..A RAM is typically used for short-term data storage because itcannot retain stored data when power is turned off.


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The RAM Family

.The two categories of RAM

.Static RAM (SRAM)

.Dynamic RAM (DRAM)

.Static RAMs generally use latchesas storage elementsand can therefore store data indefinitely as long as dcpower is applied..Dynamic RAMs use capacitorsas storage elements andcannot retain data very long without the capacitorsbeing recharged. This process of charging the capacitoris called refreshing.


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The RAM Family

.Comparison between SRAMs and DRAMs.

.Both SRAMs and DRAMs will lose stored data when dcpower is removed and, therefore, are classified asvolatile memories..Data can be read much faster from SRAMs than fromDRAMs..DRAMs can store much more data than SRAMs for agiven physical size and cost because the DRAM cell ismuch simpler, and more cells can be crammed into agiven chip area than in the SRAM.


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The RAM Family

StaticRAM(SRAM)DynamicRAM(DRAM)AsynchronousSRAM(ASRAM)SynchronousSRAM withburst feature(SB SRAM)ExtendedData OutDRAM(EDO DRAM)BurstEDO DRAM(BEDODRAM)Fast PageModeDRAM(FPM DRAM)SynchronousDRAM(SDRAM)Random-AccessMemory(RAM)Bits stored in asemiconductorlatch or flip-flop

Bits stored ascharge on acapacitor


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Static RAMs (SRAMs)

.All static RAMs are characterized bylatch memory cells.

.As long as dc power is applied to a static memory cell, itcan retain a 1 or 0 state indefinitely. If power is removed,the stored data bit is lost.

A typical SRAMlatch memory cell.


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Basic Static Memory Cell Array

.The memory cells in anSRAM are organized inrows and columns..All the cells in a row sharethe same Row Select line..Data in and data out linesare connected to a singledata line that serves aseither an input and outputline through buffers andcontrol.

Basic SRAM array

(n x 4 array)


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Basic Asynchronous SRAM Organization

.An asynchronousSRAM is one inwhich the operationis not synchronizedwith a system clock.

Logic diagramfor anasynchronous32k x 8 SRAM


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Basic Asynchronous SRAM Organization: TristateOutputs and Buses

.Tristate buffer allows two logic states (LOW -0 or HIGH -1) as input but produces three different types of outputsignals (LOW -o, HIGH -1 or HIGH IMPEDANCE Z)..It has two inputs: a data inputand a control input..The control input acts like a valve.

.When the control input is active, theoutput is the input..It allows the data lines to act as eitherinput or output lines and connect thememory to the data bus in a computer..Tristate outputs are indicated on logicsymbols by a small inverted triangle.

Tristate buffer


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Basic Asynchronous SRAM Organization: MemoryArray

.SRAM chips can be organized in single bits, nibbles (4bits), bytes (8 bits), or multiple bytes (16, 24, 32 bits, etc.)..The memory cell array is arranged in 256 rows and 128columns, each with 8 bits. The actual addresses are 215=32,768. Each address contains 8 bits. The capacity is32,768 bytes (typically expressed as 32 kB).

The organization ofa typical 32k x 8SRAM


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Basic Asynchronous SRAM Organization:Operation

.For the memory tooperate, chip select(CS) must be LOW..Fifteen address lines,eight of which aredecoded by the rowand seven by thecolumn decoder..Eight dataInput/output lines

Memory block diagram


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Basic Asynchronous SRAM Organization: Read

.Read cycle sequence:

.A valid address is put on theaddress bus.Chip select is LOW.Write enable is HIGH.Output enable is LOW.Data is obtained from the databus

.The input tristatebuffers aredisabled by gate G1, and thecolumn output tristatebuffers areenabled by gate G2.

Memory controlsignals

Connected to the eighttristateinput buffers

control input

Connected to the eighttristateoutput bufferscontrol input

0

1

0

1

(Enable)

0

(Disable)


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Basic Asynchronous SRAM Organization: Write

.Write cycle sequence:

.A valid address is put on theaddress bus.Chip select is LOW.Write enable is LOW.Output enable is a Dont Care.Data is placed on the data bus

.The input buffers are enabled bygate G1, and the output buffersare disabled by gate G2.

Memory controlsignals

Connected to the eighttristateinput bufferscontrol input

Connected to the eighttristateoutput bufferscontrol input

0

0

X

0

(Disable)

1

(Enable)


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Basic Asynchronous SRAM Organization: ReadCycle

.A valid address code is applied to the address lines for aspecified time interval..The chip select and the output enable inputs go LOW..After a specified time delay, valid data will appear on the datalines

A typical timing diagrams for a memory read cycle for SRAM


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Basic Asynchronous SRAM Organization: WriteCycle

.A valid address code is applied to the address lines for a specifiedtime interval called the write cycle time, tWE..The chip select and the write enable inputs go LOW..A valid data is supplied after a specified time interval after thedeassertionof Write enable signal.

A typical timing diagrams for a memory write cycle for SRAM


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Basic Synchronous SRAM

.A synchronous SRAM is synchronized with thesystem clock and uses clocked registers..The address, the read/write input, the chipenable, and the input data are all latched intotheir respective registers on an active clockpulse edge..Once this information is latched, the memoryoperation is in sync with the clock.


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Basic Synchronous SRAM: Read and Write

Read Cycles of Synchronous SRAM

Write Cycles of Synchronous SRAM


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Basic Synchronous SRAM with Burst Feature

A basic block diagram of a 32k x 8 synchronous SRAM with burst feature


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Basic Synchronous SRAM with Burst Feature

.A set of parallel lines can be indicated by a single heavyline with a slash and the number of separate lines in the set..Two basic types of synchronous SRAM are theflow-throughand the pipelined..The flow-throughsynchronous SRAM does not have aData output register, so the output data flowasynchronously to the data I/O lines through the outputbuffers..The pipelined synchronous SRAM has a Data outputregister so the output data are synchronously placed onthe data I/O lines.


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Basic Synchronous SRAM:The BurstFeature

.Burst feature allows the memory to read or writeat up to four locations using a single address byadding 00, 01, 10, and 11 to the two lowest -order address bits on successive clock pulses.


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Basic Synchronous SRAM:Read BurstFeature

Timing diagram of Read cycles of Synchronous SRAM with burst feature


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Basic Synchronous SRAM:Write BurstFeature

Timing diagram of Write cycles of Synchronous SRAM with burst feature


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SRAM Application: Cache Memory

.Cache memory is a relatively small, high-speed memorythat stores the most recently used instructions or datafrom the larger but slower main memory..Cache memory is basically a cost-effective method ofimproving system performance without having to resortto the expense of making all of the memory faster.

SRAM used as cache memory in computers

CACHECACHE


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SRAM Application: L1 and L2 Caches

.A first-level cache (L1 cache) is usually integrated into the processorchip and has a very limited storage capacity..L1 cache is also known as primary cache.

.A second-level cache (L2 cache) is a separate memory chip or setof chips external to the processor and usually has a larger storagecapacity than an L1 cache..L2 cache is also known as secondary cache.

Block diagram showing L1 and L2 cache memories in a computer system


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THANK YOU!


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5 Memory and Storage

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