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S.E. Sem. III [EXTC] Digital System Design

Time : 3 Hrs.] Prelim Paper Solution [Marks : 80 Q.1 Solve following : [20] Q.1(a) Explain the following decimals in gray code form

(i) (42)10 (ii) (17)10 [5]

Ans.: 1. (42)10 : 42 21 10 5 2 10 1 0 1 0 1

Decimal to binary conversion : (42)10 = (101010)2

Gray Code conversion : 1 0 1 0 1 0 1 1 1 1 1 1

(42)10 = (111111)2 in gray code 2. (17)10 :

17 8 4 2 11 0 0 0 1

Decimal to binary conversion (17)10 = (10001)2

Gray Code conversion : 1 0 0 0 1 1 1 0 0 1

(17)10 = (10001)2 in gray code. Q.1(b) Design a full adder using 3:8 Decoder [5] Ans.: 3 : 8 decoder has 3 input lines and 8 output line. Full adder is designed the following :

A B C S Ca0 0 0 0 0 01 0 0 1 1 02 0 1 0 1 03 0 1 1 0 14 1 0 0 1 05 1 0 1 0 16 1 1 0 0 17 1 1 1 1 1

Thus, S = m(1,2,4,7) Ca = m(3,5,6,7)

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Q.1(c) Convert JK flip flop to T flip flop. [5] Ans.: Truth table of T Flip-Flop Excitation table of JK flip-flop Conversion Table : K-map simplification :

T Qn Qn+1 J K0 0 0 0 X0 1 1 X 01 0 1 1 X1 1 0 X 1

Thus, Q.1(d) Perform the following operation using 2’s compliment

(i) (7)10 (15)10 (ii) (50)10 (2A)16 Comment on results of (i) and (ii)

[5]

Ans.:

T Qn Qn+1

0 0 00 1 11 0 11 1 0

Qn Qn+1 J K0 0 0 X 0 1 1 X 1 0 X 11 1 X 0

For JT

Qn

0 1

0 0 11 X X

J = T

For KT

Qn

0 1

0 X X 1 0 1

K = T

J

K

Qn

Qn

T

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Q.2(a) Prove that NAND and NOR gates are Universal gates. [10] Ans.: NAND and NOR are universal gates. This means using NAND and NOR we can construct

any other gates such as AND, OR NOT, XOR. This can be proved in the following way. 1) Constructing NOT : NAND : NOR : 2) Constructing AND : NAND : NOR : 3) Constructing OR : NAND : NOR :

y = A.A = A A

AA

A

AA

y = A A = A

A

B

y1 = A.B y1

y1

y = 1 1y .y = 1y = A.B = A . B

A A

B B

y = A B = A.B = A . B

A A

B B

y = A.B = A B = A + B

A

B

y1 = A.By1

y1

y = 1 1y y = 1y = A B = A + B

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4) Constructing XOR / XNOR : Q.2(b) Design 3 bit Binary to gray code Converter [10] Ans.:

A

B

y = A B y = A B

NAND

XOR XNOR

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Q.3(a) Minimize the following expression using Quine Mccluskey technique. F(A,B,C,D)=(0,1,2,3,5,7,9,11)

[10]

Ans.: No. A B C D

0 m0 0 0 0 0 1 m 1 0 0 0 1 2 m 2 0 0 1 0 3 m 3 0 0 1 1 5 m 5 0 1 0 1 7 m 7 0 1 1 1 9 m 9 1 0 0 1

11 m 11 1 0 1 1

1) Grouping according to number of 1’s Group A B C D

G0 0 0m0 0 0 0 0 G1 1 0m 1 0 0 0 0

2 0m 2 0 0 1 1 G2 3 0m 3 0 0 1 0

5 0m 5 0 1 0 1 9 0m 9 1 0 0 1

G3 7 0m 7 0 1 1 1 11 0m 11 1 0 1 1

2) Comparing

Group A B C DG0 G1 m0m1 0 0 0

m0m2 0 0 0

G1G2 m1m3 0 0 1 m1m5 0 0 1 m1m9 - 0 0 1 m2m3 0 0 1

G2G3 m3m7 0 1 1 m3m11 0 1 1 m5m7 0 1 1 m9m11 1 0 1

3) Comparing Group A B C DG0 G1 G2 m0 m1 m2 m3 0 0 m0 m2 m1 m3 0 0 G1 G2 G3 m1 m3 m5 m7 0 1m1 m3 m9 m11 0 1m1 m5 m3 m7 0 1m1 m9 m3 m11 0 1

A B

AD

BD

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m0 m1 m2 m3 m5 m7 m9 m11 A B () () (0,1,2,3) A D () () (1,3,5,7) B D () () (1,3,9,11)

F(A,B,C,D) = A B + A D + B D Q.3(b) What are shift registers? How are they classified? Explain working of any one

type of shift register. [10]

Ans.:

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Q.4(a) Design a 2 bit comparator and implement using logic gates [10] Ans.: Truth table:

K-map for A < B :

K-map for A = B :

n-bit comparator

A B

Input

A > B A = B A < B

Output

Input Output A1 A0 B1 B0 A < B A = B A > B 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0

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K-map for A > B

Implementation :

A1

B1

B1

B0

A0

A1

A0

B0

A1

A0

B1

B0

A1

A0

B1

B0

A0

B1

B0

A1

A0

B0

A1

B1

B1

A1

B0

A0

A1

A0

B1

B0

A > B

f(A,B,C,D)

A < B

Output

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Q.4(b) Explain Master slave JK Flip flop [5] Ans.: A Master-Slave J-K flip flop is a cascade of two S-R flip flop with feedback from the

outputs of the second to the inputs of the first, as shown in the figure below. Positive clock pulse are applied to the first flip-flop and the clock pulses are inverted

before these are applied to the second flip-flop. When Clk = 1 the first flip-flop is enabled and the outputs Qm and mQ respond to

the inputs J & K according to table below.

Truth table of J.K flip flop.

Inputs OutputsJn Kn Qn+1

0 0 Qn

1 0 10 1 01 1

nQ

At this time second flip-flop is inhibited because its clock is low (Clk 0)

When Clk goes low Clk 1 , the first flip-flop is inhibited and second flip-flop is

enabled, because now its clock is HIGH Clk 1 . Therefore the outputs Q & Q follows the outputs Qm & mQ respectively (Second &

third row of table) Since the second flip-flop simply follows the first one. It is referred to as the slave

and the first one as the master. Hence this configuration is referred to as master-slave (M-S) flip-flop.

In this circuit the inputs to the gala G3M & G4m do not change during the clock pulse therefore the race round condition does not exit.

The state to the master-slave flip-flop changes at the negative transition (tracking edge) of the clock pulse.

The logic symbol of an M-S flip-flop is shown. Fit the check input terminals the symbol is used to

illustrate that the output changes when the clock makes a transition & the accompanying bubble signifies negative transition (change is Clk from 1 to 0)

J

K

Clk

Q

Q

Pr

Cr

M-S J-K

Flip-Flop

Logic Symbol

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Q.4(c) Convert T flip flop to D flip flop. [5] Ans.: Q.5(a) What is shift register? Explain any one type of shift register. Give its

applications. [10]

Ans. : Shift Register : An array of flip flops is required to store binary information, number of bits in binary word. Thus one flip flop is required for each bit. The combination of n f/p can therefore store n bit binary word. It is called a register.

A shift is an n bit register with a provision for shifting its stored data by one bit provision at each tick of the clock. Thus, it is a storage device that can be used to store data and shift it left or right.

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Applications : They find themselves in a variety of applications including microprocessor. In 8085 have seven 8 bit registers, referred as general purpose register and five one bit registers referred to as flags. Types : They can be classified as follows based on the method which data can be loaded on and read from shift register : a) Serial in serial out shift registers. b) Serial in parallel out shift register. c) Parallel in serial out shift register. d) Parallel in parallel out shift register. Serial in serial out shift register (Left shift) The serial input (Din) is shifted by one bit position at each tick of the clock. This data bit (Din) appears at the Dout after 4 clock ticks. Thus a ‘n’ bit serial in serial out shift register can be used to delay a signal by “n” clock ticks. Initially all flip flops are reset Q3Q2Q1Q0 = 0000 Consider Din = 1 After the 1st clock pulse Q3 Q2 Q1 Q0 = 0 0 0 1 After the 2nd clock pulse Q3 Q2 Q1 Q0 = 0 0 1 1 After the 3rd clock pulse Q3 Q2 Q1 Q0 = 0 1 1 1 After the 4th clock pulse Q3 Q2 Q1 Q0 = 1 1 1 1

Q.5(b) Explain Full Adder circuit using PLA having three inputs, 8 product terms and two outputs.

[10]

Ans.:

Q3 D3

Clk

Q2 D2

Clk

Q1 D1

Clk

Q0 D0

ClkDin

Clk

Dout

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Q.6 Explain the following : [20] Q.6(a) Explain VHDL Code for Full Subtractor. [5] Ans.: Lirary IEEE; Use IEEE.STDLOGIC 1164.ALL; Use IEEE.STDLOGICARITH.ALL; Use IEEE.STDLOGICUNSIGNED.ALL; Entity full_sub is Port (a,b,c: in std_logic; bo, d: out std_logic); end full_sub; architecture behavioural of full_sub is begin d< = a xor b xor c; b0 < = ((not a) and b) or (b and c) or ((not a) and c)

end behavioural; Q.6(b) Explain SRAM and DRAM. [5] Ans.:

SRAM DRAM 1) It stands for static random access

memory. It stands for dynamic random access memory.

2) It does not require periodic refreshing. It requires periodic refreshing. 3) Simple to construct. Difficult to construct.4) No. of transistors required to hold the

data is more. It requires a transistor & capacitor for every bit of data.

5) Consumes less power. Consumes more power. 6) It is more expensive. It is less expenses.

Q.6(c) Compare TTL and CMOS logic families. [5] Ans.:

TTL CMOS 1) It utilizes BIT. It utilizes FET.2) Less functional density. High functional density. 3) It consumes more power. It consumes less power. 4) Less susceptible to static discharge. They are more susceptible discharge . 5) Transmission of digital signal becomes

difficult & more expensive. Due to longer rise & fall times, transmission becomes simpler & less.

Q.6(d) Explain CPLD and FPGA. [5] Ans.:

CPLDs FPGAs Architecture Large, wide fan-in blocks of AND-

OR logic Array of small logic blocks surrounded by I/O

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CPLDs FPGAs Applications Bus interfaces complex state

machines fast memory interfaces wide decoders PAL-device integration

Logic consolidation board integration replace obsolete devices simple state machines complex controllers / interfaces

Key Attributes Fast pin-to-pin performance Predictable timing Easy to use

Very high density lots of I/Os and flip-flops generally lower power SRAM devices are reprogrammable.

Gate Capacity 300-6,000 gates 800-100,000 gates Design Timing Fixed, PAL-like very fast pin-to-

pin performance Application dependent very high shift frequencies

Number of I/Os

30-200 50-400

Number of Flip-flops 30-200 100-5,500

Process Technology

EPROMEEPROM FLASH

SRAMAnti-fuse EEPROM

In-System Programmable

Some EEPROM- and FLASH-based devices

SRAM-based devices and some EEPROM-based devices

One-Time Programmable (OTP)

EPROM devices in plastic packages. Some EEPROM- and FLASH-based devices

All anti-fuse-based devices

Power Consumption

0.5-2.0W static0.5-4.0W dynamic

Very low static dynamic consumption is application dependent, 0.1-2W typical

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