ii New Patents

4980821

STOCK-MEMORY-BASED WRITABLE INSTRUCTION SET COMPUTER HAVING A SINGLE

DATA BUS

Philip Koopman, Glen B Haydon assigned to Harris Corporation

A computer is provided as an add-on board for attachment to a host computer. Included are a single data bus, a 16-bit arithmetic logic unit, a data stack, a return stack, a main program memory, data registers, program counters, microprocessor memory, and microinstruction register. Each stack has a pointer which may be set without altering the contents of the respective stacks. The main program memory has a direct connection to the writable microprogram memory for providing instruction. MVP- F O R T H is used for programming a microcode assembler, a cross-compiler, a set of diagnostic programs, and microcode.

4984151

FLEXIBLE, NEXT-ADDRESS GENERATION MICROPROGRAM

SEQUENCER

each means respectively generating one of the plurality of the generated addresses.

4989132

OBJECT-ORIENTED, LOGIC, AND DATABASE PROGRAMMING

TOOL WITH GARBAGE COLLECTION

Fredric H Mellender, Andrew G Straw, Stephen E Riegel assigned to Eastman Kodak Company

A programming tool is provided which in- tegrates an object-oriented programming language system, a logic programming language system, and a database in such a manner that logic terms can be treated as objects in the object- oriented programming language system, objects can be treated as logic terms in the logic pro- gramming language system, and logic terms and objects are stored in the database in a common data structure format. Automatic management of the database is provided which is transparent to the user.

Vineet Dujari assigned to Advanced Micro Devices Inc

A flexible, sequencer for providing next-address generation in the execution of a microprogram is described. The sequencer includes means for receiving an externally provided base address and an externally provided address offset value, a stack for storing return base address pointers, and means for storing a current program pointer counter address. The sequencer comprises means for selecting an address from one of a plurality of generated addresses and for pro- viding the selected address as the next address i n the execution of the microprogram, and means for generating the plurality of addresses in- eluding an address generation means selected from the group consisting of means for adding the address offset value with a stack stored return base address, means for adding the address offset value with the current program pointer counter address, means for selectively in- crementing the selected address by one of a plurality of predetermined integral values, and means for selectively shifting the address offset value and for overlaying the external base address with the shifted address offset value,

4991086

MICROPROGRAM CONTROLLED MICROPROCESSOR HAVING A

PLURALITY OF INTERNAL BUSES AND INCLUDING

TRANSFER REGISTER DESIGNATION SYSTEM

Shingo Kojima, Tokyo, Japan assigned to NEC Corporation

A microprogram transfer register designation system for a microprogram controlled micro- processor which has a plurality of internal data buses such that there are previously prepared some number of source register sets each designating one source register for each of the internal buses and some number of destination register sets each designating one destination register for each of the internal buses, wherein one of the source register sets and one of the destination register sets is selected when an inter- register transfer is executed. A transfer register designation field of a microcode includes at least one transfer inhibit flag for the internal buses.