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Transcript of 4869_VirtuosoBroch_FNL
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PreCisely The asTesT PaThTo DierenTiaTeD siliCon
Personal consumer electronics and wireless products have become the
dominant orce in todays global electronics market. And relentless
demand or new eatures and unctionality in these devices is driving
unprecedented growth in RF, analog, and mixed-signal applications.
To create new products that ulll this demand, IC designers must
manipulate precise analog quantitiesvoltages, currents, charges,
and continuous ratios o parameter values such as resistance and
capacitance. This is when companies turn to custom design.
Full-custom design maximizes perormance while minimizing area and
power. However, it requires signicant handcrating by a select set o
engineers with very high skill levels. In addition, custom analog circuits
are more sensitive to physical eects, which are exacerbated at new,
nanometer process nodes. To streamline the process o designing
custom ICs and integrating them into end products, semiconductor
and systems companies need sophisticated sotware and fow
methodologies to meet time-to-market and time-to-volume goals.
The Cadence Virtuoso custom design platorm accelerates the design
o custom ICs across various process nodes. By selectively automating
aspects o custom analog design and providing advanced technologies
integrated on a common database, it allows engineers to ocus on
precision-crating their designswithout sacricing creativity to
repetitive manual tasks.
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a new aPProaChTo CusTom Design
The Virtuoso custom design platorm is a comprehensive system that
accelerates the process o getting dierentiated designs into silicon
at a variety o design nodes.
It includes advances like new constraint-driven design, which preserves
design intent by enabling ecient design collaboration. Designers can
speciy design needs, save these constraints in context with the design,and then use this inormation to drive the accelerated layout solution
to reduce errors.
Industry-leading high-speed simulators meet the stringent simulation
and analysis requirements or analog, RF, and mixed-signal designs.
Meanwhile, a new custom foorplanner allows analog design teams
to rapidly explore multiple design architecturesand the implications
o these design choicesprior to implementation.
Improved layout capabilities, a new user interace that greatly simplies
the complex tasks analog designers must perorm, and integrated DFM
urther enhance the Virtuoso platorm. The result is the astest, most
accurate path to the most dierentiated silicon possible.
www.cadence.com
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The VirTuoso CusTom Design PlaTorm
auTomaTeD ConsTrainT managemenT
AREA
POWER PERFORMANCE PARASITICS
Multi-Mode Simulation
Silicon Analysis
Chip Finishing
Mfg
Design Specification
Accelerated Layout
OpenDatabase
ConstraintManagementCustomer IP
PDKs
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www.cadence.com
siliCon aCCuraCy
Virtuoso process design kits (PDKs) contain all the manuacturing-related
parametersrom design rules to characterized modelsneeded to
ensure a design will be manuacturable according to original design
intent. At the heart o each PDK lies a silicon-calibrated device model.
Virtuoso Multi-mode Simulation uses these same device models,
thereore designs created using the Virtuoso platorm achieve complete
silicon accuracy. Virtuoso PDKs are available rom Cadence as well as
leading IC manuacturing companies such as TSMC, UMC, Chartered,
IBM, and Jazz.
enhanCeD Design CaPTureanD simulaTion enVironmenT
The Virtuoso design environment oers a variety o new methods to
speed design creation and simulation. A revolutionary new way o
working within the schematic editor allows engineers to use design
constraints to more eciently communicate with implementation
engineers. This constraint-driven design approach lets designers speciy
design parameterssuch as matching, symmetry, and alignment
and save these constraints in context with the design. They can use
this inormation to drive an accelerated layout solution. The simulation
environment then automatically captures the design process, such as
the steps in the fow and the necessary data les, enabling designersto quickly build customized design methodologies. This method
signicantly boosts productivity, ensures consistency, and reduces errors.
The enhanced design environment also serves as a natural springboard
to IP reuse. In addition, a parallel execution capability enables designers
to quickly and easily characterize designs across all corners and statistical
variations. It automates design reviews by instinctively generating reports
that compare measured design data against specications.
worlD-Class simulaTion
Virtuoso Multi-mode Simulation provides custom IC designers with
a complete design and verication solution or analog, RF, mixed-
signal, memory and SoC designs. Virtuoso Multi-mode Simulation
is a combination o the industrys leading SPICE, Fast SPICE, RF, and
analog mixed-signal simulators in a unique shared licensing package.
It is designed to meet the changing simulation needs o designers as
they move through the design cyclerom architecture exploration to
block level development to RF design and to nal ull-chip verication.
Customers can choose the right simulator or the job. These include
Virtuoso Spectre Circuit Simulator, Virtuoso Spectre RF Simulator,
Virtuoso UltraSim Full-Chip Simulator, and Virtuoso AMS Spectre
and Virtuoso AMS Ultra options.
aCCeleraTeD layouT
Virtuoso accelerated layout provides the astest path to custom physical
design. It delivers an unparalleled set o eatures rom QuickCell
parameterized cell denition to design rule-driven support. More
advanced capabilities such as constraint-based connectivity-driven
design, foorplanning, and design optimization urther help to achieve
better yield. Connectivity-driven layout provides a proven 4-10x
productivity boost over manual layout editing, while design rule-driven
support ensures correct-by-construction layout, which is especiallyimportant at advanced design geometries. Also included are automated
custom placement and automated custom routing capabilities, which
not only ollow the technology le but also the design constraints
entered by the ront-end designer. For users who preer ully automated
layout o blocks, Virtuoso accelerated layout also supports constraint-
based layout synthesis.
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www.cadence.com
siliCon-aCCuraTe analysis
For analog/mixed-signal design at 0.18 micron and below, high-
accuracy parasitic extraction, analog IR-drop analysis, and power grid
electromigration analysis become critical or both circuit design and ull-
chip electrical verication. Virtuoso silicon analysis combines all o these
capabilities with design rule checking (DRC) and layout-versus-schematic
checking (LVS). For high-requency designs (>1GHz), Virtuoso silicon
analysis includes inductance extraction, signal-wire electromigration
analysis, and a ast eld solver or capacitance extraction. These
capabilities enable design teams to perorm silicon-accurate analysis
quickly and avoid extremely expensive unplanned re-spins.
ComPrehensiVe Design inishingTeChnologies
Several sophisticated Virtuoso technologies address the most
demanding design nishing tasks. Because the Virtuoso platorm is
built on OpenAccess, design teams can pass designs back and orth
reely between custom and cell-based environments without using
translators. Virtuoso chip nishing technologies include the worlds
most advanced chip-level routing or 90nm and 65nm designs, a new
and industry-proven chip optimization technology or optimizing design
routes at the top-level, and migration technologies to ease the reuse
o custom digital IP. Nonetheless, design nishing involves more thanjust physical design; it also requires silicon analysis, such as IR-drop,
and substrate noise analysis capabilities that are required or advanced
process technologies. The Virtuoso platorm oers the industrys most
complete set o ull-chip silicon analysis capabilities.
VirTuoso PlaTorm ConiguraTionsDesigneD or lexiBiliTy
Cadence oers the Virtuoso custom design platorm as tiered
amilies o products. Each conguration provides a set o capabilities
tailored to dierent needs. The L amily is an entry-level version,
providing the proven capabilities o this industry-leading custom IC
design environment. The Virtuoso custom design platorm XL amily
o products extends the L amily to provide higher levels o design
assistance to the end user, including new design constraints, correct-
by-design layout, and advanced simulation modes. The GXL amily
urther delivers the platorms most advanced capabilities, including
design optimization or yield, cell and foor planning capabilities, and
sophisticated routing technology.
FLEXIBLE PRODUCT CONFIGURATIONS
PlacementTechnology
YieldImprovement
ChipRouting
PlanningImplement-ation Tools
GXL LEVELAdvanced
ParasiticEstimation
DesignOptimization
MultipleTestbenches
DesignConstraints
XL LEVELAssisted
L LEVEL
Basic
Connectivity-Driven Design
AdvancedAnalyses
DesignerProductivity
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Cadence Design Systems, Inc.
Corporate Headquarters2655 Seely Avenue, San Jose, CA 95134+1.408.943.1234 (outside U.S.)+1.800.746.6223 (inside U.S.)www.cadence.com
2006 Cadence Design Systems, Inc. All rights reserved. Cadence, Spectre, and Virtuoso areregistered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc.All others are properties of their respective holders.
7048D 0307 MK/INH/JA/PDF
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