[42] MCS_SAR ADC
2
Merged capacitor switching based SAR ADC with highest switching energy-efficiency V. Hariprasath, J. Guerber, S.-H. Lee and U.-K. Moon A modified merged capacitor switching (MCS) scheme is proposed for the successive approximation register (SAR) analogue-to-digital con- verter (ADC). The conventional MCS technique previously applied to a pipelined ADC improves signal processing speed and, with use in the SAR ADC, this scheme achieves lowest switching energy among existing switching schemes. The MCS scheme achieves 93.4% less switching energy as compared to the conventional architecture. Introduction: The capacitive array digital-to-analogue converter (D/A) in the feedback path of the SAR ADC approximates the sampled input voltage after every comparison. The conventional capacitor array switch- ing scheme of the SAR ADC is energy inefficient [1] in performing this approximation. This Letter explains the MCS scheme [2] for a SAR ADC and enumerates the advantages of this scheme in comparison with the present techniques. ip V in V E = 0 cm V cm V cm V cm V cm V cm V C C 2C C C 2C cm V cm V cm V cm V cm V cm V C C 2C C C 2C cm V cm V cm V cm V ref V C C 2C C C 2C cm V cm V cm V cm V ref V C C 2C C C 2C 2 ref E = 0.5CV 2 ref E = 0.5CV ip in -V V >0 ip in ref -V > 0.5V V ip in ref -V > -0.5V V cm V cm V cm V cm V ref V C C 2C C C 2C cm V cm V ref V C C 2C C C 2C ref V cm V cm V ref V C C 2C C C 2C ref V 2 ref E = 0.125CV 2 ref E = 0.625CV cm V cm V cm V cm V ref V C C 2C C C 2C cm V cm V ref V C C 2C C C 2C ref V cm V cm V ref V C C 2C C C 2C ref V 2 ref E = 0.625CV 2 ref E = 0.125CV ip in ref -V > -0.5V V ip in ref -V > -0.25V V ip in ref -V > -0.75V V ip in ref -V >0.75V V ip in ref -V > 0.5V V ip in ref -V > 0.25V V a b Fig. 1 Merged capacitor switching scheme and energy consumption Merged capacitor switching scheme: The energy consumption of a 3-bit conventional switching scheme is described in [3]. The energy consumption is quite different for the ‘UP’ and ‘DOWN’ transitions [1]. In particular, the conventional SAR switching scheme consumes five times more energy for a ‘DOWN’ transition as compared to the cor- responding ‘UP’ transition, as illustrated in [3]. This inefficiency in switching energy leads to increased power consumption, dynamic settling errors in references and in turn limits the speed of the converter. A three-level capacitor array D/A with series capacitor coupling was used in [4] to partially address some of the above inefficiencies with the added cost of calibration and additional digital complexity. A 3-bit MCS scheme is shown in Figs. 1a and b. The input is sampled onto the virtual node. The first comparison does not consume any switching energy as compared to the conventional scheme. Further, ‘UP’ and ‘DOWN’ transitions are symmetrical and consume equal energy. In particular, ‘UP’ and ‘DOWN’ transitions consume energy of 0.5 CV ref 2 J. A single-ended implementation of the proposed 10-bit ADC implementation of the MCS SAR is shown in Fig. 2. The switching network, number of cycles and logic complexity is the same as that of the conventional switching scheme. The following Sections elaborate on switching energy and matching requirements for a 10-bit MCS SAR. 9 B 0 B sampling phase conversion phase 8 B B 7 B 6 B 5 B 1 B 0 logic Dout 9 0 B -B in V 256C 128C 64C 32C 2C C C cm V 9 0 B - B = 10 bit binary word ref V ref V 9 B Fig. 2 10-bit MCS-SAR ADC SAR switching energy: The average energy required for charging and discharging the SAR capacitor array determines the efficiency of the switching scheme [1]. The average switching energy for different switching schemes [1, 3, 5] was compared through a behavioural simulation of a 10-bit SAR ADC. The switching energy efficiency for different schemes is discussed below. The behavioural simulation of average switching energy for different schemes is shown in Fig. 3. With respect to the conventional switching tech- nique, the split-capacitor scheme [1] achieves 37.4% (E avg ¼ 852.3 CV ref 2 ), the energy-saving scheme [3] achieves 58.7% (E avg ¼ 563.8 CV ref 2 ) and the set and down scheme [5] achieves 81% (E avg ¼ 255 CV ref 2 ). However, these switching schemes achieve energy savings at the cost of increased digital switching complexity, common mode variation and matching requirements. 0 200 400 600 800 1000 0 200 400 600 800 1000 1200 1400 1600 1800 output code energy, CV 2 ref conventional [1] split-capacitor [1] energy saving [3] set and down [5] MCS Fig. 3 Switching energy comparison The MCS scheme is 93.4% (E avg ¼ 84.7 CV ref 2 ) more efficient than the conventional switching scheme and is the highest reported switching energy efficiency among existing methods. Average switching energy for the different switching schemes and the proposed switching scheme is given below: conventional scheme [1] E avg ≃ ∑ n i=1 2 n+1−2i (2 i − 1)CV 2 ref J (1) energy saving scheme [3] E avg ≃ 3.2 n−3 + ∑ n i=3 2 n+1−2i (2 i−1 − 1)CV 2 ref J (2) set and down scheme [5] E avg ≃ ∑ n i=1 2 n−2−i CV 2 ref J (3) ELECTRONICS LETTERS 29th April 2010 Vol. 46 No. 9 Authorized licensed use limited to: Sogang University Loyola Library. Downloaded on May 08,2010 at 01:17:54 UTC from IEEE Xplore. Restrictions apply.
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Merged capacitor switching based SAR ADCwith highest switching energy-efficiency
V. Hariprasath, J. Guerber, S.-H. Lee and U.-K. Moon
A modified merged capacitor switching (MCS) scheme is proposed forthe successive approximation register (SAR) analogue-to-digital con-verter (ADC). The conventional MCS technique previously appliedto a pipelined ADC improves signal processing speed and, with usein the SAR ADC, this scheme achieves lowest switching energyamong existing switching schemes. The MCS scheme achieves93.4% less switching energy as compared to the conventionalarchitecture.
Introduction: The capacitive array digital-to-analogue converter (D/A)in the feedback path of the SAR ADC approximates the sampled inputvoltage after every comparison. The conventional capacitor array switch-ing scheme of the SAR ADC is energy inefficient [1] in performing thisapproximation. This Letter explains the MCS scheme [2] for a SARADC and enumerates the advantages of this scheme in comparisonwith the present techniques.
ipV
inV
E = 0
cmV
cmV
cmV
cmV
cmV
cmV
C C2C
C C2C
cmV
cmV
cmV
cmV
cmV
cmV
C C2C
C C2C
cmV
cmV
cmV
cmV
refV
C C2C
C C2C
cmV
cmV
cmV
cmVrefV
C C2C
C C2C
2refE = 0.5CV
2refE = 0.5CV
ip in-VV >0
ip in ref-V > 0.5VV
ip in ref-V > -0.5VV
cmV
cmV
cmV
cmV
refV
C C2C
C C2C
cmV
cmV
refV
C C2C
C C2C
refV
cmV
cmV
refV
C C2C
C C2C
refV
2 ref
E =
0.1
25C
V
2refE
= 0.625C
VcmV
cmV
cmV
cmVrefV
C C2C
C C2C
cmV
cmVrefV
C C2C
C C2C
refV
cmV
cmVrefV
C C2C
C C2C
refV
2 ref
E =
0.6
25C
V
2refE
= 0.125C
V
ip in ref-V > -0.5VV
ip in ref-V > -0.25VV
ip in ref-V > -0.75VV
ip in ref-V >0.75VV
ip in ref-V > 0.5VV
ip in ref-V > 0.25VV
a
b
Fig. 1 Merged capacitor switching scheme and energy consumption
Merged capacitor switching scheme: The energy consumption of a3-bit conventional switching scheme is described in [3]. The energyconsumption is quite different for the ‘UP’ and ‘DOWN’ transitions[1]. In particular, the conventional SAR switching scheme consumesfive times more energy for a ‘DOWN’ transition as compared to the cor-responding ‘UP’ transition, as illustrated in [3]. This inefficiency inswitching energy leads to increased power consumption, dynamicsettling errors in references and in turn limits the speed of the converter.A three-level capacitor array D/A with series capacitor coupling wasused in [4] to partially address some of the above inefficiencies withthe added cost of calibration and additional digital complexity.
A 3-bit MCS scheme is shown in Figs. 1a and b. The input is sampledonto the virtual node. The first comparison does not consume anyswitching energy as compared to the conventional scheme. Further,‘UP’ and ‘DOWN’ transitions are symmetrical and consume equal
ELECTRONICS LETTERS 29th April 2010 Vol. 46
Authorized licensed use limited to: Sogang University Loyola Library. Downl
energy. In particular, ‘UP’ and ‘DOWN’ transitions consume energyof 0.5 CVref
2 J.A single-ended implementation of the proposed 10-bit ADC
implementation of the MCS SAR is shown in Fig. 2. The switchingnetwork, number of cycles and logic complexity is the same as that ofthe conventional switching scheme. The following Sections elaborateon switching energy and matching requirements for a 10-bit MCS SAR.
9B 0Bsampling
phase
conversionphase
8B B7 B6 B5 B1 B0
logic
Dout
9 0B -B
inV
256C 128C 64C 32C 2C C C
cmV
9 0B - B = 10 bit binary word
refVrefV
9B
Fig. 2 10-bit MCS-SAR ADC
SAR switching energy: The average energy required for charging anddischarging the SAR capacitor array determines the efficiency of theswitching scheme [1]. The average switching energy for differentswitching schemes [1, 3, 5] was compared through a behaviouralsimulation of a 10-bit SAR ADC. The switching energy efficiency fordifferent schemes is discussed below.
The behavioural simulation of average switching energy for differentschemes is shown in Fig. 3. With respect to the conventional switching tech-nique, the split-capacitor scheme [1] achieves 37.4% (Eavg ¼ 852.3 CVref
2 ),the energy-saving scheme [3] achieves 58.7% (Eavg ¼ 563.8 CVref
2 ) andthe set and down scheme [5] achieves 81% (Eavg ¼ 255 CVref
2 ). However,these switching schemes achieve energy savings at the cost of increaseddigital switching complexity, common mode variation and matchingrequirements.
0 200 400 600 800 10000
200
400
600
800
1000
1200
1400
1600
1800
output code
ener
gy, C
V2 re
f
conventional [1] split-capacitor [1] energy saving [3] set and down [5] MCS
Fig. 3 Switching energy comparison
The MCS scheme is 93.4% (Eavg ¼ 84.7 CVref2 ) more efficient than
the conventional switching scheme and is the highest reported switchingenergy efficiency among existing methods. Average switching energyfor the different switching schemes and the proposed switchingscheme is given below:
conventional scheme [1] Eavg ≃∑n
i=12n+1−2i(2i − 1)CV 2
ref J (1)
energy saving scheme [3] Eavg ≃ 3.2n−3
+∑n
i=32n+1−2i(2i−1 − 1)CV 2
ref J(2)
set and down scheme [5] Eavg ≃∑n
i=12n−2−iCV 2
ref J (3)
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MCS scheme Eavg ≃∑n−1
i=12n−3−2i × (2i − 1)CV 2
ref J (4)
INL and DNL requirements: The unit capacitor in the SAR ADCcapacitor array is typically limited by matching requirements. The vari-ation in unit capacitors was assumed to be Gaussian distributed (N (0,s2)), where s is the standard deviation of matching between unit capaci-tors. Assuming Vref and GND as the reference levels for the capacitorarray D/A, the INL and DNL requirement for an ‘n’ bit conventionalconverter can be derived as follows:
Vout(n) =S
n−1i=1 (Ci + DCi)bi
CtotalVref = Dout Vref (5)
DNL(n) = Vout(n) − Vout(n − 1), INL(n) = Vout(n) − Videal(n) (6)
E(DNL2)max = 2ns2, sDNL,max = 2n/2s (7)
E(INL2)max = 2n−2s2, sINL,max = 0.5 × 2n/2s (8)
where Dout is the output code of the ADC, and Vout(n), DCi, Ctotal are thereference voltage, mismatch and total capacitance of the capacitive arrayD/A. The total capacitance was assumed to be constant for all theswitching schemes. The INL and DNL requirements for the differentswitching schemes are shown in Table 1.
Table 1: INL and DNL comparison for 10bit SAR ADC
Switching scheme sINL,max, LSB sDNL,max, LSB
Conventional [1] 16s 32s
Split-capacitor [1] 16s32s��2
√
Energy saving [3] 16s 32s
Set and down [5] 16s 32s
MCS16s��2
√ 32s��2
√
The unit-capacitance for MCS SAR is twice that of the conventionalSAR ADC when sized for the same kT/C noise consideration, which
ELECTR
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results in improved INL and DNL performance as compared to aconventional architecture.
Conclusions: A three-level capacitor switching scheme is proposed forSAR ADC. This switching scheme achieves the highest switchingenergy efficiency among the existing switching schemes while reducingstatic linearity requirements. The MCS scheme also has relaxed match-ing requirements for the capacitor array without increasing the complex-ity of digital logic and switches.
# The Institution of Engineering and Technology 201015 March 2010doi: 10.1049/el.2010.0706
V. Hariprasath, J. Guerber and U.-K. Moon (School of ElectricalEngineering and Computer Science, Oregon State University, 1148Kelley Engineering Center, Corvallis, OR 97331-5501, USA)
E-mail: [email protected]
S.-H. Lee (Electronic Engineering, Sogang University, 1 Sinsoo-Dong,Mapo-Gu, Seoul 121-742, Korea)
References
1 Ginsburg, B.P., and Chandrakasan, A.P.: ‘An energy-efficient chargerecycling approach for a SAR converter with capacitive DAC’. IEEEInt. Symp. on Circuits and Systems, May 2005, pp. 184–187
2 Yoo, S., Park, J., Lee, S., and Moon, U.: ‘A 2.5-V 10-b 120-MSample/sCMOS pipelined ADC based on merged-capacitor switching’, IEEETrans. Circuits Syst. II, 2004, 51, pp. 269–275
3 Chang, Y., Wang, C., and Wang, C.: ‘A 8-bit 500-KS/s low power SARADC for bio-medical applications’. IEEE Asian Solid-State CircuitsConf., 2007, Jeju, Korea, November 2007, pp. 228–231
4 Chen, Y., Tsukamoto, S., and Kuroda, T.: ‘A 9b 100MS/s 1.46 mWSAR ADC in 65 nm CMOS’. IEEE Asian Solid-State Circuits Conf.,Taipei, Taiwan, November 2009, pp. 145–148
5 Liu, C., Chang, S., Huang, G., and Lin, Y.: ‘A 0.92 mW 10-bit 50-MS/sSAR ADC in 0.13 mm CMOS process’. Symp. on VLSI Circuits Digestof Technical Papers, June 2009, pp. 236–237
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