40551 Logic Synthesis Optimization

Dr. Yaser M. Agami Khalifa

Fall 2004Lecture # 1

Contact Information

Dr. Yaser M. A. KhalifaLocation: REH 202Office Hours: MW 2:00 – 4:00 PMPhone: (845) 257-3764FAX: (845) 257-3730

E-mail: yaserma@engr.newpaltz.edu Website: www.engr.newpaltz.edu/~khalify

Course Description The aim of this course is to present automatic logic

synthesis techniques for computer-aided design (CAD) of very large-scale integrated (VLSI) circuits and systems.This course will broadly survey the state of the art, and give a detailed study of various problems, pertaining to the logic-level synthesis of VLSI circuits and systems, including: two-level Boolean network optimization, multi-level Boolean network optimization, technology mapping for library-based designs and field-programmable gate-array (FPGA) designs, and state-assignment and re-timing for sequential circuits. The course will also cover various representations of Boolean functions, such as binary decision diagrams

(BDDs), and discuss their applications in logic synthesis

Course Objectives To introduce students to basic optimization

techniques used in circuits design To introduce students to advanced tools and

techniques in digital systems design. These include Hardware Modeling and Compilation Techniques.

To introduce in details Logic-Level synthesis and optimization techniques for combinational and sequential circuits.

To introduce students to Library binding algorithms to achieve implementations with specific cell libraries.

Textbook De Micheli G.: “Synthesis and

Optimization of Digital Circuits”, McGraw Hill, 1994. 

Course Contents [1] Introductiona)      Semiconductor Technologies and Circuit Taxonomyb)      Design of Microelectronic Circuitsc)      Computer-Aided Synthesis and Optimization

[2] Optimization Algorithmsa)      Graph Theoryb)      Combinatorial Optimizationc)      Fundamental Algorithmsd)      Graph Optimization Algorithmse)      Boolean Algebra and Applications

      

Course Contents [3] Hardware Modelinga)      Hardware Modeling languagesb)      Abstract Modelsc)      Compilation and Behavioral Optimization

[4] Architecture Synthesisa)      Circuit Specifications for Architectural Synthesisb)      Fundamental Architectural Synthesis Problemsc)      Area and Performance Estimations

Course Contents [5] Two-Level Combinational Logic optimizationa)      Logic Optimization Principlesb)      Operations on Two-Level Logic Coversc)      Algorithms for Logic Minimizationd)      Symbolic Minimization and Encoding Problemse)      Minimization of Boolean Relations.

[6] Multi-Level Combinational Logic Optimizationa)      Models and Transformations for Combinational Networksb)      The Algebraic Modelc)      The Boolean Modeld)      Algorithms for Delay Evaluation and Optimizatione) Rule-based Systems for Logic Optimization

Course Contents [7] Sequential Logic Optimizationa)      Sequential Circuit optimization Using State-Based

Modelsb)      Sequential Circuit optimization Using Network Modelsc)      Implicit Finite-Stet Machine Traversal Methodsd)      Testability Considerations for Synchronous Circuits

[8] Cell-Library Bindinga)      Problem Formulation and Analysisb)      Algorithms for Library Bindingc)      Specific problems and Algorithms for Library Bindingd) Rule-Based Library Binding

Course Contents [9] State of the Art and Future Trends

Homework Approximately ten written

homework assignments will be given throughout the semester related to the concepts covered during the lectures. Each assignment must be turned in by the end of class on the scheduled due date.

Homework Submission of late work will be accepted by

the professor; however the maximum possible score will be scaled by the percentage shown in the following table.  

Homework in due time 100.0%One day late 75.0%Two days late 50.0%> Two days 0.0%

Special circumstances will be considered provided the professor is contacted before the due date.

Quizzes! Unannounced short (drop) quizzes

may be given during the class period from time to time. They may cover previous work or lectures.

Course Assessment

Project 10 %

Homework Assignments

20 %

Research Paper 10 %

Quizzes 10 %

Midterm Exams 20 %

Final Exam 30 %

Exam Dates

Midterm Exams

Wednesdays, October 13th, and November 17th

Final Exam TBA

Grading Policy

A > 90 %

B 80 % - 90 %

C 70 % - 80 %

F < 70 %