4) PIC IO Port Programming

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    PIC I/O Port ProgrammingChapter 3

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    PIC18F4550 Pin Diagram

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    I/O Ports on PIC18F4550 Consist of five ports:

    PORTA (RAx) 7 Pins

    PORTB (RBx) 8 Pins PORTC (RCx) 8 Pins - 3 SFRPORTx.

    PORTD (RDx) 8 Pins TRISx, and LATx

    PORTE (REx) 3 Pins

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    TRIS Register (TRIState)All the five ports can be used as either output or input.

    If TRISx = 0 ; PORTx = output

    If TRISx = 1 ; PORTx = input

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    Setting up the I/O PortsMOVLWB11110000

    MOVWFTRISB;RB7,RB6,RB5,RB4 AS INPUT;RB3,RB2,RB1,RB0 AS OUTPUT

    CLRFTRISB;clear all TRISB bits PORTB output

    SETFTRISC;set all TRISC bits PORTC input

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    Writing output bits to I/O PORTCLRFTRISB;set PORTB as output

    MOVLW0x55; W=01010101

    MOVWFPORTB;PORTB = 01010101

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    Reading input bits from I/O

    PORTSETFTRISC;set PORTC as input

    MOVFPORTC,W;get PORTC & move to W

    MOVWFMYREG;MYREG = 01010101

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    Study Example 4-1Write a test program for the PIC18 chip to toggle all the bits of PORTB,

    PORTC, and PORTD every of a sec. Assume crystal frequency is 4 MHz.#include

    R1 equ 0x07

    R2 equ 0x08

    ORG 0

    CLRF TRISB ;make Port B an output port

    CLRF TRISC ;make Port C an output port

    CLRF TRISD ;make Port D an output port

    MOVLW 0X55 ; WREG = 55h

    MOVWF PORTB ;put 55H to Port B pins

    MOVWF PORTC ;put 55H to Port C pins

    MOVWF PORTD ;put 55H to Port D pinsLOOP COMF PORTB, F;toggle bits of Port B

    COMF PORTC, F ;toggle bits of Port C

    COMF PORTD, F ;toggle bits of Port D

    CALL DELAY

    BRA LOOP

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    QDELAY

    MOVLWD 200

    MOVWFR1

    D1 MOVLWD 250MOVWFR1

    D2 NOP

    NOP

    DECF R2, FBNZD2

    DECFR1

    BNZD1

    RETURN

    END

    Inst Cycle Duration = 4/fosc = 1 Sec

    Delay = 250 X 200 X

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    I/O Bit Manipulation

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    BIT-ORIENTED OPERATIONS1. Some times, we are interested to access only 1 or 2 bits of the port insteadof the entire 8 bits.2. BIT Oriented operation are supporting to do the above things in PIC18

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    BSF(bit set fileReg)

    BCF(bit clear fileReg)Syntex:

    BSFfileReg, bit_numBCFfileReg, bit_num

    Example:

    BSFPORTD,2;Set bit RD2

    BCFPORTD,5;Clear bit RD5

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    Study Example:

    CLRFTRISD;Make PORT D an output

    BSFPORTD, 0 ; Bit set turns on RD 0CALL DELAY

    BSF PORTD,1 ; Bit set turns on RD 1

    CALL DELAY

    -----------------------------------------------------------------------------------------

    BCFTRISB, 2 ;bit = 0, make RB2 an output pinAGAIN BSFPORTB,2 ; bit set (RB2 = high)

    CALL DELAY

    BCFPORTB, 2 ; bit clear (RB2=low)

    CALL DELAY

    BRA AGAIN

    An LED is connected to each pin of PORT D. Write a program to turn oneach LED from pin D0 to pin D7. Call a delay module before turning on the

    next LED

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    Exercise 1Write a program to generate 1kHz square wave with80% duty cycle on bit3 of PORTC. Prepare theflowchart.

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    BTFSS(bit test fileReg, skip if set)

    BTFSC(bit test fileReg, skip if clear)

    In order to make a decision on based on the status of a

    given bit in the file register, we use the followinginstructions.

    BTFSS - to monitor the status of single bit HIGH

    BTFSC to monitor the status of single bit LOW

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    Example 4-4Write a program to perform the following:

    a)Keep monitoring the RB2 bit until it becomes HIGH

    b)When RB2 becomes HIGH, write value 45H toPORTC, and also send a HIGH-to-LOW pulse to RD3

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    Example 4-4 (Solution)BSF TRISB,2; RB2 as inputCLRFTRISC ; PORT C as output BCF PORTD,3 ; RD3 as output

    MOVLW0x45; WREG = 45h

    AGAINBTFSS PORTB,2 ; bit test RB2 for HIGH

    BRAAGAIN; Keep checking LOW

    MOVWFPORTC; issue WREG to Port C

    BSF PORTD,3; bit set file reg RD3 (H-L)

    BCFPORTD,3 ; bit clear file reg RD3 (L)

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    Example 4-5

    BSF TRISB,3BCF TRISC,5

    HERE BTFSC PORTB,3

    BRA HERE

    BSF PORTC,5

    BCF PORTC,5BRA HERE

    Assume RB3 is an input. If it goes LOW, it means that the door open.

    Monitor the bit continuously. Whenever it goes LOW, sent a HIGH-to-LOW

    pulse to port RC5.