4-BIT SINGLE CHIP MICROCOMPUTERS ADAM28PXX · 2019-08-30 · May 02, 2016 Ver. 1.4 3 Program memory...
Transcript of 4-BIT SINGLE CHIP MICROCOMPUTERS ADAM28PXX · 2019-08-30 · May 02, 2016 Ver. 1.4 3 Program memory...
4-BIT SINGLE CHIP MICROCOMPUTERS
ADAM28PXX USER`S MANUAL
May 02, 2016 Ver 1.4
• ADAM28P08
• ADAM28P16
• ADAM28P16T
1 May 02, 2016 Ver. 1.4
REVISION HISTORY
VERSION 0.0 (Dec. 16, 2013) Preliminary version
VERSION 0.1 (Arp. 25, 2014) Correct some errata
VERSION 1.0 (Aug. 30, 2014) Public release
VERSION 1.1 (Oct. 17, 2014) Change the Internal RC Oscillator tolerance and it’s condition
VERSION 1.2 (Dec. 15, 2014) Change the Calibration condition of Internal RC Oscillator
VERSION 1.3 (June 01, 2015) Add the typical value of the LVD
VERSION 1.4 (May 02, 2016) Add the 16-TSSOP Package
1. Overview ADAM28P16/08
Version 1.4
Published by FAE Team
ⓒ2013 ABOV Semiconductor Co., Ltd. All rights reserved.
Additional information of this manual may be served by ABOV Semiconductor offices in Korea or
Distributors.
ABOV Semiconductor reserves the right to make changes to any information here in at any time
without notice.
The information, diagrams and other data in this manual are correct and reliable; however, ABOV
Semiconductor is in no way responsible for any violations of patents or other rights of the third party
generated by the use of this manual.
2 May 02, 2016 Ver. 1.4
ADAM28P16/08 1. Overview
1. OVERVIEW 1.1 Features ................................................. 3 1.2 Block Diagram ............................................ 4 1.3 Pin Assignments .......................................... 4 1.4 Package Dimension ........................................ 5 1.5 Pin Function ............................................. 6 1.6 Pin Circuit .............................................. 7 1.7 Electrical Characteristics ............................... 8 2. ARCHITECTURE 2.1 Program Memory ........................................... 11 2.2 Address Register ......................................... 12 2.3 Data Memory & Special function register ................. 13 2.4 X-register ............................................... 13 2.5 Y-register ............................................... 14 2.6 Accumulator .............................................. 14 2.7 Arithmetic and Logic Unit ................................ 14 2.8 Clock Generator .......................................... 15 2.9 Timer .................................................... 15 2.10 Carrier Generator ....................................... 18 2.11 Pulse Generator ....................................... 19 2.12 Reset Operation ......................................... 19 2.13 STOP Operation .......................................... 21 2.14 Port Operation .......................................... 21 3. INSTRUCTION 3.1 Instruction Format ....................................... 22 3.2 Instruction Table ....................................... 23 3.3 Details of Instruction System ............................ 25 3.4 Guideline for S/W ........................................ 39 ※ APPENDIX -. OTP Programming ........................................... 40 -. Application Circuit of ADAM28P16/ADAM28P16T (T-Type) ...... 42 -. Application Circuit of ADAM28P08 (T-Type) ................. 42 -. Application Circuit of ADAM28P16/ADAM28P16T (M-Type) ...... 43 -. Application Circuit of ADAM28P08 (M-Type) ................. 43
Table of Contents
3 May 02, 2016 Ver. 1.4
■ Program memory (MTP)
● 3,072 Bytes (3,072 x 8bit)
● Multi Time Programming : 1K * 3, 1.5K * 2, 3K * 1
● Data Retention : > 10 years
■ Data memory (RAM)
● 32 nibble (32 x 4bit)
■ 3 levels of subroutine nesting
■ 8-bit Table Read Instruction
■ Oscillator Type
● Calibrated Internal RC Oscillator
■ Instruction cycle
● fOSC/6
■ Stop mode
■ Released stop mode by key input
■ Built in Power-on Reset circuit
■ Built in Transistor for I.R LED Drive
● IOL=250mA at VDD=3V and VO=0.3V
■ Built in Low Voltage reset circuit
■ Built in a watch dog timer (WDT)
■ One 8bit Timer with a auto reload register and overflow flag bit.
■ Carrier Frequency generator : 1820.00kHz ~ 7.11kHz
■ Voltage Detection Indicator Circuit : 2-Level [ 2.3V(±0.15V) / 1.9V(±0.1V) ]
■ Low operating voltage
● 1.8 ~ 3.6V
■ 16-SOP/TSSOP, 8-SOP Package.
1. OVERVIEW
The ADAM28PXX is remote control transmitter which uses CMOS technology.
The ADAM28PXX is suitable for remote control of TV, VCR, FANS, Air-conditioners,
Audio Equipments, Toys, Games etc. The ADAM28PXX is MTP version.
1.1. Features
Table 1.1 ADAM28PXX series members
1. Overview ADAM28PXX
Series ADAM28P16 ADAM28P16T ADAM28P08
Program memory 3,072 x 8 3,072 x 8 3,072 x 8
Data memory 32 x 4 32 x 4 32 x 4
I/O ports 13 13 5
Output ports 1 1 1
Package 16SOP(150mil) 16 TSSOP(4.4mm) 8SOP(150mil)
4 May 02, 2016 Ver. 1.4
1.2. Block Diagram
ADAM28PXX 1. Overview
ROUT
VDD GND
ADAM28
Core
RAM
(32 nibbles)
& SFR
Watchdog
Timer
Carrier
Generator
Key Scan
&
Input
Clock Gen.
&
System
Control
MTP (3K x 1)
(1.5K x 2)
(1K x 3)
K
Port
K0~K3
R0~R3
P0~P2
CS0~CS1
K0 ~ K3
Internal RC
Oscillator (3.64MHz)
R
Port
P
Port
CS
Port
R0 ~ R3
P0 ~ P2
CS0 ~ CS1
Timer (8Bit x 1ch)
5 May 02, 2016 Ver. 1.4
ADAM28PXX 1. Overview
1.3. Pin Assignments ( top view )
VDD
ROUT
CS0
P2
P1/ [SDA]
ADAM28P16
(16-SOP)
16
15
14
13
1
2
3
4
GND
CS1
K0
[SCK] /K1
K2 5
6
7
8
12
11
10
9
K3
[VPP] /R0
R1
P0
R3
R2
VDD
ROUT
CS0
P1/ [SDA]
ADAM28P08
(8-SOP)
8
7
6
5
1
2
3
4
GND
[SCK] /K1
[VPP] /R0
R1
VDD
ROUT
CS0
P2
P1/ [SDA]
ADAM28P16T
(16-TSSOP)
16
15
14
13
1
2
3
4
GND
CS1
K0
[SCK] /K1
K2 5
6
7
8
12
11
10
9
K3
[VPP] /R0
R1
P0
R3
R2
6 May 02, 2016 Ver. 1.4
1. Overview ADAM28PXX
16 SOP(150MIL) Pin Dimension (dimensions in millimeters)
1.4. Package Dimension
8 SOP (150MIL) Pin Dimension (dimensions in millimeters)
7 May 02, 2016 Ver. 1.4
1. Overview ADAM28PXX
0.650 ± 0.075
16 TSSOP (4.4mm) Pin Dimension (dimensions in millimeters)
8 May 02, 2016 Ver. 1.4
ADAM28PXX 1. Overview
1.5. Pin Function
PIN
NAME
INPUT
OUTPUT FUNCTION @RESET @STOP
K0 ~ K3
R0 ~ R3 I/O
-. 4-bit I/O port. (Input mode is set only when each of
them output `H`)
-. Each pin has STOP mode release function
in input mode.
-. Output mode is set when each of them output `L`.
-. When used as `output`, each pin can be set and
reset independently.
-. When set as the input mode, input state of pin is
read. At output mode, if port is read, data register
is read instead of the state of pin.
Input
(with Pull-up)
Key-Strobe
(at T-key Scan)
or
Keep status
Before STOP
(at M-key Scan)
P0 ~ P2 I/O
-. 3-bit I/O port. (Input mode is set only when each of
them output `H`)
-. Each pin has STOP mode release function
in input mode.
-. Output mode is set when each of them output `L`.
-. When used as `output`, each pin can be set and
reset independently.
-. When T-key Scan is disabled, P0~P2 are forcibly
Low output at STOP mode.
-. When set as the input mode, input state of pin is
read. At output mode, if port is read, data register
is read instead of the state of pin.
Input
(with Pull-up)
Key-Strobe
(at T-key Scan)
or
Low
(at M-key Scan)
CS0~CS1 I/O
-. 2-bit I/O port. (Input mode is set only when each of
them output `H` and pull-up is enabled.)
-. Pull-ups can be enabled by user program.
-. Each pin has STOP mode release function
in input mode (when it’s pull-up is enabled)
-. Output mode is set when each of them output `L`,
or when it’s pull-up is disabled.
-. When used as `output`, each pin can be set and
reset independently.
-. When set as the input mode, input state of pin is
read. At output mode, if port is read, data register
is read instead of the state of pin.
Hi-Z
Key-Strobe
(at T-key Scan)
or
Keep status
before STOP
ROUT Output -. High Current Pulse Output.
-. N-ch open drain output. Hi-Z Hi-Z
VDD Power -. Positive power supply. - -
GND Power -. Ground - -
9 May 02, 2016 Ver. 1.4
1. Overview ADAM28PXX
1.6. Pin Circuit
Pin Name I/O I/O circuit Note
CS0
CS1 I/O
- CMOS I/O port.
- Open drain output at reset.
- Built in MOS Tr. for pull-up.
It can be enabled by user
program.
- In M-key scan mode, they
keep the status before STOP
at Stop Mode.
- In T-key scan mode, they do
key-strobe at STOP Mode.
ROUT O
- Open drain output
- Output Tr. Disable at
reset and Stop Mode.
P0 ~ P2 I/O
- CMOS I/O port.
- Input mode with pull-up
at reset.
- Built in MOS Tr. for pull-up.
- In M-key scan mode, they
are `L` output at Stop Mode.
- In T-key scan mode, they do
key-strobe at STOP Mode.
K0 ~ K3
R0 ~ R3 I/O
- CMOS I/O port.
- Input mode with pull-up
at reset.
- Built in MOS Tr. for pull-up.
- In M-key scan mode, they
keep the status before STOP
at Stop Mode.
- In T-key scan mode, they do
key-strobe at STOP Mode.
VDD Pull up
resistor
PAD
Pull-up disable VDD
GND
ROUT
PAD
GND
VDD
GND
VDD
Pull up
resistor
PAD
VDD
GND
* R0 has no P-Protection .
10 May 02, 2016 Ver. 1.4
ADAM28PXX 1. Overview
1.7. Electrical Characteristics
* Thermal derating above 25℃ : 6mW per degree ℃ rise in temperature.
1.7.1. Absolute Maximum Ratings (Ta = 25℃)
Parameter Symbol Max. rating Unit
Supply Voltage VDD -0.3 ~ 4.0 V
Power dissipation PD 700 * ㎽
Input voltage VIN -0.3 ~ VDD+0.3 V
Output voltage VOUT -0.3 ~ VDD+0.3 V
Storage Temperature TSTG -65 ~ 150 ℃
1.7.2. Recommended operating condition
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply Voltage VDD fOSC = 3.64MHz 1.8 - 3.6 V
Oscillation Frequency fOSC
VDD=1.8 ~ 3.6V
Temp. = -10 ~ 50℃
3.604 *
(-1.0%) 3.640
3.677 *
(+1.0%) MHz
VDD=1.8 ~ 3.6V
Temp. = -20 ~ 70℃
3.585
(-1.5%) 3.640
3.695
(+1.5%) MHz
Operating temperature Topr - -20 - 70 ℃
PARAMETER Symbol Condition Specification
UNIT MIN. TYP. MAX.
High level
input voltage VIH K, R, P, CS 0.7VDD VDD V
Low level
input voltage VIL K, R, P, CS 0 0.3VDD V
High level input
leakage current IIH K, R, P, CS VIH = VDD 1 ㎂
High level output
leakage current IOLK K, R, P, CS, ROUT VOH = VDD 1 ㎂
Low level
output current
IOL1 K, R, P, CS VDD = 3V
VOL = 0.6V 5 10 - ㎃
IOL2 ROUT VDD = 3V
VOL = 0.3V - 250 - ㎃
Input Pull-up
Resistance RPU K, R, P, CS VDD =3V 70 140 210 ㏀
Power
supply
current
IDD Operating
current
fosc =
3.64MHz
VDD = 3.6V 0.7 1.5 ㎃
VDD = 1.8V 0.3 0.6 ㎃
ISTOP Stop mode
current
Oscillator
stop
VDD = 3.6V 0.3 1.0 ㎂
VDD = 1.8V 0.2 0.5 ㎂
LVD Detection
Voltage VLVD 1.2 1.5 1.8 V
1.7.3. DC Characteristics (Ta = -20 ~ 70℃, VDD=1.8 ~ 3.6V, GND=0V )
* Guaranteed by design, but might be On-Board programming after SMT process.
( IRC Calibration with high temperature can cause the shift of the frequency, be sure to calibrate enough to
cool to near room temperature after SMT process. )
11 May 02, 2016 Ver. 1.4
1. Overview ADAM28PXX
※ Internal RC Oscillator Characteristics Graphs (for reference only)
12 May 02, 2016 Ver. 1.4
This graphs provided in this section are for design guidance only and are not tested or guaranteed.
The data presented in this section is a statistical summary of data collected on units from different lots over
a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean +
3σ) and (mean – 3σ) respectively where σ is standard deviation.
※ Typical Characteristics
▶ IOL vs. VOL (at T=25℃) for ROUT Port with built in Transistor.
0
200
400
600
800
1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0
IOL[m
A]
VOL[V]
VCC=3.0VTa=25℃
ADAM28PXX 1. Overview
13 May 02, 2016 Ver. 1.4
2. ARCHITECTURE
The ADAM28PXX can incorporate maximum 3,072 words (3 Block × 16 pages × 64 words
× 8bits) for program memory. Program counter PC (A0~A5), page address register
PA(A6~A9) and Block address register BA(A10~A11) are used to address the whole area of
program memory having an instruction (8bits) to be next executed.
The program memory consists of 64 words on each page, and thus each page can hold up to
64 steps of instructions.
The program memory is composed as shown below.
2.1. Program Memory
ADAM28PXX 2. Architecture
Block2
Fig 2-1 Configuration of Program Memory
Program counter (PC)
Page address register (PA)
10 1
(Level `1`)
(Level `2`)
(Level `3`)
Stack register (SR)
A0~A9
0 1
A10~A11
10
Page buffer (PB) 4 Block address register (BA) Block buffer (BB) 2
Block1
Block0
(16pages x 64words x 8bit)
Y-register (Y)
2 Y0~Y1
2
14 May 02, 2016 Ver. 1.4
2.2. Address Register
The following registers are used to address the ROM.
• Block address register (BA) :
Holds ROM's Block number (0~2h) to be addressed.
• Block buffer register (BB) :
Value of BB is loaded by an LBBY command when newly addressing a block.
Then it is shifted into the BA when rightly executing a branch instruction (BR)
and a subroutine call (CAL).
• Page address register (PA) :
Holds ROM's page number (0~Fh) to be addressed.
• Page buffer register (PB) :
Value of PB is loaded by an LPBI command when newly addressing a page.
Then it is shifted into the PA when rightly executing a branch instruction (BR)
and a subroutine call (CAL).
• Program counter (PC) :
Available for addressing word on each page.
• Stack register (SR) :
Stores returned-word address in the subroutine call mode.
ADAM28PXX 2. Architecture
2.2.1. Page address register and page buffer register :
Address one of pages #0 to #15 in the ROM by the 4-bit binary counter.
Unlike the program counter, the page address register is usually unchanged so
that the program will repeat on the same page unless a page changing command
is issued. To change the page address, take two steps such as
(1) writing in the page buffer what page to jump (execution of LPBI) and
(2) execution of BR or CAL, because instruction code is of eight bits so that page
and word can not be specified at the same time.
In case a return instruction (RTN) is executed within the subroutine that has been
called in the other page, the page address will be changed at the same time.
2.2.2. Program counter : This 6-bit binary counter increments for each fetch to address a word in the
currently addressed page having an instruction to be next executed.
For easier programming, at turning on the power, the program counter is
reset to the zero location. The PA is also set to `0`. Then the program
counter specifies the next address in random sequence.
When BR, CAL or RTN instructions are decoded, the switches on each step
are turned off not to update the address. Then, for BR or CAL, address
data are taken in from the instruction operands (a0 to a5), or for RTN, and
address is fetched from stack register No. 1.
15 May 02, 2016 Ver. 1.4
Up to 32 nibbles (16 words × 2pages × 4bits) is incorporated for storing data at data memory. The whole data memory is indirectly specified by a data pointer (X,Y). Page
number is specified by value of X register, and words in the page by 4 bits in
Y-register. Data memory is composed in 16 nibbles/page. The SFR area is also
Specified by a data pointer(X,Y) where X register should be set to 3.
Figure 2-2 shows the configuration.
Fig 2-2 Composition of Data Memory
2.3. Data Memory (RAM) and Special function register (SFR)
X-register is consist of 2bit(X1,X0), X is a data pointer of page in the RAM/SFR, and X is used for selecting the input/output of K, R, P, CS Ports with value of Y-register for port access. LVI bits can be read by LAR and setting X=2. the 2’nd bit of A is LVD19(0 if VDD>1.9v, 1 if VDD<1.9v) and 3’rd bit is LVD23(0 if VDD>2.3v, 1 if VDD<2.3v)
Table2-1 Mapping table between X and Y register for port access
2.4. X-register (X)
X = 0 or 1 X = 2
Input
Data
LAK (Instruction) A K0~K3 A P0~P2
LAR (Instruction) A R0~R3 A {CS0,CS1,LVI19,LVI23}
Output
Data
Y=0h~3h K0~K3 P0~P2
Y=4h~7h R0~R3 CS0~CS1
ADAM28PXX 2. Architecture
2.2.3. Stack register : This stack register provides three stages each for the program counter (6bits)
and the page address register (4bits) so that subroutine nesting can be made
on three levels.
0 1
2 3
15
Output port
Y-register (Y) X-register (X)
K ROUT
Page 0
(RAM)
Page 1
(RAM)
0 or 2 1 4
Data memory (page 0~1) and SFR (page 3)
A0~A3
R P CS
Page 3
(SFR)
3
16 May 02, 2016 Ver. 1.4
2.6. Accumulator (ACC) The 4-bit register for holding data and calculation results.
2.7. Arithmetic and Logic Unit (ALU) In this unit, 4bits of adder/comparator are connected in parallel as it's main
components and they are combined with status latch and status logic (flag.)
2.7.1. Operation circuit (ALU) :
The adder/comparator serves fundamentally for full addition and data
comparison. It executes subtraction by making a complement by processing
an inversed output of ACC (ACC+1)
2.7.2. Status logic :
This is to bring an ST, or flag to control the flow of a program. It occurs when
a specified instruction is executed in three cases such as overflow or underflow
in operation and two inputs unequal.
Y-register has 4 bits. It operates as a data pointer or a general-purpose register.
Y-register specifies an address (A0~A3) in a page of data memory and SFR, as well
as it is used to specify an output port. Further it is used to specify a mode of carrier
signal outputted from the ROUT port. It can also be treated as a general-purpose
register on a program.
2.5. Y-register (Y)
ADAM28PXX 2. Architecture
17 May 02, 2016 Ver. 1.4
2.9. Timer The ADAM28PXX has the programmable timer. The programmable timer has a reload
register. It is incremented from a setting value n. When it overflow (count to n+1), a timer
overflow flag is set to “1”, new data is loaded from the reload register, and count
continues (auto-reload function). The content value of timer can’t be read by program.
Because the interrupt isn’t provided, using polling the flag(T0F) of timer is only the way
to check out overflow.
Timer execution is stopped and the value of counter is cleared at RESET mode and
STOP mode. T0F is reset at RESET mode and STOP mode and T0CS rising Edge.
T0F is set by T0 counter overflow.
ADAM28PXX 2. Architecture
2.8. Clock Generator The ADAM28PXX has an internal RC oscillator which has 3.64MHz frequency only.
The oscillator circuit is designed to operate without an external ceramic resonator.
The Internal Oscillator is calibrate in Factory. In STOP mode, Internal oscillator is
stopped.
Fig 2-3 Block Diagram of Timer0 in 8-bit timer/counter
CCR
[R/W ]
T0F
TIMER0
HIGH
DATA
BUFFER
TIMER0
L0W
DATA
BUFFER
3 2 1 0
TCK
FLAG
GEN.
fosc/48 Counter
Overflow
(8)
T0CS
auto-re load
Flag Check by Instruction
(TM CCR.3)
(8)
TIMER0
HIGH
DATA
REG
TIMER0
L0W
DATA
REG
T0 COUNTER
(8 BIT)
LMA or LAMIY or LMIIY
(4) (4)
(X=3,Y=3) (X=3,Y=2)
1
0
T0
CS
T0
F
fosc/6
T0
CK
S
CC
R0
set
reset
fosc = 3.64MHz
Resolution (TCK) Max. Count
TCK0 : 1.648us (freq = fosc/6) 422us
TCK1 : 13.19us (freq = fosc/48) 3,376us
2.9.1. Timer 0 Resolution & Max. Count
18 May 02, 2016 Ver. 1.4
Register Address @RESET Usable
command Remarks
T0D1 Xreg = 3
Yreg = 2 Fh
LMA
LMAIY
LMIIY
Timer0 Data Register
= {T0D1,T0D0} T0D0
Xreg = 3
Yreg = 3
CCR Xreg = 3
Yreg = 8 0h
LMA
LMAIY
LMIIY
SEM
REM
TM
If CCR[0]=0, Select ROUT by PMR Data
If CCR[0]=1, Select ROUT by Carrier Data
ADAM28PXX 2. Architecture
CCR
3 2 1 0 Address :
Xreg=3
Yreg=8
2.9.4. Counter Control Register (CCR)
T0F T0CS T0CK CCR0
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W
bit
T0F Timer0 overflow Flag 0 Timer0 overflow is not occurred
1 Timer0 overflow is occurred
T0CS Timer0 Stop / Start
Control
0 Timer0 Stop
1 Timer0 Clear and Start
T0CK Input clock selection 0 fosc/6 (TCK =1.648us)
1 fosc/48 (TCK =13.19us)
CCR0 Carrier Control Bit 0 0 Select ROUT by PMR Data
1 Select ROUT by Carrier Data
T0D1
3 2 1 0 Address :
Xreg=3
Yreg=2
2.9.2. Timer 0 Data Register 1 (T0D1)
T0D13 T0D12 T0D11 T0D10
1
W
1
W
1
W
1
W
Initial Value
R/W
bit
T0D0
3 2 1 0 Address :
Xreg=3
Yreg=3
2.9.3. Timer 0 Data Register 0 (T0D0)
T0D03 T0D02 T0D01 T0D00
1
W
1
W
1
W
1
W
Initial Value
R/W
bit
19 May 02, 2016 Ver. 1.4
ADAM28PXX 2. Architecture
Fig 2-5 Operation of Timer0 in 8-bit timer/counter mode
Fig 2-6 Start / Stop operation of Timer0 in 8-bit timer/counter mode
Fig 2-4 Timing Chart of Timer0 in 8-bit timer/counter mode
Clock
1 0 2 4 6 n n 0 Counter
T0D1
+T0D0 - -
T0OVF
n
Match Clear
T0CS T0D1+T0D0
3 5
T0F
(CCR.3)
n+1
T0OVF
T0CS
T0F
(CCR.3)
0 1
Clear
&
Start
Stop Clear
&
Start
Clear
&
Start
Concurrence
Clear
T0 Data
Registers
Value
Concurrence
T0 Value
0 Clear
Counter Count Clear
&
Start
REM CCR.3 (instruction)
Set Reset Set Reset
Clear
T0 Data Reg. Value
Interval period
(n+1 count)
T0 Value
0 Clear Clear
T0OVF
(T0D1+T0D0) (T0D1+T0D0) (T0D1+T0D0)
T0F
(CCR.3) Set Set Set
20 May 02, 2016 Ver. 1.4
Register Address @RESET Usable
command Remarks
CDRH1 Xreg = 3
Yreg = 4
Fh LMA
LMAIY
LMIIY
Carrier High period, T1 = {CDRH1,CDRH0}
determination.
(first compare) CDRH0 Xreg = 3
Yreg = 5
CDRL1 Xreg = 3
Yreg = 6 Carrier Low period, T2 = {CDRL1,CDRL0}
determination. CDRL0
Xreg = 3
Yreg = 7
CCR Xreg = 3
Yreg = 8 0h
If CCR[0]=0, Select ROUT by PMR Data
If CCR[0]=1, Select ROUT by Carrier Data
2.10. Carrier Generator The following low or high pulse width are selected for carrier signal outputted from
the ROUT port depending on a carrier data High register(CDRH1:CDRH0) value and
carrier data Low register(CDRL1:CDRL0) set in a program.
T
T1
< ROUT Port Output >
T2
Below table show a few ROUT port example by compare data reg. value when fosc is 3.64MHz.
The number of pulse can be made as many kind as 65,536 (256 * 256) by carrier generator.
CDRH
{CDRH1,CDRH0}
CDRL
{CDRL1,CDRL0} T1 (us) T2 (us) Total (us) Freq. (kHz)
0 0 0.2747 0.2747 0.5495 1820.00
0 1 0.27 0.55 0.82 1213.33
0 2 0.27 0.82 1.10 910.00
0 3 0.27 1.10 1.37 728.00
30 32 8.52 9.07 17.58 56.88
43 43 12.09 12.09 24.18 41.36
45 44 12.64 12.36 25.00 40.00
31 63 8.79 17.58 26.37 37.92
47 47 13.19 13.19 26.37 37.92
33 66 9.34 18.41 27.75 36.04
33 67 9.34 18.68 28.02 35.69
255 252 70.33 69.51 139.84 7.15
255 253 70.33 69.78 140.11 7.14
255 254 70.33 70.05 140.38 7.12
255 255 70.33 70.33 140.66 7.11
ADAM28PXX 2. Architecture
21 May 02, 2016 Ver. 1.4
2.12. Reset Operation ADAM28PXX has three reset sources. One is a built-in Low VDD Detection circuit,
another is the overflow of Watch Dog Timer (WDT), the other is the overflow of Stack.
All reset operations are internal in the ADAM28PXX.
2.12.1 Built-in Low VDD Reset Circuit ADAM28PXX has a Low VDD detection circuit.
If VDD becomes Reset Voltage of Low VDD detection circuit in a active status,
system reset occur and WDT is cleared.
When VDD is increased over Reset Voltage again, WDT is re-counted until WDT
overflow, system reset is released.
ADAM28PXX 2. Architecture
2.11. Pulse Generator The following frequency and duty ratio are selected for carrier signal outputted from
the ROUT port depending on a PMR (Pulse Mode Register) value set in a program.
* Default value is `0`
Table 2-2 PMR selection table
PMR ROUT Signal Carrier Frequency
(fOSC = 3.64MHz)
0 T = 1/fPUL = [ 96/fOSC ], T1/T = 1/2 37.92 kHz
1 T = 1/fPUL = [ 96/fOSC ], T1/T = 1/3 37.92 kHz
2 T = 1/fPUL = [ 64/fOSC ], T1/T = 1/2 56.88 kHz
3 T = 1/fPUL = [ 64/fOSC ], T1/T = 1/4 56.88 kHz
4 T = 1/fPUL = [ 88/fOSC ], T1/T = 4/11 41.36 kHz
5 No Pulse (same to P0~P2) -
6 T = 1/fPUL = [ 101/fOSC ], T1/T = 34/101 36.04 kHz
7 T = 1/fPUL = [ 91/fOSC ], T1/T = 31/91 40.00 kHz
T
T1
< ROUT Port Output >
22 May 02, 2016 Ver. 1.4
2.12.2 Watch Dog Timer (WDT) Watch dog timer is organized binary of 14 steps. The signal of fOSC/48 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically comes out so that internal circuit is initialized.
The overflow time is 8×6×213/fOSC (108.026ms at fOSC = 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR), Power-on reset pulse or Low VDD detection pulse.
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted. ( Refer to 2.13. STOP Operation)
Fig 2-8 Block Diagram of Watch-dog Timer
Binary counter(14 steps)
Reset by instruction
(WDTR)
fOSC/48
Power-On Reset
Stop Mode
1 2 3 4 5 6 7 8 9 10 11 12 13 14 CPU reset
1
RESET (edge-trigger)
ADAM28PXX 2. Architecture
Fig 2-7 Low Voltage Detection Timing Chart.
VDD
Reset Voltage
about 108msec at fOSC = 3.64MHz
Internal
RESETB
23 May 02, 2016 Ver. 1.4
2.13. STOP Operation
Stop mode can be achieved by STOP instructions.
In stop mode :
1. Oscillator is stopped, the operating current is low.
2. Watch dog timer, timer0 is reset and ROUT output is `High-Z` .
3. Part other than WDT and ROUT output have a value before come into stop mode.
4. P0~P2 are outputted successively T-Key Scan when T-Key Scan mode is
enabled, but when M-Key Scan mode is enabled, they output Low forcibly.
5. All of K, R, CS is outputted successively T-Key Scan when T-Key Scan mode is
enabled, but when M-Key Scan mode is enabled, It keeps the status before STOP.
6. At T-Key Scan mode, before entering the STOP mode, All of K, R, P and CS must
be set the input mode with pull-up.
Stop mode is released when one of K or R or P or CS input is going to `Low`.
When stop mode released :
1. State of K, R, P, CS output and ROUT output is return to state of before stop mode
is achieved.
2. After 8×6×210/fOSC time for stable oscillating, first instruction start to operate.
3. In return to normal operation, WDT is counted from zero.
When executing stop instruction, if any one of K,R,P,CS input is `Low` state,
stop instruction is same to NOP instruction.
2.14. Port Operation
Value of
X-reg
Value of
Y-reg Operation
0 or 1
0h~3h SO : K[Y] 1 (Pull-up) RO : K[Y] 0
4h~7h SO : R[Y-4] 1 (Pull-up) RO : R[Y-4] 0
2
0h~3h SO : P[Y] 1 (Pull-up) RO : P[Y] 0
4h~7h SO : CS[Y-4] 1 (Pull-up or Hi-Z) RO : CS[Y-4] 0
0 or 1
or 2
8h SO : ROUT(PMR) 0 RO : ROUT 1 (High-Z)
9h SO : All of K, R 1 RO : All of K, R 0
Ah~Bh SO : CS[Y-10] Pull-up disable
T-Key Mode disable for CS
RO : CS[Y-10] Pull-up enable
T-Key Mode enable for CS
Eh SO : T-Key Scan enable RO : M-Key Scan enable
Fh SO : All of K,R,P 1 RO : All of K,R,P 0
ADAM28PXX 2. Architecture
24 May 02, 2016 Ver. 1.4
3.1. Instruction Format All of the 43 instruction in ADAM28PXX is format in two fields of OP code and operand which consist of eight bits. The following formats are available with different types of operands. *FormatⅠ All eight bits are for OP code without operand. *FormatⅡ Two bits are for operand and six bits for OP code. Two bits of operand are used for specifying bits of RAM and X-register (bit 1 and bit 7 are fixed at ″0″) *FormatⅢ Four bits are for operand and the others are OP code. Four bits of operand are used for specifying a constant loaded in RAM or Y- register, a comparison value of compare command, or page addressing in ROM. *Format Ⅳ Six bits are for operand and the others are OP code. Six bits of operand are used for word addressing in the ROM.
3. INSTRUCTION
ADAM28PXX 3. Instruction
25 May 02, 2016 Ver. 1.4
3.2. Instruction Table
The ADAM28PXX provides the following 43 basic instructions.
Category
1
2
3
Register to
Register
LAY
LYA
LAZ
Mnemonic
A ← Y
Function
Y ← A
A ← 0
S
S
S
ST*1
4
5
6 RAM to
Register
LMA
LMAIY
LYM
M(X,Y) ← A
M(X,Y) ← A, Y ← Y+1
Y ← M(X,Y)
S
S
S
7
8
LAM
XMA
A ← M(X,Y)
A ↔ M(X,Y)
S
S
9
10
11
Immediate
LYI i
LMIIY i
LXI n
Y ← i
M(X,Y) ← i, Y ← Y+1
X ← n
S
S
S
12
13
14
RAM Bit
Manipulation
SEM n
REM n
TM n
M(n) ← 1
M(n) ← 0
TEST M(n) = 1
S
S
E
15
16
17 ROM
Address
BR a
CAL a
RTN
if ST = 1 then Branch
if ST = 1 then Subroutine call
Return from Subroutine
S
S
S
18 LPBI i PB ← i S
21
22
23
Arithmetic
AM
SM
IM
A ← M(X,Y) + A
A ← M(X,Y) - A
A ← M(X,Y) + 1
C
B
C
24
25
DM
IA
A ← M(X,Y) - 1
A ← A + 1
B
S
26
27
IY
DA
Y ← Y + 1
A ← A - 1
C
B
19 LBBY BB ←Y S
20 LDWAY AY ← [@XAY] S
ADAM28PXX 3. Instruction
26 May 02, 2016 Ver. 1.4
Note) i = 0~f, n = 0~3, a = 6bit PC Address
*1 Column ST indicates conditions for changing status. Symbols have the following
meanings
S : On executing an instruction, status is unconditionally set.
C : Status is only set when carry or borrow has occurred in operation.
B : Status is only set when borrow has not occurred in operation.
E : Status is only set when equality is found in comparison.
N : Status is only set when equality is not found in comparison.
Z : Status is only set when the result is zero.
*2 Refer to 2.13. Port Operation.
Category
28
29
30
Arithmetic
DY
EORM
NEGA
Mnemonic
Y ← Y - 1
Function
B
S
Z
ST*1
A ← A + M (X,Y)
A ← A + 1
31
32
Comparison
ALEM
ALEI i
TEST A ≤ M(X,Y)
TEST A ≤ i
E
E
33
34
MNEZ
YNEA
TEST M(X,Y) ≠ 0
TEST Y ≠ A
N
N
35 YNEI i TEST Y ≠ i N
36
37 Input /
Output
LAK
LAR
A ← K (if X=0 or 1), A ← P (if X=2)
A ← R (if X=0 or 1), A ← CS (if X=2)
S
S
38
39
SO
RO
Output(Y) ← 1*2
Output(Y) ← 0*2
S
S
40
41 Control
WDTR
STOP
Watch Dog Timer Reset
Stop operation
S
S
42
43
LPY
NOP
PMR ← Y (if CCR0=0)
CDRH/CDRL ← M (if CCR0=1)
No operation
S
S
ADAM28PXX 3. Instruction
27 May 02, 2016 Ver. 1.4
3.3. Details of Instruction System All 43 basic instructions of the ADAM28PXX are one by one described in detail below. Description Form Each instruction is headlined with its mnemonic symbol according to the instructions table given earlier. Then, for quick reference, it is described with basic items as shown below. After that, detailed comment follows.
• Items : - Naming : Full spelling of mnemonic symbol - Status : Check of status function - Format : Categorized into Ⅰ to Ⅳ - Operand : Omitted for Format Ⅰ - Function
ADAM28PXX 3. Instruction
28 May 02, 2016 Ver. 1.4
(1) LAY
Naming : Load Accumulator from Y-Register
Status : Set
Format : I
Function : A ← Y
<Comment> Data of four bits in the Y-register is unconditionally transferred
to the accumulator. Data in the Y-register is left unchanged.
(2) LYA
Naming : Load Y-register from Accumulator
Status : Set
Format : I
Function : Y ← A
<Comment> Load Y-register from Accumulator
(3) LAZ
Naming : Clear Accumulator
Status : Set
Format : I
Function : A ← 0
<Comment> Data in the accumulator is unconditionally reset to zero.
(4) LMA
Naming : Load Memory from Accumulator
Status : Set
Format : I
Function : M(X,Y) ← A
<Comment> Data of four bits from the accumulator is stored in the RAM
location addressed by the X-register and Y-register. Such
data is left unchanged.
(5) LMAIY
Naming : Load Memory from Accumulator and Increment Y-Register
Status : Set
Format : I
Function : M(X,Y) ← A, Y ← Y+1
<Comment> Data of four bits from the accumulator is stored in the RAM
location addressed by the X-register and Y-register. Such
data is left unchanged.
ADAM28PXX 3. Instruction
29 May 02, 2016 Ver. 1.4
(6) LYM
Naming : Load Y-Register form Memory
Status : Set
Format : I
Function : Y ← M(X,Y)
<Comment> Data from the RAM location addressed by the X-register and
Y-register is loaded into the Y-register. Data in the memory is
left unchanged.
(7) LAM
Naming : Load Accumulator from Memory
Status : Set
Format : I
Function : A ← M(X,Y)
<Comment> Data from the RAM location addressed by the X-register and
Y-register is loaded into the Y-register. Data in the memory is
left unchanged.
(8) XMA
Naming : Exchanged Memory and Accumulator
Status : Set
Format : I
Function : M(X,Y) ↔ A
<Comment> Data from the memory addressed by X-register and Y-register
is exchanged with data from the accumulator. For example,
this instruction is useful to fetch a memory word into the
accumulator for operation and store current data from the
accumulator into the RAM. The accumulator can be restored
by another XMA instruction.
(9) LYI i
Naming : Load Y-Register from Immediate
Status : Set
Format : Ⅲ
Operand : Constant 0 ≤ i ≤ 15
Function : Y ← i
<Purpose> To load a constant in Y-register. It is typically used to specify
Y-register in a particular RAM word address, to specify the
address of a selected output line, to set Y-register for
specifying a carrier signal outputted from OUT port, and to
initialize Y-register for loop control. The accumulator can be
restored by another XMA instruction.
<Comment> Data of four bits from operand of instruction is transferred to
the Y-register.
ADAM28PXX 3. Instruction
30 May 02, 2016 Ver. 1.4
(10) LMIIY i
Naming : Load Memory from Immediate and Increment Y-Register
Status : Set
Format : Ⅲ
Operand : Constant 0 ≤ i ≤ 15
Function : M(X,Y) ← i, Y ← Y + 1
<Comment> Data of four bits from operand of instruction is stored into the
RAM location addressed by the X-register and Y-register.
Then data in the Y-register is incremented by one.
(11) LXI n
Naming : Load X-Register from Immediate
Status : Set
Format : Ⅱ
Operand : X file address 0 ≤ n ≤ 3
Function : X ← n
<Comment> A constant is loaded in X-register. It is used to set X-register in
an index of desired RAM page. Operand of 1 bit of command
is loaded in X-register.
(12) SEM n
Naming : Set Memory Bit
Status : Set
Format : Ⅱ
Operand : Bit address 0 ≤ n ≤ 3
Function : M(X,Y,n) ← 1
<Comment> Depending on the selection in operand of operand, one of four
bits is set as logic 1 in the RAM memory addressed in
accordance with the data of the X-register and Y-register.
(13) REM n
Naming : Reset Memory Bit
Status : Set
Format : Ⅱ
Operand : Bit address 0 ≤ n ≤ 3
Function : M(X,Y,n) ← 0
<Comment> Depending on the selection in operand of operand, one of four
bits is set as logic 0 in the RAM memory addressed in
accordance with the data of the X-register and Y-register.
ADAM28PXX 3. Instruction
31 May 02, 2016 Ver. 1.4
(14) TM n
Naming : Test Memory Bit
Status : Comparison results to status
Format : Ⅱ
Operand : Bit address 0 ≤ n ≤ 3
Function : M(X,Y,n) ← 1?
ST ← 1 when M(X,Y,n)=1, ST ← 0 when M(X,Y,n)=0
<Purpose> A test is made to find if the selected memory bit is logic. 1
Status is set depending on the result.
(15) BR a
Naming : Branch on status 1
Status : Conditional depending on the status
Format : Ⅳ
Operand : Branch address a (Addr)
Function : When ST =1 : BA ← BB, PA ← PB, PC ← a (Addr)
When ST = 0 : PC ← PC + 1, ST ← 1
Note : PC indicates the next address in a fixed sequence that
is actually pseudo-random count.
<Purpose> For some programs, normal sequential program execution
can be change.
A branch is conditionally implemented depending on the
status of results obtained by executing the previous
instruction.
<Comment> Branch instruction is always conditional depending on the status.
a. If the status is reset (logic 0), a branch instruction is not
rightly executed but the next instruction of the sequence is executed.
b. If the status is set (logic 1), a branch instruction is executed as
follows.
Branch is available in two types - short and long. The former
is for addressing in the current page and the latter for
addressing in other block/page.
Which type of branch to execute is decided according to the BB and PB
register. To execute a long branch, data of the BB or PB register should
in advance be modified to a desired block/page address through the
LBBY or LPBI instruction.
ADAM28PXX 3. Instruction
32 May 02, 2016 Ver. 1.4
(16) CAL a
Naming : Subroutine Call on status 1
Status : Conditional depending on the status
Format : Ⅳ
Operand : Subroutine code address a (Addr)
Function : When ST =1 :
PC ← a (Addr) PA ← PB BA ← BB
SR1 ← PC + 1 PSR1 ← PA BSR1 ← BA
SR2 ← SR1 PSR2 ← PSR1 BSR2 ← BSR1
SR3 ← SR2 PSR3 ← PSR2 BSR3 ← BSR2
When ST = 0 :
PC ← PC + 1 PA ← PA BA ← BA ST ← 1
Note : PC actually has pseudo-random count against the next instruction.
<Comment> In a program, control is allowed to be transferred to a mutual
subroutine. Since a call instruction preserves the return
address, it is possible to call the subroutine from different
locations in a program, and the subroutine can return control
accurately to the address that is preserved by the use of the
call return instruction (RTN).
Such calling is always conditional depending on the status.
a. If the status is reset, call is not executed.
b. If the status is set, call is rightly executed.
The subroutine stack (SR) of three levels enables a subroutine to be
manipulated on three levels. Besides, a long call (to call another page)
can be executed on any level.
For a long call, LBBY or LPBI instruction should be executed before
the CAL. When LBBY or LPBI is omitted (and when BA=BB and PA=PB),
a short call (calling in the same page) is executed.
(17) RTN
Naming : Return from Subroutine
Status : Set
Format : Ⅰ
Function : PC ← SR1 PA, PB ← PSR1 BA, BB ← BSR1
SR1 ← SR2 PSR1 ← PSR2 BSR1 ← BSR2
SR2 ← SR3 PSR2 ← PSR3 BSR2 ← BSR3
SR3 ← SR3 PSR3 ← PSR3 BSR3 ← BSR3
ST ← 1
<Purpose> Control is returned from the called subroutine to the calling
program.
<Comment> Control is returned to its home routine by transferring to the
PC the data of the return address that has been saved in the stack
register (SR1).
At the same time, data of the page stack register (PSR1) is
transferred to the PA and PB, and data of the block stack register(BSR1)
is transferred to the BA and BB.
ADAM28PXX 3. Instruction
33 May 02, 2016 Ver. 1.4
(18) LPBI i
Naming : Load Page Buffer Register from Immediate
Status : Set
Format : Ⅲ
Operand : ROM page address 0 ≤ i ≤ 15
Function : PB ← i
<Purpose> A new ROM page address is loaded into the page buffer
register (PB).
This loading is necessary for a long branch or call instruction.
<Comment> The PB register is loaded together with three bits from 4 bit
operand.
(19) LBBY
Naming : Load Block Buffer Register from Y-register.
Status : Set
Format : I
Function : BB ← Y
<Purpose> A new ROM page address is loaded into the block buffer
register (BB).
This loading is necessary for a long branch or call instruction.
<Comment> The BB register is loaded two bits(Y[1:0]) in the Y-register.
Data in the Y-register is left unchanged.
(20) LDWAY
Naming : Load Word from ROM addressed by XAY-register.
Status : Set
Format : I
Function :
SR1 ← PC + 1 PSR1 ← PA
SR2 ← SR1 PSR2 ← PSR1
SR3 ← SR2 PSR3 ← PSR2
PA,PC ← XAY(Addr)
AY ← [@XAY]
A ← MSB 4-Bit of [@XAY]
Y ← LSB 4-Bit of [@XAY]
PC ← SR1 PA, PB ← PSR1
SR1 ← SR2 PSR1 ← PSR2
SR2 ← SR3 PSR2 ← PSR3
SR3 ← SR3 PSR3 ← PSR3
<Purpose> Data transfer from ROM to AY-register.
<Comment> The A register is loaded higher four bits in the ROM,
and the Y register is loaded lower four bits in the ROM.
ADAM28PXX 3. Instruction
34 May 02, 2016 Ver. 1.4
(21) AM
Naming : Add Accumulator to Memory and Status 1 on Carry
Status : Carry to status
Format : Ⅰ
Function : A ← M(X,Y) + A ST ← 1(when total>15),
ST ← 0 (when total ≤15)
<Comment> Data in the memory location addressed by the X and Y-register
is added to data of the accumulator. Results are stored in the
accumulator. Carry data as results is transferred to status.
When the total is more than 15, a carry is caused to put ″1″
in the status. Data in the memory is not changed.
(22) SM
Naming : Subtract Accumulator to Memory and Status 1 Not Borrow
Status : Carry to status
Format : Ⅰ
Function : A ← M(X,Y) - A ST ← 1(when A ≤ M(X,Y))
ST ← 0(when A > M(X,Y))
<Comment> Data of the accumulator is, through a 2`s complement
addition, subtracted from the memory word addressed by the
Y-register. Results are stored in the accumulator. If data of
the accumulator is less than or equal to the memory word, the
status is set to indicate that a borrow is not caused.
If more than the memory word, a borrow occurs to reset the
status to ″0″.
(23) IM
Naming : Increment Memory and Status 1 on Carry
Status : Carry to status
Format : Ⅰ
Function : A ← M(X,Y) + 1 ST ← 1(when M(X,Y) ≥ 15)
ST ← 0(when M(X,Y) < 15)
<Comment> Data of the memory addressed by the X and Y-register is
fetched. Adding 1 to this word, results are stored in the
accumulator. Carry data as results is transferred to the status.
When the total is more than 15, the status is set. The memory
is left unchanged.
(24) DM
Naming : Decrement Memory and Status 1 on Not Borrow
Status : Carry to status
Format : Ⅰ
Function : A ← M(X,Y) - 1 ST ← 1(when M(X,Y) ≥1)
ST ← 0 (when M(X,Y) = 0)
<Comment> Data of the memory addressed by the X and Y-register is
fetched, and one is subtracted from this word (addition of Fh).
Results are stored in the accumulator. Carry data as results is
transferred to the status. If the data is more than or equal to
one, the status is set to indicate that no borrow is caused. The
memory is left unchanged.
ADAM28PXX 3. Instruction
35 May 02, 2016 Ver. 1.4
(25) IA
Naming : Increment Accumulator
Status : Set
Format : Ⅰ
Function : A ← A+1
<Comment> Data of the accumulator is incremented by one. Results are
returned to the accumulator.
A carry is not allowed to have effect upon the status.
(26) IY
Naming : Increment Y-Register and Status 1 on Carry
Status : Carry to status
Format : Ⅰ
Function : Y ← Y + 1 ST ← 1 (when Y = 15)
ST ← 0 (when Y < 15)
<Comment> Data of the Y-register is incremented by one and results are
returned to the Y-register.
Carry data as results is transferred to the status. When the
total is more than 15, the status is set.
(27) DA
Naming : Decrement Accumulator and Status 1 on Borrow
Status : Carry to status
Format : Ⅰ
Function : A ← A - 1 ST ← 1(when A ≥1)
ST ← 0 (when A = 0)
<Comment> Data of the accumulator is decremented by one. As a result
(by addition of Fh), if a borrow is caused, the status is reset to
″0″ by logic. If the data is more than one, no borrow occurs
and thus the status is set to ″1″.
ADAM28PXX 3. Instruction
36 May 02, 2016 Ver. 1.4
ADAM28PXX 3. Instruction
(28) DY
Naming : Decrement Y-Register and Status 1 on Not Borrow
Status : Carry to status
Format : Ⅰ
Function : Y ← Y -1 ST ← 1 (when Y ≥ 1)
ST ← 0 (when Y = 0)
<Purpose> Data of the Y-register is decremented by one.
<Comment> Data of the Y-register is decremented by one by addition of
minus 1 (Fh).
Carry data as results is transferred to the status. When the
results is equal to 15, the status is set to indicate that no
borrow has not occurred.
(29) EORM
Naming : Exclusive or Memory and Accumulator
Status : Set
Format : Ⅰ
Function : A ← M(X,Y) + A
<Comment> Data of the accumulator is, through a Exclusive OR,
subtracted from the memory word addressed by X and Y-
register. Results are stored into the accumulator.
(30) NEGA
Naming : Negate Accumulator and Status 1 on Zero
Status : Carry to status
Format : Ⅰ
Function : A ← A + 1 ST ← 1(when A = 0)
ST ← 0 (when A != 0)
<Purpose> The 2`s complement of a word in the accumulator is obtained.
<Comment> The 2`s complement in the accumulator is calculated by adding
one to the 1`s complement in the accumulator. Results are
stored into the accumulator. Carry data is transferred to the
status. When data of the accumulator is zero, a carry is
caused to set the status to ″1″.
37 May 02, 2016 Ver. 1.4
(31) ALEM
Naming : Accumulator Less Equal Memory
Status : Carry to status
Format : Ⅰ
Function : A ≤ M(X,Y) ST ← 1 (when A ≤ M(X,Y))
ST ← 0 (when A > M(X,Y))
<Comment> Data of the accumulator is, through a complement addition,
subtracted from data in the memory location addressed by the
X and Y-register. Carry data obtained is transferred to the
status. When the status is ″1″, it indicates that the data of
the accumulator is less than or equal to the data of the
memory word. Neither of those data is not changed.
(32) ALEI
Naming : Accumulator Less Equal Immediate
Status : Carry to status
Format : Ⅲ
Function : A ≤ i ST ← 1 (when A ≤ i)
ST ← 0 (when A > i)
<Purpose> Data of the accumulator and the constant are arithmetically
compared.
<Comment> Data of the accumulator is, through a complement addition,
subtracted from the constant that exists in 4bit operand.
Carry data obtained is transferred to the status.
The status is set when the accumulator value is less than or
equal to the constant. Data of the accumulator is left
unchanged.
(33) MNEZ
Naming : Memory Not Equal Zero
Status : Comparison results to status
Format : Ⅰ
Function : M(X,Y) ≠ 0 ST ← 1(when M(X,Y) ≠ 0)
ST ← 0 (when M(X,Y) = 0)
<Purpose> A memory word is compared with zero.
<Comment> Data in the memory addressed by the X and Y-register is
logically compared with zero. Comparison data is
transferred to the status. Unless it is zero, the status is set.
ADAM28PXX 3. Instruction
38 May 02, 2016 Ver. 1.4
(34) YNEA
Naming : Y-Register Not Equal Accumulator
Status : Comparison results to status
Format : Ⅰ
Function : Y ≠ A ST ← 1 (when Y ≠ A)
ST ← 0 (when Y = A)
<Purpose> Data of Y-register and accumulator are compared to check if
they are not equal.
<Comment> Data of the Y-register and accumulator are logically
compared.
Results are transferred to the status. Unless they are equal,
the status is set.
(35) YNEI
Naming : Y-Register Not Equal Immediate
Status : Comparison results to status
Format : Ⅲ
Operand : Constant 0 ≤ i ≤ 15
Function : Y ≠ i ST ← 1 (when Y ≠ i)
ST ← 0 (when Y = i)
<Comment> The constant of the Y-register is logically compared with 4bit
operand. Results are transferred to the status. Unless the
operand is equal to the constant, the status is set.
(36) LAK
Naming : Load Accumulator from K or P
Status : Set
Format : Ⅰ
Function : A ← K (when X-reg = 0 or 1)
A ← P (when X-reg = 2)
<Comment> Data on K or P are transferred to the accumulator
(37) LAR
Naming : Load Accumulator from R or CS
Status : Set
Format : Ⅰ
Function : A ← R (when X-reg = 0 or 1)
A ← CS (when X-reg = 2)
<Comment> Data on R or CS are transferred to the accumulator
ADAM28PXX 3. Instruction
39 May 02, 2016 Ver. 1.4
(38) SO
Naming : Set Output Register Latch
Status : Set
Format : Ⅰ
Function : K(Y) ← 1 (Pull-up) if 0 ≤ Y ≤ 3 , X=0 or 1
P(Y) ← 1 (Pull-up) if 0 ≤ Y ≤ 3 , X=2
R(Y-4) ← 1 (Pull-up) if 4 ≤ Y ≤ 7 , X=0 or 1
CS(Y-4) ← 1 (Pull-up or Hi-Z) if 4 ≤ Y ≤ 7 , X=2
ROUT ← 0 (PMR=5) if Y = 8, X=0~3
All of K, R ← 1 if Y = 9, X≠3
Pull-up disable of CS(Y-10) if Ah ≤ Y ≤ Bh, X≠3
T-Key Scan Enable if Y = Eh, X≠3
All of K, R, P ← 1 if Y = Fh, X≠3
(43) RO
Naming : Set Output Register Latch
Status : Set
Format : Ⅰ
Function : K(Y) ← 0 if 0 ≤ Y ≤ 3 , X=0 or 1
P(Y) ← 0 if 0 ≤ Y ≤ 3 , X=2
R(Y-4) ← 0 if 4 ≤ Y ≤ 7 , X=0 or 1
CS(Y-4) ← 0 if 4 ≤ Y ≤ 7 , X=2
ROUT ← 1 (Hi-Z) if Y = 8, X=0~3
All of K, R ← 0 if Y = 9, X≠3
Pull-up enable of CS(Y-10) if Ah ≤ Y ≤ Bh, X≠3
M-Key Scan Enable if Y = Eh, X≠3
All of K, R, P ← 0 if Y = Fh, X≠3
ADAM28PXX 3. Instruction
40 May 02, 2016 Ver. 1.4
(40) WDTR
Naming : Watch Dog Timer Reset
Status : Set
Format : Ⅰ
Function : Reset Watch Dog Timer (WDT)
<Purpose> Normally, you should reset this counter before overflowed
counter for dc watch dog timer. this instruction controls this
reset signal.
(41) STOP
Naming : STOP
Status : Set
Format : Ⅰ
Function : Operate the stop function
<Purpose> Stopped oscillator, and little current.
(42) LPY
Naming : Pulse Mode Set and Carrier Generator Data loading.
Status : Set
Format : Ⅰ
Function : PMR ← Y (if CCR0=0)
CDRH1, CDRH0, CDRL1, CDRL0 ← M, (if CCR0=1)
<Comment> Selects a pulse signal outputted from ROUT port.
(43) NOP
Naming : No Operation
Status : Set
Format : Ⅰ
Function : No operation
ADAM28PXX 3. Instruction
41 May 02, 2016 Ver. 1.4
(1) All rams need to be initialized to any value in reset address for proper design.
(2) Make the output ports `High` after reset.
(3) Do not use WDTR instruction in subroutine.
(4) When you try to read input port changed from external condition, you must secure chattering
time more than 200uS.
(5) To decrease current consumption, make the output port as high in normal routine except
for key scan strobe and STOP mode in the M-KEY Scan mode
(6) We recommend you do not use all 64 ROM bytes in a page.
It’s recommend to add `BR $` at first and last address of each page.
Do not add `BR $` at reset address which is first address of `00` page of `0` bank.
(7) `NOP` instruction should be follows STOP instruction for pre-charge time of Data Bus line.
ex) STOP : STOP instruction execution
NOP : NOP instruction
(8) We recommend that set output port low and delay 100us before stop mode entrance.
3.4. Guideline for S/W
ADAM28PXX 3. Instruction
42 May 02, 2016 Ver. 1.4
OTP Programming
ADAM28PXX Appendix
SYMBOL User Mode OTP Mode
VDD Power VDD Power (typ. 3.3V)
GND Ground Ground (0V)
VPP General port Program/Verify Power (typ. 6.5V / 3.3V)
SCK General port Serial Clock Input (open drain)
SDA General port Serial Data input/output (Open drain output)
ADAM28P16/ADAM28P16T (16SOP/TSSOP) Pin Assignments
ADAM28P16
(16 SOP)
ADAM28P16T
(16TSSOP)
3
4
5
6
7
8
2
1
10
9
11
12
14
13
15
16
K1
R0
K2
R1
GND
CS1
K0
K3
CS0
P2
P1
R2
P0
R3
VDD ROUT
SDA
VDD GND
SCK
VPP
ADAM28P08
(8 SOP) 3
4
2
1
6
5
7
8
R1
GND
K1
R0 CS0
P1
VDD ROUT
GND
SCK
VPP
VDD
SDA
ADAM28P08 (8SOP) Pin Assignments
DATA : SDA (1bit I/O)
CLOCK : SCK (1bit I/O)
VPP : VPP (1bit I/O)
Power : VDD, GND
N.C pin : don’t care
Pin count is 5pin : 3pin + power(2pin)
43 May 02, 2016 Ver. 1.4
ADAM28PXX Appendix
Pre-notice to programming the device
Configuration : OPTION0 address 4000h– Read / Write Area
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SIZE[2:0] LOCK[2:0] RCAL[1:0]
This device uses command based programming algorithm. You can read configuration data when you want. You can read code memory when you want, except device protection was enabled. Blank data is 0xff.
Name Option Description Option Value Option Results
SIZE MTP Size Definition
111 3kbytes x 1time
011 1’st 1.5kbytes
010 2’nd 1.5kbytes
110 1’st 1kbyte
100 (101)
2’nd 1kbyte
000 (001)
3’rd 1kbyte
LOCK MTP Lock Definition
111 un-lock
110 lock in 1’st 1kbyte
100 lock in 1’st 1.5kbytes
lock in 2’nd 1kbyte
000
lock in 2’nd 1.5kbytes
lock in 3’rd 1kbyte
lock in 3kbytes
101 011 010 001
prohibited
RCAL IRC Re-calibration
01 Using FCAL1[7:0] in OPTION3
11 10 00
using FCAL0[7:0] in OPTION2
44 May 02, 2016 Ver. 1.4
Application Circuit of ADAM28P16/ADAM28P16T (T-Type)
T-Type Keyboard ( 91-Key)
Application Circuit of ADAM28P08 (T-Type)
T-Type Keyboard ( 15-Key)
6
1
2
3
4
5
VDD
GND
AD
AM
28
P0
8
K1
R0
R1
P1
CS0
GND
8
1
VDD
ROUT 7
+
IR
=
-
1
4
2
3
8
6
7
11
10
13
5 9 12 14 15
7
8
9
3
4
5
6
10
11
12
13
VDD
GND
AD
AM
28
P1
6 / A
DA
M2
8P
16
T
2
14
K0
K1
K2
K3
R0
R1
R2
16
1
VDD
ROUT 15
+
IR
=
-
1
4
5
6
2
3
16
17
18
14
15
27
28
29
26
37
38
39
47
48 56
66
67
64
65
9
10
7
8
21
22
19
20
32
33
30
31
42
43
40
41
51
52
49
50
59
60
57
58
72
73
71
77
78 82
68 11 23 34 44 53 61 74 79 83 86
R3
P0
P1
P2
CS0
CS1
GND 1
69 12 24 35 45 54 62 75 80 84 87
70 13 25 36 46 55 63 76 81 85 88
89
90 91
ADAM28PXX Appendix
45 May 02, 2016 Ver. 1.4
Application Circuit of ADAM28P16/ADAM28P16T (M-Type)
Application Circuit of ADAM28P08 (M-Type)
M-Type Keyboard ( 9-Key)
2
3
4
VDD
GND
AD
AM
28
P0
8
1
K1
R0
R1
P1
CS0
GND
8
1
VDD
ROUT
+
1
2
3
4
5
6
7
8
9
=
-
7
IR
6
5
M-Type Keyboard ( 48-Key)
7
8
9
3
4
5
6
11
12
13
14
2 VDD
GND
AD
AM
28
P1
6 / A
DA
M2
8P
16
T
1
K0
K1
K2
K3
R0
R1
R2
R3
P0
P1
P2
CS0
CS1
16
1
VDD
ROUT
+
5
6
7
1
2
3
4
13
14
15
9
10
11
12
21
22
23
17
18
19
20
29
30
31
25
26
27
28
37
38
39
33
34
35
36
45
46
47
41
42
43
44
=
-
GND
15
IR
8 16 24 32 40 48 10
ADAM28PXX Appendix