4-Bit ALU Circuit Glitch Reduction for Power …agrawvd/COURSE/E6270_Spr15/PROJECT/REPORTS/...4-Bit...

4-Bit ALU Circuit Glitch Reduction for Power

Optimization For ELEC 6270 Dr. Vishwani D. Agrawal

By Hunter Thorington Fall 2015

Abstract— ELEC 6270 is an elective offered by Auburn

University’s Dr. Vishwani D. Agrawal. This paper concludes a

semester’s worth of studies in low power circuit design. The

project I was tasked with was: “Redesign a 4-bit ALU circuit for

glitch reduction and examine its power saving”. In this final

semester project, I developed my own VHDL model of a simple

ALU and synthesized this design using Leonardo Spectrum.

Following synthesis, I used the PTM High Performance 45nm

Metal Gate model provided. After applying the model to the

netlist, the design was simulated for a base line. Following initial

characterization of the circuit, the circuit was enhanced for glitch

reduction and low power operation by adding buffers on non-

critical paths. The results show a marked 27% decrease in power

consumption for the applied test vector.

Keywords—low power, CMOS, 45nm, gate delay, glitch

reduction, power optimization, ALU, Auburn

I. INTRODUCTION

This report was written for ELEC 6270 Low Power Design of Electronic Circuits for Dr. Vishwani D. Agrawal. This class focused on the design of digital circuit systems for reduced power consumption, power analysis algorithsm, low power MOS technologies, low power design architectures for FPGA, memory and microprocessors and reduction of power in testing of circuits. The project I was assigned was “Redesign a 4-bit ALU circuit for glitch reduction and examine its power saving”.

II. PROJECT BACKGROUND

A. Glitch Reduction

Circuit power is all about Dynamic Power. Dynamic power

or 𝐶𝑉2

2 , is the amount of power consumed by each gate each

time a transistion occurs. A glitch is defined as any

intermediate change of state of a signal, whether from high

to low or low to high during signal propagation before the

final value is reached. These glitches cause unwanted power

consumption.

B. Boolean Gate Single Transition Theorem

This theorem states that for correct operation with minimum

energy consumption, a Boolean gate much produce no more

than one event per transition. This means that for optimal

power reduction signal arriving at the input of a Boolean

gate much either arrive at the same time (assuming internal

Boolean gate delays are equal) or arrive at nearly the same

time in order to produce a single synchronized transition at

the output of the gate. If each and every gate in the circuit is

held to this theorem the circuit will have minimized power

consumption due to glitches.

C. Differential Path Delays

A multi-input gate will inevitably have differential path

delay. This delay occurs when the path from one input to the

output respective to another input to the same output is

different. Gate with differential path delay inherently

introduce glitch power consumption into the circuit. Figure

1. Shows the glitch caused by a multi-input gate with

differential path delay.

Figure 1. Differential Path Delay

In this figure The input A precedes the response of the gate

to input B which lags by one time period, this produces a

momentary high glitch on the output. This high output draws

Figure 2. Glitch Reduced Using a Buffer Delay

power from the power supply, but is wasted because it soon

returns to the expected value 0. Figure 2 demonstrates that

by placing a delay buffer on input A this issue can be

reduced. Notice in Figure 2 how the glitch is minimized.

Therefore, to ensure glitch reduction, delay A, the input

delay must be less than the delay B – delay A. This is

represented by the equation d < DPD.

D. Delay Balance Method

The buffer enhanced differential delay method can be extended

to circuit wide glitch reduction. The balanced delay method

treats the entire circuit as an effectively large Boolean gate, but

rather than have delay buffers external to the gate the buffers

are internal. Delay buffers are inserted on non-critical paths in

the circuit to delay their response to be in time with the critical

path. If this method is followed for all non-critical paths through

the circuit, all paths will have the same delay. This results

creates a circuit with minimal glitch power loss.

E. Gate Delay Mathmatical Glitch Suppression

Once can define gate delay, the time taken for a signal to propagate from input to output as di. The time differential for each

input can be defined as ti the earlies arriving signal, and Ti the latest arriving signal. To ensure a glitch is suppressed Ti – ti < di

F. Linear Programing Buffer Delay Minimization

To achieve near optimal power reduction, the minimum

number of buffers must be used. While this criterion is

nonlinear, one can minimize the sum of the total buffer delays.

By minimizing total buffer delay one ensures that a near

optimal number of buffers are inserted into the circuit and draw

no more power than necessary to reduce glitch power

consumption. To many buffers (each drawing power

themselves) can increase power consumption rather than

reduce.

G. ALU 74181 Example

The slides provided example results from a previous student of this project. The project took a 74181 ALU, an industry standard DIP package ALU. The circuit was modified in an undisclosed manner and achieved an average of 21% power reduction. I began my design work for this project by studying the 74181 circuit and preparing to optimize the 74181’s design for glitch reduction. This proved to be a difficult task to large size of the 74181 nearing 75 gates. Also, the circuit schematic would have to be drawn by hand in Design Architect to get a base line. Due to time constraints, I decided to design my own ALU with fewer functions and write it in VHDL allowing it to be synthesized into a gate-level model with which I could then modify.

III. PROJECT DESIGN

A. VHDL Model of 4-Bit ALU

The 4-Bit ALU model for this project was written in VHDL.

The ALU has 4 functions add, subtract, add one, and subtract

one. This design could clearly be extended to a larger design

but was out of scope for this project. The ALU has two inputs

A and B which are the two 4 bit unsigned arguments. The output

is a 4 bit vector F. The function of the ALU is selected by setting

the bus S.

entity alu is

port( Clk : in std_logic; --clock signal

A,B : in unsigned(3 downto 0); --input operands

S : in unsigned(1 downto 0); --Operation to be performed

F : out unsigned(3 downto 0) --output of ALU

);

end alu;

architecture Behavioral of alu is

signal t1,t2,t3: unsigned(3 downto 0) := (others => '0');

begin

t1<= A;

t2<= B;

F<= t3;

process(Clk)

begin

if(rising_edge(Clk)) then --Do the calculation at the positive

edge of clock cycle.

case S is

when "00" =>

t3<= t1 + t2; --addition

when "01" =>

t3<= t1 - t2; --subtraction

when "10" =>

t3<= t1 - 1; --sub 1

when "11" =>

t3<= t1 + 1; --add 1

when others =>

NULL;

end case;

end if;

end process;

end Behavioral;

B. Synthesis using Leonardo Spectrum

The circuit was synthesized using Leonardo Spectrum into

TSMC 035 design package for 35nm operation. The resulting

circuit contained 26 block level gates and 54 total gates.

Leonardo defined the critical path as follows and featured a

1.11ns delay time.

Critical path #1, (unconstrained path)

NAME GATE ARRIVAL

LOAD

---------------------------------------------------------------------------

---

S(0)/ 0.00 0.00 up 0.04

ix1/Y xnor2 0.21 0.21 dn 0.07

ix7/Y xnor2 0.15 0.36 up 0.02

ix9/Y xnor2 0.13 0.49 dn 0.03

ix134/Y aoi22 0.16 0.65 up 0.02

ix146/Y mux21 0.19 0.84 up 0.02

ix155/Y mux21 0.17 1.00 up 0.02

ix89/Y xnor2 0.11 1.11 dn 0.01

reg_t3(3)/D dff 0.00 1.11 dn 0.00

data arrival time 1.11

C. Vector Selection

HSPICE was used to simulate the circuit by applying a test

vector set. The test vector set I used contained 1024 test

vectors. This represented every possible input combination

one time for each operation. These vectors were run 5ns

apart for a total of 5120ns to profile the circuit for power

consumption.

D. Power Analysis Initial Circuit

The power analayis for the un modified circuit was run using

HSPICE. The result showed 336uW used before glitch

reduction.

****** transient analysis tnom= 25.000 temp= 25.000 *****

avg_current= 3.3691E-01 from= 0.0000E+00 to= 1.2000E-06

rms_current= 4.6810E-01 from= 0.0000E+00 to= 1.2000E-06

avg_pow= 3.3691E-01 from= 0.0000E+00 to= 1.2000E-06

rms_pow= 4.6810E-01 from= 0.0000E+00 to= 1.2000E-06

powavg= 3.3691E-01

powrms= 4.6810E-01

E. Glitch Reduction Design Using Buffer Delays

As given earlier, the critical path had a delay of 1.11ns. Using

the gate level model of the circuit I determined 8 paths that

could be optimized using buffer delays to bring their total path

delay near 1.11 ns. These buffer delays are as follows:

Path 1: S[1] ix129, ix1, ix7, ix136, ix134, new buffer, ix146, ix155, regt33

Buffer delay added 0.32ns

Path 2: S[0], ix129, ix127, ix7, new buffer, ix134, ix146, ix155,ix89,reg33


Path 3: S[1], new buffer, ix134, ix146, ix155, ix99, reg33


Path 4: A[0], new buffer, ix11, regt30,


Path 5: S[1], ix127,ix7,ix9, new buffer,ix11


Path 6: A[1], ix9,new buffer, ix87,ix63,reg32


Path 7: S[1], ix35, new buffer, ix37,reg31


Path 8: S[1], ix134, new buffer, ix37,reg31


F. Power Analysis Final Circuit

The power analayis for the modified circuit was run using


reduction.

G. Power Analysis Initial Circuit

The power analayis for the un modified circuit was run using


reduction.






powavg= 2.4379E-01

powrms= 4.1507E-01

H. Results Comparison

4-Bit ALU

Standard

4-Bit ALU

w/ buffer

delay glitch

reduction

%

Difference

Average

power

consumption

336uW 243uW 27.6%

IV. CONCLUSION

A. Results

This simple ALU designed allowed me to tune in really good

results. Using a minimal number of delay buffers, 8, on select

non critical paths allow me to make 9 selected paths through the

circuit has similar delays. This resulted in fewer glitches and

decreased power consumption. While not all paths were

optimized and the number of buffers and total buffer delay was

not optimized using linear programming I feel this a good

results considering the time constraints and project scope.

Please see the following pages and appendixes for addition

evidence of completed work.

B. Overall

This project and class was quite enjoyable. I really learned a lot

about power reduction and how complex and simple it can be

at the same time. Low power devices are the next generation

devices that will be made. Battery power and mobile devices

rely heavily on reduced power consumption. The design and

analysis techniques learned in this class are very applicable to

the job market today. I feel I have come away with actionable

knowledge ready to be applied and expanded on in my career.

REFERENCES

[1] Vishwani D. Agrawal, James J. Danaher Professor of ECE

http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Spr1

5/course.html

[2] Victor P. Nelson, Professor of ECE

http://www.eng.auburn.edu/~nelson/courses/elec5250_6250/

http://www.eng.auburn.edu/~vagrawal/index.html

http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Spr15/course.html

http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Spr15/course.html

http://www.eng.auburn.edu/~nelsovp

Circuit Design Before Buffers, Red Line Shows Critical Path

Circuit Design After Buffers, Red Line Shows Critical Path, Green Arrows new Buffers

Waveforms demonstrating Glitch Power Reduction

After:

Before:

Glitch and the Power

drawn from VDD.

Wow! Big Reduction!

Glitch and the Power

drawn from VDD

Appendix I. Spice Netlist and HSPICE analysis configuration parameters.

* LVS netlist generated with ICnet by 'hlt0001' on Wed Apr 29 2015 at 22:39:34

*

* Globals.

*

.inc '45nm_MGK.pm'

.global GND VDD

.param lam=0.045u

.param t=300ns

.param tr=0.01ns

.param supply=1v

.option post brief probe

vclk Clk 0 pulse(0 5 0 .1n .1n 1n 2n)

VDD VDD GND supply

.vec 'aluVectors.vec'

X_alu A[0] A[1] A[2] A[3] B[0] B[1] B[2] B[3] S[0] S[1] F[0]

+ F[1] F[2] F[3] Clk alu

*

* Component pathname : $ADK/parts/mux21

*

.subckt mux21 S0 A0 A1 Y

M_I$5 Y S0 N$10 VDD pmos L=0.4u W=.045u

M_I$13 N$6 A1 GND GND nmos L=0.4u W=2u

M_I$12 Y S0 N$6 GND nmos L=0.4u W=2u

M_I$17 Y N$7 N$5 VDD pmos L=0.4u W=.045u

M_I$16 N$5 A1 VDD VDD pmos L=0.4u W=.045u


M_I$6 Y N$7 N$4 GND nmos L=0.4u W=2u

M_I$4 N$10 A0 VDD VDD pmos L=0.4u W=.045u

M_I$3 N$7 S0 GND GND nmos L=0.4u W=1u

M_I$2 N$7 S0 VDD VDD pmos L=0.4u W=1.8u

.ends mux21

*

* Component pathname : $ADK/parts/inv01

*

.subckt inv01 A Y

M_I$411 Y A VDD VDD pmos L=0.4u W=1.8u

M_I$412 Y A GND GND nmos L=0.4u W=1u

.ends inv01

*

* Component pathname : $ADK/parts/nand02

*

.subckt nand02 Y A0 A1

M_I$472 Y A1 VDD VDD pmos L=0.4u W=2.4u

M_I$471 Y A0 VDD VDD pmos L=0.4u W=2.4u

M_I$4 Y A0 N$7 GND nmos L=0.4u W=2u


.ends nand02

*

* Component pathname : $ADK/parts/xnor2

*

.subckt xnor2 Y A0 A1


M_I$217 N$212 A0 N$213 GND nmos L=0.4u W=2u

M_I$9 N$212 A1 VDD VDD pmos L=0.4u W=2.6u


M_I$7 N$3 N$212 GND GND nmos L=0.4u W=2u



M_I$4 Y A1 N$1 VDD pmos L=0.4u W=5.2u

M_I$3 Y N$212 VDD VDD pmos L=0.4u W=2.6u


.ends xnor2

*

* Component pathname : $ADK/parts/buf16

*

.subckt buf16 A Y

M_I$1238 N$1022 A GND GND nmos L=0.4u W=100u

M_I$1235 N$1022 A VDD VDD pmos L=0.4u W=180u

M_I$1233 Y N$1022 VDD VDD pmos L=0.4u W=180u

M_I$1232 Y N$1022 GND GND nmos L=0.4u W=50u















M_I$411 N$1022 A VDD VDD pmos L=0.4u W=180u

M_I$412 N$1022 A GND GND nmos L=0.4u W=50u

.ends buf16

*

* Component pathname : $ADK/parts/aoi22

*

.subckt aoi22 B1 A0 A1 B0 Y

M_I$425 Y B0 N$9 GND nmos L=0.4u W=2u

M_I$426 Y B1 N$4 VDD pmos L=0.4u W=2.6u



M_I$7 Y B0 N$4 VDD pmos L=0.4u W=2.6u



M_I$13 N$9 B1 GND GND nmos L=0.4u W=2u

.ends aoi22

*

* Component pathname : $ADK/parts/xor2

*

.subckt xor2 Y A0 A1


M_I$420 Y N$4 VDD VDD pmos L=0.4u W=1.8u








M_I$4 N$4 A1 N$1 VDD pmos L=0.4u W=5.2u

M_I$3 N$4 N$212 VDD VDD pmos L=0.4u W=2.6u


.ends xor2

*

* Component pathname : $ADK/parts/dff

*

.subckt dff QB Q CLK D

M_I$441 N$847 bclk- N$851 GND nmos L=0.4u W=3u

M_I$440 N$849 N$847 VDD VDD pmos L=0.4u W=1u

M_I$439 N$847 bclk- N$848 VDD pmos L=0.4u W=1u


M_I$437 N$847 bclk N$845 VDD pmos L=0.4u W=5.4u

M_I$436 N$845 D VDD VDD pmos L=0.4u W=5.4u

M_I$452 bclk bclk- GND GND nmos L=0.4u W=2u

M_I$673 Q QB GND GND nmos L=0.4u W=2u

M_I$672 Q QB VDD VDD pmos L=0.4u W=.045u

M_I$669 QB N$1074 GND GND nmos L=0.4u W=2u

M_I$675 QB N$1074 VDD VDD pmos L=0.4u W=.045u



M_I$666 N$1074 bclk- N$1073 GND nmos L=0.4u W=1u


M_I$664 N$1074 bclk N$1072 GND nmos L=0.4u W=3u


M_I$662 N$1074 bclk N$1070 VDD pmos L=0.4u W=1u


M_I$660 N$1074 bclk- N$1069 VDD pmos L=0.4u W=5.4u

M_I$659 N$1069 N$847 VDD VDD pmos L=0.4u W=5.4u

M_I$449 bclk- CLK GND GND nmos L=0.4u W=2u

M_I$448 bclk- CLK VDD VDD pmos L=0.4u W=.045u

M_I$453 bclk bclk- VDD VDD pmos L=0.4u W=.045u



M_I$443 N$847 bclk N$852 GND nmos L=0.4u W=1u

M_I$442 N$851 D GND GND nmos L=0.4u W=3u

.ends dff

*

* Component pathname : /home/u1/hlt0001/4BitALU3/alu

*

.subckt alu A[0] A[1] A[2] A[3] B[0] B[1] B[2] B[3] S[0] S[1] F[0] F[1]

+ F[2] F[3] Clk

X_ix155 nx60 nx58 nx145 nx154 mux21

X_ix146 nx34 nx32 nx133 nx145 mux21

X_ix136 nx6 nx135 inv01

X_ix129 S[1] nx128 inv01

X_ix159 nx158 B[3] nx128 nand02

X_ix150 nx149 B[2] nx128 nand02

X_ix141 nx140 B[1] nx128 nand02

X_ix127 nx126 B[0] nx128 nand02

X_ix85 nx84 nx0 nx158 xnor2

X_ix87 nx86 N$465 nx84 xnor2



X_ix61 nx60 A[2] nx58 xnor2


X_BUF1614 A[3] N$465 buf16

X_BUF1613 nx34 N$462 buf16

X_BUF1612 nx133 N$14 buf16

X_ix134 N$674 N$27 N$459 N$460 nx133 aoi22

X_BUF1611 A[0] N$253 buf16

X_BUF1610 nx140 N$255 buf16

X_BUF169 nx135 N$27 buf16

X_BUF168 A[0] N$459 buf16

X_BUF167 S[0] N$460 buf16

X_BUF166 S[0] N$676 buf16

X_BUF165 N$676 N$675 buf16

X_BUF164 N$675 N$458 buf16

X_BUF163 N$674 N$673 buf16

X_BUF162 N$673 N$672 buf16

X_BUF161 N$672 N$457 buf16

X_ix33 nx32 nx0 N$255 xnor2

X_ix35 nx34 A[1] nx32 xnor2

X_ix37 nx36 N$14 N$462 xnor2

X_ix1 nx0 S[0] S[1] xnor2


X_ix9 N$674 N$253 nx6 xnor2

X_ix11 nx10 N$458 N$457 xor2

X_reg_t3_3 N$dummy_esc1[3] F[3] Clk nx88 dff




.ends alu

.tran 1ns '4*t'

.measure tran avg_current avg i(vdd) from=0ns to='4*t'

.measure tran rms_current rms i(vdd) from=0ns to='4*t'

.measure tran avg_pow avg p(vdd) from=0ns to='4*t'

.measure tran rms_pow rms p(vdd) from=0ns to='4*t'

.measure tran powavg param='avg_current*supply'

.measure tran powrms param='rms_current*supply'

.print i(vdd)

.print power

.probe v(A[0]) v(A[1]) v(A[2]) v(A[3]) v(B[0]) v(B[1]) v(B[2]) v(B[3]) v(S[0]) v(S[1]) v(F[0]) v(F[1]) v(F[2]) v(F[3]) v(Clk)

.end

Appendix II. ALU Test Vectors

; start of Pattern Definition section

RADIX 4 4 2

vname A[[3:0]] B[[3:0]] S[[1:0]]

IO I I I

period 1

tunit ns

slope 0.01

vih 1

vil 0

voh 0.7

vol 0.3

;Vector

Table

0 0 0

1 0 0

2 0 0

3 0 0

4 0 0

5 0 0

6 0 0

7 0 0

8 0 0

9 0 0

A 0 0

B 0 0

C 0 0

D 0 0

E 0 0

F 0 0

0 0 1

1 0 1

2 0 1

3 0 1

4 0 1

5 0 1

6 0 1

7 0 1

8 0 1

9 0 1

A 0 1

B 0 1

C 0 1

D 0 1

E 0 1

F 0 1

0 0 2

1 0 2

2 0 2

3 0 2

4 0 2

5 0 2

6 0 2

7 0 2

8 0 2

9 0 2

A 0 2

B 0 2

C 0 2

D 0 2

E 0 2

F 0 2

0 0 3

1 0 3

2 0 3

3 0 3

4 0 3

5 0 3

6 0 3

7 0 3

8 0 3

9 0 3

A 0 3

B 0 3

C 0 3

D 0 3

E 0 3

F 0 3

0 0 0

1 0 0

2 0 0

3 0 0

4 0 0

5 0 0

6 0 0

7 0 0

8 0 0

9 0 0

A 0 0

B 0 0

C 0 0

D 0 0

E 0 0

F 0 0

0 1 1

1 1 1

2 1 1

3 1 1

4 1 1

5 1 1

6 1 1

7 1 1

8 1 1

9 1 1

A 1 1

B 1 1

C 1 1

D 1 1

E 1 1

F 1 1

0 1 2

1 1 2

2 1 2

3 1 2

4 1 2

5 1 2

6 1 2

7 1 2

8 1 2

9 1 2

A 1 2

B 1 2

C 1 2

D 1 2

E 1 2

F 1 2

0 1 3

1 1 3

2 1 3

3 1 3

4 1 3

5 1 3

6 1 3

7 1 3

8 1 3

9 1 3

A 1 3

B 1 3

C 1 3

D 1 3

E 1 3

F 1 3

0 2 0

1 2 0

2 2 0

3 2 0

4 2 0

5 2 0

6 2 0

7 2 0

8 2 0

9 2 0

A 2 0

B 2 0

C 2 0

D 2 0

E 2 0

F 2 0

0 2 1

1 2 1

2 2 1

3 2 1

4 2 1

5 2 1

6 2 1

7 2 1

8 2 1

9 2 1

A 2 1

B 2 1

C 2 1

D 2 1

E 2 1

F 2 1

0 2 2

1 2 2

2 2 2

3 2 2

4 2 2

5 2 2

6 2 2

7 2 2

8 2 2

9 2 2

A 2 2

B 2 2

C 2 2

D 2 2

E 2 2

F 2 2

0 2 3

1 2 3

2 2 3

3 2 3

4 2 3

5 2 3

6 2 3

7 2 3

8 2 3

9 2 3

A 2 3

B 2 3

C 2 3

D 2 3

E 2 3

F 2 3

0 2 0

1 2 0

2 2 0

3 2 0

4 2 0

5 2 0

6 2 0

7 2 0

8 2 0

9 2 0

A 2 0

B 2 0

C 2 0

D 2 0

E 2 0

F 2 0

0 3 0

1 3 0

2 3 0

3 3 0

4 3 0

5 3 0

6 3 0

7 3 0

8 3 0

9 3 0

A 3 0

B 3 0

C 3 0

D 3 0

E 3 0

F 3 0

0 3 1

1 3 1

2 3 1

3 3 1

4 3 1

5 3 1

6 3 1

7 3 1

8 3 1

9 3 1

A 3 1

B 3 1

C 3 1

D 3 1

E 3 1

F 3 1

0 3 2

1 3 2

2 3 2

3 3 2

4 3 2

5 3 2

6 3 2

7 3 2

8 3 2

9 3 2

A 3 2

B 3 2

C 3 2

D 3 2

E 3 2

F 3 2

0 3 3

1 3 3

2 3 3

3 3 3

4 3 3

5 3 3

6 3 3

7 3 3

8 3 3

9 3 3

A 3 3

B 3 3

C 3 3

D 3 3

E 3 3

F 3 3

0 3 0

1 3 0

2 3 0

3 3 0

4 3 0

5 3 0

6 3 0

7 3 0

8 3 0

9 3 0

A 3 0

B 3 0

C 3 0

D 3 0

E 3 0

F 3 0

0 4 0

1 4 0

2 4 0

3 4 0

4 4 0

5 4 0

6 4 0

7 4 0

8 4 0

9 4 0

A 4 0

B 4 0

C 4 0

D 4 0

E 4 0

F 4 0

0 4 1

1 4 1

2 4 1

3 4 1

4 4 1

5 4 1

6 4 1

7 4 1

8 4 1

9 4 1

A 4 1

B 4 1

C 4 1

D 4 1

E 4 1

F 4 1

0 4 2

1 4 2

2 4 2

3 4 2

4 4 2

5 4 2

6 4 2

7 4 2

8 4 2

9 4 2

A 4 2

B 4 2

C 4 2

D 4 2

E 4 2

F 4 2

0 4 3

1 4 3

2 4 3

3 4 3

4 4 3

5 4 3

6 4 3

7 4 3

8 4 3

9 4 3

A 4 3

B 4 3

C 4 3

D 4 3

E 4 3

F 4 3

0 4 0

1 4 0

2 4 0

3 4 0

4 4 0

5 4 0

6 4 0

7 4 0

8 4 0

9 4 0

A 4 0

B 4 0

C 4 0

D 4 0

E 4 0

F 4 0

0 5 1

1 5 1

2 5 1

3 5 1

4 5 1

5 5 1

6 5 1

7 5 1

8 5 1

9 5 1

A 5 1

B 5 1

C 5 1

D 5 1

E 5 1

F 5 1

0 5 2

1 5 2

2 5 2

3 5 2

4 5 2

5 5 2

6 5 2

7 5 2

8 5 2

9 5 2

A 5 2

B 5 2

C 5 2

D 5 2

E 5 2

F 5 2

0 5 3

1 5 3

2 5 3

3 5 3

4 5 3

5 5 3

6 5 3

7 5 3

8 5 3

9 5 3

A 5 3

B 5 3

C 5 3

D 5 3

E 5 3

F 5 3

0 6 0

1 6 0

2 6 0

3 6 0

4 6 0

5 6 0

6 6 0

7 6 0

8 6 0

9 6 0

A 6 0

B 6 0

C 6 0

D 6 0

E 6 0

F 6 0

0 6 1

1 6 1

2 6 1

3 6 1

4 6 1

5 6 1

6 6 1

7 6 1

8 6 1

9 6 1

A 6 1

B 6 1

C 6 1

D 6 1

E 6 1

F 6 1

0 6 2

1 6 2

2 6 2

3 6 2

4 6 2

5 6 2

6 6 2

7 6 2

8 6 2

9 6 2

A 6 2

B 6 2

C 6 2

D 6 2

E 6 2

F 6 2

0 6 3

1 6 3

2 6 3

3 6 3

4 6 3

5 6 3

6 6 3

7 6 3

8 6 3

9 6 3

A 6 3

B 6 3

C 6 3

D 6 3

E 6 3

F 6 3

0 6 0

1 6 0

2 6 0

3 6 0

4 6 0

5 6 0

6 6 0

7 6 0

8 6 0

9 6 0

A 6 0

B 6 0

C 6 0

D 6 0

E 6 0

F 6 0

0 7 0

1 7 0

2 7 0

3 7 0

4 7 0

5 7 0

6 7 0

7 7 0

8 7 0

9 7 0

A 7 0

B 7 0

C 7 0

D 7 0

E 7 0

F 7 0

0 7 1

1 7 1

2 7 1

3 7 1

4 7 1

5 7 1

6 7 1

7 7 1

8 7 1

9 7 1

A 7 1

B 7 1

C 7 1

D 7 1

E 7 1

F 7 1

0 7 2

1 7 2

2 7 2

3 7 2

4 7 2

5 7 2

6 7 2

7 7 2

8 7 2

9 7 2

A 7 2

B 7 2

C 7 2

D 7 2

E 7 2

F 7 2

0 7 3

1 7 3

2 7 3

3 7 3

4 7 3

5 7 3

6 7 3

7 7 3

8 7 3

9 7 3

A 7 3

B 7 3

C 7 3

D 7 3

E 7 3

F 7 3

0 7 0

1 7 0

2 7 0

3 7 0

4 7 0

5 7 0

6 7 0

7 7 0

8 7 0

9 7 0

A 7 0

B 7 0

C 7 0

D 7 0

E 7 0

F 7 0

0 8 0

1 8 0

2 8 0

3 8 0

4 8 0

5 8 0

6 8 0

7 8 0

8 8 0

9 8 0

A 8 0

B 8 0

C 8 0

D 8 0

E 8 0

F 8 0

0 8 1

1 8 1

2 8 1

3 8 1

4 8 1

5 8 1

6 8 1

7 8 1

8 8 1

9 8 1

A 8 1

B 8 1

C 8 1

D 8 1

E 8 1

F 8 1

0 8 2

1 8 2

2 8 2

3 8 2

4 8 2

5 8 2

6 8 2

7 8 2

8 8 2

9 8 2

A 8 2

B 8 2

C 8 2

D 8 2

E 8 2

F 8 2

0 8 3

1 8 3

2 8 3

3 8 3

4 8 3

5 8 3

6 8 3

7 8 3

8 8 3

9 8 3

A 8 3

B 8 3

C 8 3

D 8 3

E 8 3

F 8 3

0 8 0

1 8 0

2 8 0

3 8 0

4 8 0

5 8 0

6 8 0

7 8 0

8 8 0

9 8 0

A 8 0

B 8 0

C 8 0

D 8 0

E 8 0

F 8 0

0 9 1

1 9 1

2 9 1

3 9 1

4 9 1

5 9 1

6 9 1

7 9 1

8 9 1

9 9 1

A 9 1

B 9 1

C 9 1

D 9 1

E 9 1

F 9 1

0 9 2

1 9 2

2 9 2

3 9 2

4 9 2

5 9 2

6 9 2

7 9 2

8 9 2

9 9 2

A 9 2

B 9 2

C 9 2

D 9 2

E 9 2

F 9 2

0 9 3

1 9 3

2 9 3

3 9 3

4 9 3

5 9 3

6 9 3

7 9 3

8 9 3

9 9 3

A 9 3

B 9 3

C 9 3

D 9 3

E 9 3

F 9 3

0 A 0

1 A 0

2 A 0

3 A 0

4 A 0

5 A 0

6 A 0

7 A 0

8 A 0

9 A 0

A A 0

B A 0

C A 0

D A 0

E A 0

F A 0

0 A 1

1 A 1

2 A 1

3 A 1

4 A 1

5 A 1

6 A 1

7 A 1

8 A 1

9 A 1

A A 1

B A 1

C A 1

D A 1

E A 1

F A 1

0 A 2

1 A 2

2 A 2

3 A 2

4 A 2

5 A 2

6 A 2

7 A 2

8 A 2

9 A 2

A A 2

B A 2

C A 2

D A 2

E A 2

F A 2

0 A 3

1 A 3

2 A 3

3 A 3

4 A 3

5 A 3

6 A 3

7 A 3

8 A 3

9 A 3

A A 3

B A 3

C A 3

D A 3

E A 3

F A 3

0 A 0

1 A 0

2 A 0

3 A 0

4 A 0

5 A 0

6 A 0

7 A 0

8 A 0

9 A 0

A A 0

B A 0

C A 0

D A 0

E A 0

F A 0

0 B 0

1 B 0

2 B 0

3 B 0

4 B 0

5 B 0

6 B 0

7 B 0

8 B 0

9 B 0

A B 0

B B 0

C B 0

D B 0

E B 0

F B 0

0 B 1

1 B 1

2 B 1

3 B 1

4 B 1

5 B 1

6 B 1

7 B 1

8 B 1

9 B 1

A B 1

B B 1

C B 1

D B 1

E B 1

F B 1

0 B 2

1 B 2

2 B 2

3 B 2

4 B 2

5 B 2

6 B 2

7 B 2

8 B 2

9 B 2

A B 2

B B 2

C B 2

D B 2

E B 2

F B 2

0 B 3

1 B 3

2 B 3

3 B 3

4 B 3

5 B 3

6 B 3

7 B 3

8 B 3

9 B 3

A B 3

B B 3

C B 3

D B 3

E B 3

F B 3

0 B 0

1 B 0

2 B 0

3 B 0

4 B 0

5 B 0

6 B 0

7 B 0

8 B 0

9 B 0

A B 0

B B 0

C B 0

D B 0

E B 0

F B 0

0 C 0

1 C 0

2 C 0

3 C 0

4 C 0

5 C 0

6 C 0

7 C 0

8 C 0

9 C 0

A C 0

B C 0

C C 0

D C 0

E C 0

F C 0

0 C 1

1 C 1

2 C 1

3 C 1

4 C 1

5 C 1

6 C 1

7 C 1

8 C 1

9 C 1

A C 1

B C 1

C C 1

D C 1

E C 1

F C 1

0 C 2

1 C 2

2 C 2

3 C 2

4 C 2

5 C 2

6 C 2

7 C 2

8 C 2

9 C 2

A C 2

B C 2

C C 2

D C 2

E C 2

F C 2

0 C 3

1 C 3

2 C 3

3 C 3

4 C 3

5 C 3

6 C 3

7 C 3

8 C 3

9 C 3

A C 3

B C 3

C C 3

D C 3

E C 3

F C 3

0 C 0

1 C 0

2 C 0

3 C 0

4 C 0

5 C 0

6 C 0

7 C 0

8 C 0

9 C 0

A C 0

B C 0

C C 0

D C 0

E C 0

F C 0

0 D 1

1 D 1

2 D 1

3 D 1

4 D 1

5 D 1

6 D 1

7 D 1

8 D 1

9 D 1

A D 1

B D 1

C D 1

D D 1

E D 1

F D 1

0 D 2

1 D 2

2 D 2

3 D 2

4 D 2

5 D 2

6 D 2

7 D 2

8 D 2

9 D 2

A D 2

B D 2

C D 2

D D 2

E D 2

F D 2

0 D 3

1 D 3

2 D 3

3 D 3

4 D 3

5 D 3

6 D 3

7 D 3

8 D 3

9 D 3

A D 3

B D 3

C D 3

D D 3

E D 3

F D 3

0 E 0

1 E 0

2 E 0

3 E 0

4 E 0

5 E 0

6 E 0

7 E 0

8 E 0

9 E 0

A E 0

B E 0

C E 0

D E 0

E E 0

F E 0

0 E 1

1 E 1

2 E 1

3 E 1

4 E 1

5 E 1

6 E 1

7 E 1

8 E 1

9 E 1

A E 1

B E 1

C E 1

D E 1

E E 1

F E 1

0 E 2

1 E 2

2 E 2

3 E 2

4 E 2

5 E 2

6 E 2

7 E 2

8 E 2

9 E 2

A E 2

B E 2

C E 2

D E 2

E E 2

F E 2

0 E 3

1 E 3

2 E 3

3 E 3

4 E 3

5 E 3

6 E 3

7 E 3

8 E 3

9 E 3

A E 3

B E 3

C E 3

D E 3

E E 3

F E 3

0 E 0

1 E 0

2 E 0

3 E 0

4 E 0

5 E 0

6 E 0

7 E 0

8 E 0

9 E 0

A E 0

B E 0

C E 0

D E 0

E E 0

F E 0

0 F 0

1 F 0

2 F 0

3 F 0

4 F 0

5 F 0

6 F 0

7 F 0

8 F 0

9 F 0

A F 0

B F 0

C F 0

D F 0

E F 0

F F 0

0 F 1

1 F 1

2 F 1

3 F 1

4 F 1

5 F 1

6 F 1

7 F 1

8 F 1

9 F 1

A F 1

B F 1

C F 1

D F 1

E F 1

F F 1

0 F 2

1 F 2

2 F 2

3 F 2

4 F 2

5 F 2

6 F 2

7 F 2

8 F 2

9 F 2

A F 2

B F 2

C F 2

D F 2

E F 2

F F 2

0 F 3

1 F 3

2 F 3

3 F 3

4 F 3

5 F 3

6 F 3

7 F 3

8 F 3

9 F 3

A F 3

B F 3

C F 3

D F 3

E F 3

F F 3

Appendix III. HPSICE with Buffer Modifications

Using: /usr/bin/time -p /linux_apps/synopsys/v2.5/hspice/hspice/linux/hspice -i alu_16buf.sp

****** HSPICE -- E-2010.12-SP1 32-BIT (Feb 23 2011) linux ******

Copyright (C) 2010 Synopsys, Inc. All Rights Reserved.

Unpublished-rights reserved under US copyright laws.

This program is protected by law and is subject to the

terms and conditions of the license agreement from Synopsys.

Use of this program is your acceptance to be bound by the

license agreement. HSPICE is the trademark of Synopsys, Inc.

Input File: alu_16buf.sp

Command line options: -i alu_16buf.sp

lic: No 'setenv LM_LICENSE_FILE' in current environment'

lic:

lic: FLEXlm: v10.8

lic: USER: hlt0001 HOSTNAME: eelnx165.eng.auburn.edu

lic: HOSTID: 00101897217b PID: 17774

lic: Using FLEXlm license file:

lic: [email protected]

lic: Checkout 1 hspice

lic: License/Maintenance for hspice will expire on 21-jul-2015/2014.09

lic: 1(in_use)/50(total) FLOATING license(s) on SERVER perseus.eng.auburn.edu

lic:

Init: read install configuration file: /linux_apps/synopsys/v2.5/hspice/hspice/meta.cfg

**info** (alu_16buf.sp:15) DC voltage reset to initial transient source value in source 0:vclk new dc=

0.0000D+00

**warning**(nmos:m_i$13)Warning: Acde = 0.235521 may be too small in BSIM4 model with w=2e-06 l=4e-07.

**info** set option symb=1 internally to help for convergence.

*****************************************************************

****** option summary

******

runlvl = 3 bypass = 2

Opening plot unit= 15

file=alu_16buf.pa0

**info** dc convergence failure,

resetting dcon option to 1 and retrying

**info** dc convergence successful

you can increase the efficiency of the

operating point calculation by setting dcon= 1

in the .option statement


******

* lvs netlist generated with icnet by 'hlt0001' on wed apr 29 2015 at 22:39:34

****** operating point information tnom= 25.000 temp= 25.000 *****

***** operating point status is voltage simulation time is 0.

node =voltage node =voltage node =voltage

+ 0:a[0] = 0. 0:a[1] = 0. 0:a[2] = 0.

+ 0:a[3] = 0. 0:b[0] = 0. 0:b[1] = 0.

+ 0:b[2] = 0. 0:b[3] = 0. 0:clk = 0.

+ 0:f[0] = 981.6060m 0:f[1] = 981.6060m 0:f[2] = 981.6072m

+ 0:f[3] = 981.6072m 0:s[0] = 0. 0:s[1] = 0.

+ 0:vdd = 1.0000 1:n$14 = 987.4975m 1:n$253 = 3.5724m

+ 1:n$255 = 987.2324m 1:n$27 = 3.0494m 1:n$457 = 3.5572m

+ 1:n$458 = 3.5776m 1:n$459 = 3.4629m 1:n$460 = 3.4399m

+ 1:n$462 = 2.9194m 1:n$465 = 3.5722m 1:n$672 = 10.2030m

+ 1:n$673 = 9.9967m 1:n$674 = 456.1716m 1:n$675 = 10.2031m

+ 1:n$676 = 10.1986m 1:n$dummy_= 17.6697m 1:n$dummy_= 17.6697m

+ 1:n$dummy_= 17.6883m 1:n$dummy_= 17.6883m 1:nx0 = 873.1322m

+ 1:nx10 = 41.8759m 1:nx126 = 954.0011m 1:nx128 = 877.8123m

+ 1:nx133 = 634.8125m 1:nx135 = 464.6358m 1:nx140 = 645.5544m

+ 1:nx145 = 62.4663m 1:nx149 = 953.9984m 1:nx154 = 63.3984m

+ 1:nx158 = 954.0008m 1:nx32 = 930.7184m 1:nx34 = 457.7854m

+ 1:nx36 = 50.0775m 1:nx58 = 921.5921m 1:nx6 = 942.0705m

+ 1:nx60 = 67.2151m 1:nx62 = 915.7367m 1:nx84 = 939.4112m

+ 1:nx86 = 57.3812m 1:nx88 = 914.6173m 2:n$10 = 245.9733m

+ 2:n$4 = 34.3978m 2:n$5 = 984.6960m 2:n$6 = 20.0491m

+ 2:n$7 = 954.1453m 3:n$10 = 578.6172m 3:n$4 = 31.5792m

+ 3:n$5 = 994.3004m 3:n$6 = 17.8991m 3:n$7 = 808.6386m

+ 6:n$7 = 2.2891m 7:n$7 = 2.2891m 8:n$7 = 2.2890m

+ 9:n$7 = 2.2891m 10:n$1 = 996.9217m 10:n$212 = 29.4059m

+10:n$213 = 16.9806m 10:n$3 = 735.7860m 11:n$1 = 981.0604m

+11:n$212 = 956.1282m 11:n$213 = 2.9837m 11:n$3 = 31.2451m

+12:n$1 = 943.3338m 12:n$212 = 971.3122m 12:n$213 = 23.8631m

+12:n$3 = 3.4247m 13:n$1 = 996.7877m 13:n$212 = 29.2432m

+13:n$213 = 16.9023m 13:n$3 = 735.7202m 14:n$1 = 980.7930m

+14:n$212 = 956.0106m 14:n$213 = 2.7653m 14:n$3 = 35.7230m

+15:n$1 = 944.1433m 15:n$212 = 971.5368m 15:n$213 = 19.2802m

+15:n$3 = 3.4294m 16:n$1022 = 946.0686m 17:n$1022 = 846.7571m

+18:n$1022 = 113.4102m 19:n$4 = 857.2678m 19:n$8 = 17.4558m

+19:n$9 = 301.8323u 20:n$1022 = 946.0686m 21:n$1022 = 107.6177m

+22:n$1022 = 832.6803m 23:n$1022 = 946.0677m 24:n$1022 = 946.0675m

+25:n$1022 = 946.1578m 26:n$1022 = 946.6747m 27:n$1022 = 946.5855m

+28:n$1022 = 849.8958m 29:n$1022 = 946.6647m 30:n$1022 = 946.5853m

+31:n$1 = 998.6955m 31:n$212 = 29.6310m 31:n$213 = 17.2466m

+31:n$3 = 760.6366m 32:n$1 = 980.8087m 32:n$212 = 957.8367m

+32:n$213 = 2.8752m 32:n$3 = 177.6779m 33:n$1 = 187.2465m

+33:n$212 = 956.2938m 33:n$213 = 757.0869m 33:n$3 = 28.2843m

+34:n$1 = 919.8806m 34:n$212 = 967.7967m 34:n$213 = 17.0606m

+34:n$3 = 3.3650m 35:n$1 = 996.9533m 35:n$212 = 29.4306m

+35:n$213 = 16.9925m 35:n$3 = 735.7952m 36:n$1 = 981.0642m

+36:n$212 = 958.0661m 36:n$213 = 3.0176m 36:n$3 = 180.3171m

+37:n$1 = 943.8775m 37:n$212 = 968.0270m 37:n$213 = 17.8392m

+37:n$3 = 3.3685m 37:n$4 = 922.4964m 38:bclk = 5.9492m

+38:bclk- = 941.1957m 38:n$1069 = 983.5051m 38:n$1070 = 899.1962m

+38:n$1071 = 10.4182m 38:n$1072 = 9.6151m 38:n$1073 = 720.3513m

+38:n$1074 = 828.3980m 38:n$845 = 195.2060m 38:n$847 = 42.0287m

+38:n$848 = 973.9694m 38:n$849 = 951.5408m 38:n$851 = 23.7383m

+38:n$852 = 3.1401m 39:bclk = 5.9491m 39:bclk- = 941.1957m

+39:n$1069 = 983.5050m 39:n$1070 = 899.1962m 39:n$1071 = 10.4182m

+39:n$1072 = 9.6153m 39:n$1073 = 720.3513m 39:n$1074 = 828.3980m

+39:n$845 = 194.9010m 39:n$847 = 42.0277m 39:n$848 = 973.9694m

+39:n$849 = 951.5407m 39:n$851 = 23.7383m 39:n$852 = 3.1401m

+40:bclk = 21.9777m 40:bclk- = 962.1077m 40:n$1069 = 994.5827m

+40:n$1070 = 900.4294m 40:n$1071 = 10.4219m 40:n$1072 = 2.5558m

+40:n$1073 = 736.7862m 40:n$1074 = 829.6889m 40:n$845 = 936.3759m

+40:n$847 = 903.1340m 40:n$848 = 981.5629m 40:n$849 = 10.8093m

+40:n$851 = 740.7616m 40:n$852 = 24.0869m 41:bclk = 21.9564m

+41:bclk- = 962.1075m 41:n$1069 = 994.6225m 41:n$1070 = 900.4279m

+41:n$1071 = 10.4219m 41:n$1072 = 2.5523m 41:n$1073 = 736.7859m

+41:n$1074 = 829.6874m 41:n$845 = 936.0202m 41:n$847 = 902.8182m

+41:n$848 = 981.5627m 41:n$849 = 10.8075m 41:n$851 = 740.2736m

+41:n$852 = 24.0770m

******







powavg= 2.4379E-01

powrms= 4.1507E-01

x

time current

vdd

0. -50.9247m

1.00000n 605.9220m

2.00000n -65.4088m

3.00000n 580.7015m

4.00000n -64.0738m

5.00000n 563.9858m

6.00000n -80.0305m

7.00000n 538.2293m

8.00000n -100.0482m

9.00000n 541.0778m

10.00000n -81.0236m

11.00000n 552.6719m

12.00000n -77.2905m

13.00000n 557.7865m

14.00000n -72.7271m

15.00000n 559.3820m

16.00000n -72.8648m

17.00000n 507.9179m

18.00000n -101.4353m

19.00000n 550.1230m

20.00000n -81.7512m

21.00000n 549.3658m

22.00000n -90.3706m

23.00000n 541.2793m

24.00000n -83.5393m

25.00000n 541.6009m

26.00000n -88.5356m

27.00000n 539.1702m

28.00000n -95.8650m

29.00000n 541.6500m

30.00000n -92.4869m

31.00000n 539.8664m

32.00000n -96.1870m

33.00000n 498.8510m

34.00000n -89.7602m

35.00000n 561.2986m

36.00000n -69.0680m

37.00000n 568.5992m

38.00000n -66.7022m

39.00000n 569.7653m

40.00000n -66.2231m

41.00000n 560.1159m

42.00000n -66.9320m

43.00000n 567.1079m

44.00000n -65.9184m

45.00000n 566.4975m

46.00000n -67.2757m

47.00000n 567.9439m

48.00000n -65.0374m

49.00000n 515.9252m

50.00000n -94.8013m

51.00000n 558.8617m

52.00000n -72.8799m

53.00000n 558.6513m

54.00000n -78.2381m

55.00000n 544.8504m

56.00000n -101.3715m

57.00000n 52.045517m

58.00000n -86.3318m

59.00000n 548.5074m

60.00000n -90.0243m

61.00000n 541.1770m

62.00000n -87.5738m

63.00000n 549.5090m

64.00000n -81.3220m

65.00000n 505.9357m

66.00000n -86.4111m

67.00000n 556.7095m

68.00000n -77.0642m

69.00000n 555.1292m

70.00000n -81.7917m

71.00000n 557.1286m

72.00000n -73.8913m

73.00000n 550.8997m

74.00000n -73.0364m

75.00000n 559.4014m

76.00000n -73.3908m

77.00000n 558.8625m

78.00000n -71.6381m

79.00000n 560.2347m

80.00000n -72.4466m

81.00000n 508.0690m

82.00000n -100.6344m

83.00000n 550.3982m

84.00000n -80.6771m

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1.01500u 1.5826k

1.01600u 78.0719m

1.01700u 1.5824k

1.01800u 84.0507m

1.01900u 1.5834k

1.02000u 84.5056m

1.02100u 1.5834k

1.02200u 84.2299m

1.02300u 1.5821k

1.02400u 91.0751m

1.02500u 1.5820k

1.02600u 83.1793m

1.02700u 1.5833k

1.02800u 65.6561m

1.02900u 1.5834k

1.03000u 62.2891m

1.03100u 1.5828k

1.03200u 58.5170m

1.03300u 1.5825k

1.03400u 61.1771m

1.03500u 1.5815k

1.03600u 61.5089m

1.03700u 1.5814k

1.03800u 61.3676m

1.03900u 1.5830k

1.04000u 61.4271m

1.04100u 1.5832k

1.04200u 72.2749m

1.04300u 1.5829k

1.04400u 69.0258m

1.04500u 1.5821k

1.04600u 75.9483m

1.04700u 1.5809k

1.04800u 98.4322m

1.04900u 1.5818k

1.05000u 78.5919m

1.05100u 1.5823k

1.05200u 83.8275m

1.05300u 1.5832k

1.05400u 84.2889m

1.05500u 1.5820k

1.05600u 76.4231m

1.05700u 1.5820k

1.05800u 82.2971m

1.05900u 1.5832k

1.06000u 68.1693m

1.06100u 1.5832k

1.06200u 76.0297m

1.06300u 1.5816k

1.06400u 66.3889m

1.06500u 1.5809k

1.06600u 77.6146m

1.06700u 1.5814k

1.06800u 69.0671m

1.06900u 1.5823k

1.07000u 65.2612m

1.07100u 1.5810k

1.07200u 65.3344m

1.07300u 1.5809k

1.07400u 63.1650m

1.07500u 1.5822k

1.07600u 67.6407m

1.07700u 1.5817k

1.07800u 73.8971m

1.07900u 1.5806k

1.08000u 64.9794m

1.08100u 1.5806k

1.08200u 68.3370m

1.08300u 1.5816k

1.08400u 73.7490m

1.08500u 1.5804k

1.08600u 86.3285m

1.08700u 1.5812k

1.08800u 88.1065m

1.08900u 1.5819k

1.09000u 75.5321m

1.09100u 1.5829k

1.09200u 70.3159m

1.09300u 1.5823k

1.09400u 82.5388m

1.09500u 1.5821k

1.09600u 71.6771m

1.09700u 1.5821k

1.09800u 79.0370m

1.09900u 1.5839k

1.10000u 87.0172m

1.10100u 1.5830k

1.10200u 77.5442m

1.10300u 1.5820k

1.10400u 73.7701m

1.10500u 1.5819k

1.10600u 81.8102m

1.10700u 1.5834k

1.10800u 77.3383m

1.10900u 1.5823k

1.11000u 90.1998m

1.11100u 1.5817k

1.11200u 68.7325m

1.11300u 1.5809k

1.11400u 70.5891m

1.11500u 1.5811k

1.11600u 77.6237m

1.11700u 1.5805k

1.11800u 91.6438m

1.11900u 1.5817k

1.12000u 96.0743m

1.12100u 1.5828k

1.12200u 75.9490m

1.12300u 1.5824k

1.12400u 69.6411m

1.12500u 1.5821k

1.12600u 76.6603m

1.12700u 1.5809k

1.12800u 100.8382m

1.12900u 1.5818k

1.13000u 79.0690m

1.13100u 1.5823k

1.13200u 84.9923m

1.13300u 1.5832k

1.13400u 82.9154m

1.13500u 1.5820k

1.13600u 75.9967m

1.13700u 1.5831k

1.13800u 76.1998m

1.13900u 1.5831k

1.14000u 76.4700m

1.14100u 1.5831k

1.14200u 76.6070m

1.14300u 1.5831k

1.14400u 76.7132m

1.14500u 1.5831k

1.14600u 76.8014m

1.14700u 1.5831k

1.14800u 76.8681m

1.14900u 1.5831k

1.15000u 76.9125m

1.15100u 1.5831k

1.15200u 76.9380m

1.15300u 1.5831k

1.15400u 76.9498m

1.15500u 1.5831k

1.15600u 76.9529m

1.15700u 1.5831k

1.15800u 76.9511m

1.15900u 2.0078k

1.16000u 76.9467m

1.16100u 1.5831k

1.16200u 76.9423m

1.16300u 1.5831k

1.16400u 76.9378m

1.16500u 1.5831k

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1.16700u 1.5831k

1.16800u 76.9304m

1.16900u 1.5831k

1.17000u 76.9278m

1.17100u 1.5831k

1.17200u 76.9257m

1.17300u 1.5831k

1.17400u 76.9241m

1.17500u 1.5831k

1.17600u 76.9230m

1.17700u 1.5831k

1.17800u 76.9220m

1.17900u 1.5831k

1.18000u 76.9214m

1.18100u 1.5831k

1.18200u 76.9208m

1.18300u 1.5831k

1.18400u 76.9205m

1.18500u 1.5831k

1.18600u 76.9201m

1.18700u 1.5831k

1.18800u 76.9200m

1.18900u 1.5831k

1.19000u 76.9198m

1.19100u 1.5831k

1.19200u 76.9198m

1.19300u 1.5831k

1.19400u 76.9196m

1.19500u 1.5831k

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1.19700u 1.5831k

1.19800u 76.9195m

1.19900u 1.5831k

1.20000u 76.9196m

y

***** job concluded


******


****** job statistics summary tnom= 25.000 temp= 25.000 *****

****** Machine Information ******

CPU:

model name : Intel(R) Xeon(R) CPU X5650 @ 2.67GHz

cpu MHz : 2661.000

OS:

Linux version 2.6.32-504.12.2.el6.x86_64 ([email protected]) (

gcc version 4.4.7 20120313 (Red Hat 4.4.7-11) (GCC) ) #1 SMP Wed Mar 11 22:03:1

4 UTC 2015

****** HSPICE Threads Information ******

Command Line Threads Count : 1

Available CPU Count : 24

Actual Model Evaluation(Load) Threads Count : 1

Actual Solver Threads Count : 1

****** Circuit Statistics ******

# nodes = 2485 # elements = 574

# resistors = 0 # capacitors = 0 # inductors = 0

# mutual_inds = 0 # vccs = 0 # vcvs = 0

# cccs = 0 # ccvs = 0 # volt_srcs = 2

# curr_srcs = 0 # diodes = 0 # bjts = 0

# jfets = 0 # mosfets = 572 # U elements = 0

# T elements = 0 # W elements = 0 # B elements = 0

# S elements = 0 # P elements = 0 # va device = 0

# vector_srcs = 10

****** Runtime Statistics (seconds) ******

analysis time # points tot. iter conv.iter

op point 0.41 1 142

transient 962.78 1201 802072 92923 rev= 2169

readin 0.01

errchk 0.01

setup 0.28

output 0.01

peak memory used 84.57 megabytes

total cpu time 963.49 seconds

total elapsed time 966.64 seconds

job started at 23:04:38 04/29/2015

job ended at 23:20:45 04/29/2015

lic: Release hspice token(s)

Appendix IV. HPSICE without Buffer Modifications

Using: /usr/bin/time -p /linux_apps/synopsys/v2.5/hspice/hspice/linux/hspice -i alu3.sp


Copyright (C) 2010 Synopsys, Inc. All Rights Reserved.

Unpublished-rights reserved under US copyright laws.

This program is protected by law and is subject to the

terms and conditions of the license agreement from Synopsys.

Use of this program is your acceptance to be bound by the

license agreement. HSPICE is the trademark of Synopsys, Inc.

Input File: alu3.sp

Command line options: -i alu3.sp

lic: No 'setenv LM_LICENSE_FILE' in current environment'

lic:

lic: FLEXlm: v10.8

lic: USER: hlt0001 HOSTNAME: eelnx165.eng.auburn.edu

lic: HOSTID: 00101897217b PID: 16285

lic: Using FLEXlm license file:

lic: [email protected]

lic: Checkout 1 hspice

lic: License/Maintenance for hspice will expire on 21-jul-2015/2014.09

lic: 1(in_use)/50(total) FLOATING license(s) on SERVER perseus.eng.auburn.edu

lic:

Init: read install configuration file: /linux_apps/synopsys/v2.5/hspice/hspice/meta.cfg

**info** (alu3.sp:15) DC voltage reset to initial transient source value in source 0:vclk new dc= 0.0000D+00

**warning**(nmos:m_i$218)Warning: Acde = 0.235521 may be too small in BSIM4 model with w=2e-06 l=4e-07.

**info** set option symb=1 internally to help for convergence.

*****************************************************************

****** option summary

******

runlvl = 3 bypass = 2

Opening plot unit= 15

file=alu3.pa0

**info** dc convergence failure,

resetting dcon option to 1 and retrying

**info** dc convergence successful

you can increase the efficiency of the

operating point calculation by setting dcon= 1

in the .option statement


******


****** operating point information tnom= 25.000 temp= 25.000 *****

***** operating point status is voltage simulation time is 0.

node =voltage node =voltage node =voltage

+ 0:a[0] = 0. 0:a[1] = 0. 0:a[2] = 0.

+ 0:a[3] = 0. 0:b[0] = 0. 0:b[1] = 0.

+ 0:b[2] = 0. 0:b[3] = 0. 0:clk = 0.

+ 0:f[0] = 981.6060m 0:f[1] = 981.6060m 0:f[2] = 981.6072m

+ 0:f[3] = 3.5281m 0:s[0] = 0. 0:s[1] = 0.

+ 0:vdd = 1.0000 1:n$dummy_= 17.6697m 1:n$dummy_= 17.6697m

+ 1:n$dummy_= 17.6883m 1:n$dummy_= 965.9016m 1:nx0 = 873.1078m

+ 1:nx10 = 41.8102m 1:nx126 = 953.9994m 1:nx128 = 877.8285m

+ 1:nx133 = 903.0866m 1:nx135 = 22.9859m 1:nx140 = 953.9981m

+ 1:nx145 = 82.4681m 1:nx149 = 953.9983m 1:nx154 = 63.3974m

+ 1:nx158 = 954.0006m 1:nx32 = 920.6560m 1:nx34 = 42.6686m

+ 1:nx36 = 48.0944m 1:nx58 = 921.5952m 1:nx6 = 930.3478m

+ 1:nx60 = 67.2929m 1:nx62 = 916.4608m 1:nx8 = 69.0572m

+ 1:nx84 = 939.4111m 1:nx86 = 57.3802m 1:nx88 = 914.6115m

+ 2:n$1 = 996.7850m 2:n$212 = 29.2344m 2:n$213 = 16.8978m

+ 2:n$3 = 735.7145m 3:n$1 = 980.7912m 3:n$212 = 955.8328m

+ 3:n$213 = 2.7542m 3:n$3 = 23.8827m 4:n$1 = 230.8489m

+ 4:n$212 = 958.6329m 4:n$213 = 693.3123m 4:n$3 = 26.3030m

+ 5:n$1 = 919.8689m 5:n$212 = 967.7967m 5:n$213 = 17.0606m

+ 5:n$3 = 3.3650m 6:n$1 = 996.8416m 6:n$212 = 29.3222m

+ 6:n$213 = 16.9401m 6:n$3 = 735.7516m 7:n$1 = 980.8070m

+ 7:n$212 = 956.0076m 7:n$213 = 2.8707m 7:n$3 = 36.7413m

+ 8:n$1 = 950.0687m 8:n$212 = 969.7338m 8:n$213 = 4.4478m

+ 8:n$3 = 3.3988m 8:n$4 = 931.5238m 9:bclk = 3.1331m

+ 9:bclk- = 935.0043m 9:n$1069 = 983.4855m 9:n$1070 = 187.3166m

+ 9:n$1071 = 953.1726m 9:n$1072 = 8.2988m 9:n$1073 = 38.0333m

+ 9:n$1074 = 71.5951m 9:n$845 = 192.7886m 9:n$847 = 41.8670m

+ 9:n$848 = 970.7182m 9:n$849 = 951.5327m 9:n$851 = 23.5893m

+ 9:n$852 = 3.1399m 10:bclk = 5.9490m 10:bclk- = 941.1957m

+10:n$1069 = 983.5050m 10:n$1070 = 899.1962m 10:n$1071 = 10.4182m

+10:n$1072 = 9.6154m 10:n$1073 = 720.3513m 10:n$1074 = 828.3980m

+10:n$845 = 194.7086m 10:n$847 = 42.0271m 10:n$848 = 973.9694m

+10:n$849 = 951.5407m 10:n$851 = 23.7384m 10:n$852 = 3.1401m

+11:bclk = 21.9727m 11:bclk- = 962.1077m 11:n$1069 = 994.5922m

+11:n$1070 = 900.4290m 11:n$1071 = 10.4219m 11:n$1072 = 2.5549m

+11:n$1073 = 736.7861m 11:n$1074 = 829.6886m 11:n$845 = 936.2914m

+11:n$847 = 903.0590m 11:n$848 = 981.5628m 11:n$849 = 10.8089m

+11:n$851 = 740.6565m 11:n$852 = 24.0845m 12:bclk = 21.9562m

+12:bclk- = 962.1075m 12:n$1069 = 994.6229m 12:n$1070 = 900.4279m

+12:n$1071 = 10.4219m 12:n$1072 = 2.5522m 12:n$1073 = 736.7859m

+12:n$1074 = 829.6874m 12:n$845 = 936.0173m 12:n$847 = 902.8156m

+12:n$848 = 981.5627m 12:n$849 = 10.8075m 12:n$851 = 740.2692m

+12:n$852 = 24.0769m 13:n$10 = 246.0392m 13:n$4 = 34.3973m

+13:n$5 = 985.7791m 13:n$6 = 1.045040m 13:n$7 = 954.1487m

+14:n$10 = 225.3191m 14:n$4 = 4.045963m 14:n$5 = 993.1085m

+14:n$6 = 2.5564m 14:n$7 = 954.3407m 15:n$4 = 935.6732m

+15:n$8 = 28.0504m 15:n$9 = 4.4372m 18:n$7 = 2.2892m

+19:n$7 = 2.2892m 20:n$7 = 2.2892m 21:n$7 = 2.2892m

+22:n$1 = 996.9234m 22:n$212 = 29.4055m 22:n$213 = 16.9802m

+22:n$3 = 735.7840m 23:n$1 = 980.8183m 23:n$212 = 955.9104m

+23:n$213 = 2.9836m 23:n$3 = 31.2444m 24:n$1 = 943.3310m

+24:n$212 = 971.3121m 24:n$213 = 23.8630m 24:n$3 = 3.4247m

+25:n$1 = 996.7895m 25:n$212 = 29.2428m 25:n$213 = 16.9019m

+25:n$3 = 735.7182m 26:n$1 = 980.7930m 26:n$212 = 956.0111m

+26:n$213 = 2.7653m 26:n$3 = 35.7603m 27:n$1 = 944.9409m

+27:n$212 = 972.0424m 27:n$213 = 28.2400m 27:n$3 = 3.4411m

******







powavg= 3.3691E-01

powrms= 4.6810E-01

x

time current

vdd

0. -1.1714m

1.00000n 655.6682m

2.00000n -1.2606m

3.00000n 655.5241m

4.00000n -1.2909m

5.00000n 654.9913m

6.00000n -1.5347m

7.00000n 656.1865m

8.00000n -1.3267m

9.00000n 656.1687m

10.00000n -1.5987m

11.00000n 655.7515m

12.00000n -1.3343m

13.00000n 655.6221m

14.00000n -1.5053m

15.00000n 656.7555m

16.00000n -1.2516m

17.00000n 655.4306m

18.00000n -1.9147m

19.00000n 655.2952m

20.00000n -1.6063m

21.00000n 655.6795m

22.00000n -1.3842m

23.00000n 655.5338m

24.00000n -1.2929m

25.00000n 654.8334m

26.00000n -1.5525m

27.00000n 655.0286m

28.00000n -1.2990m

29.00000n 654.2925m

30.00000n -1.5035m

31.00000n 656.0927m

32.00000n -1.2470m

33.00000n 655.8116m

34.00000n -1.7742m

35.00000n 656.2148m

36.00000n -1.4233m

37.00000n 655.4938m

38.00000n -1.6173m

39.00000n 656.7101m

40.00000n -1.3995m

41.00000n 655.4449m

42.00000n -1.6155m

43.00000n 655.6061m

44.00000n -1.3589m

45.00000n 654.9036m

46.00000n -1.5523m

47.00000n 656.7152m

48.00000n -1.3345m

49.00000n 655.9595m

50.00000n -1.7226m

51.00000n 655.3562m

52.00000n -1.6281m

53.00000n 654.8934m

54.00000n -1.2651m

55.00000n 655.5647m

56.00000n -1.3232m

57.00000n 655.9828m

58.00000n -1.5689m

59.00000n 654.6700m

60.00000n -1.3977m

61.00000n 655.5611m

62.00000n -1.5377m

63.00000n 655.6789m

64.00000n -1.3035m

65.00000n 655.5236m

66.00000n -1.6252m

67.00000n 656.0494m

68.00000n -1.3436m

69.00000n 655.0006m

70.00000n -1.5417m

71.00000n 656.2104m

72.00000n -1.3274m

73.00000n 656.1721m

74.00000n -1.5997m

75.00000n 655.7506m

76.00000n -1.3353m

77.00000n 655.6227m

78.00000n -1.5055m

79.00000n 656.7558m

80.00000n -1.2516m

81.00000n 655.3789m

82.00000n -1.8684m

83.00000n 655.4112m

84.00000n -1.6071m

85.00000n 655.3465m

86.00000n -1.4053m

87.00000n 655.7486m

88.00000n -1.3617m

89.00000n 655.0475m

90.00000n -1.5469m

91.00000n 655.1922m

92.00000n -1.3230m

93.00000n 654.4827m

94.00000n -1.5471m

95.00000n 656.2985m

96.00000n -1.2904m

97.00000n 655.3697m

98.00000n -1.7550m

99.00000n 655.7981m

100.00000n -1.7779m

101.00000n 655.5771m

102.00000n -1.5511m

103.00000n 656.7264m

104.00000n -1.3851m

105.00000n 655.4534m

106.00000n -1.6028m

107.00000n 655.6205m

108.00000n -1.3489m

109.00000n 654.9161m

110.00000n -1.5411m

111.00000n 656.7276m

112.00000n -1.3222m

113.00000n 655.9718m

114.00000n -1.7107m

115.00000n 655.3667m

116.00000n -1.6161m

117.00000n 654.9050m

118.00000n -1.2536m

119.00000n 655.5763m

120.00000n -1.3117m

121.00000n 655.9945m

122.00000n -1.5575m

123.00000n 654.6921m

124.00000n -1.3859m

125.00000n 655.5721m

126.00000n -1.5263m

127.00000n 655.6904m

128.00000n -1.2920m

129.00000n 655.5203m

130.00000n -1.6853m

131.00000n 655.9586m

132.00000n -1.4709m

133.00000n 654.9879m

134.00000n -1.4002m

135.00000n 655.6975m

136.00000n -1.4113m

137.00000n 656.5475m

138.00000n -1.5340m

139.00000n 655.8676m

140.00000n -1.2662m

141.00000n 656.6363m

142.00000n -1.3930m

143.00000n 656.4088m

144.00000n -1.3266m

145.00000n 656.3228m

146.00000n -1.8488m

147.00000n 654.2765m

148.00000n -1.7281m

149.00000n 656.4730m

150.00000n -1.5323m

151.00000n 655.2980m

152.00000n -1.4397m

153.00000n 654.8519m

154.00000n -1.6415m

155.00000n 655.5012m

156.00000n -1.3664m

157.00000n 656.0963m

158.00000n -1.4350m

159.00000n 655.3133m

160.00000n -1.2805m

161.00000n 655.7646m

162.00000n -1.8963m

163.00000n 655.4801m

164.00000n -1.4077m

165.00000n 655.4059m

166.00000n -1.4519m

167.00000n 656.1578m

168.00000n -1.3359m

169.00000n 655.4564m

170.00000n -1.6025m

171.00000n 655.6179m

172.00000n -1.3477m

173.00000n 654.9161m

174.00000n -1.5400m

175.00000n 656.7272m

176.00000n -1.3222m

177.00000n 655.9718m

178.00000n -1.7106m

179.00000n 655.3669m

180.00000n -1.6180m

181.00000n 654.9511m

182.00000n -1.2529m

183.00000n 655.5768m

184.00000n -1.3117m

185.00000n 655.9944m

186.00000n -1.5578m

187.00000n 654.6639m

188.00000n -1.3862m

189.00000n 655.5726m

190.00000n -1.5263m

191.00000n 655.6902m

192.00000n -1.2919m

193.00000n 655.5207m

194.00000n -1.6853m

195.00000n 655.9584m

196.00000n -1.4710m

197.00000n 654.9880m

198.00000n -1.4001m

199.00000n 655.6975m

200.00000n -1.4113m

201.00000n 656.5475m

202.00000n -1.5339m

203.00000n 655.8676m

204.00000n -1.2662m

205.00000n 656.6361m

206.00000n -1.3929m

207.00000n 656.4077m

208.00000n -1.3265m

209.00000n 656.4208m

210.00000n -1.6630m

211.00000n 655.2291m

212.00000n -1.4362m

213.00000n 655.4927m

214.00000n -1.4462m

215.00000n 655.9016m

216.00000n -1.2928m

217.00000n 654.8202m

218.00000n -1.6279m

219.00000n 656.8359m

220.00000n -1.3156m

221.00000n 656.1671m

222.00000n -1.4103m

223.00000n 656.3666m

224.00000n -1.2426m

225.00000n 655.2137m

226.00000n -1.8540m

227.00000n 655.4077m

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921.00000n 656.0045m

922.00000n -1.5490m

923.00000n 654.7038m

924.00000n -1.3744m

925.00000n 655.5834m

926.00000n -1.5148m

927.00000n 655.7020m

928.00000n -1.2805m

929.00000n 655.5176m

930.00000n -1.7468m

931.00000n 655.9232m

932.00000n -1.4344m

933.00000n 655.6193m

934.00000n -1.4569m

935.00000n 655.5648m

936.00000n -1.2246m

937.00000n 655.0288m

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939.00000n 656.7449m

940.00000n -1.2538m

941.00000n 656.3005m

942.00000n -1.4468m

943.00000n 656.2421m

944.00000n -1.1916m

945.00000n 655.2229m

946.00000n -1.7679m

947.00000n 655.5685m

948.00000n -1.6103m

949.00000n 655.5310m

950.00000n -1.5350m

951.00000n 655.4145m

952.00000n -1.3116m

953.00000n 654.3421m

954.00000n -1.5982m

955.00000n 656.2487m

956.00000n -1.3510m

957.00000n 655.7032m

958.00000n -1.4758m

959.00000n 655.8255m

960.00000n -1.2675m

961.00000n 654.7865m

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963.00000n 654.8727m

964.00000n -1.7344m

965.00000n 655.8215m

966.00000n -1.4963m

967.00000n 656.6286m

968.00000n -1.3577m

969.00000n 655.4795m

970.00000n -1.5778m

971.00000n 655.6430m

972.00000n -1.3252m

973.00000n 654.9406m

974.00000n -1.5166m

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976.00000n -1.2977m

977.00000n 655.9962m

978.00000n -1.6864m

979.00000n 655.3874m

980.00000n -1.5935m

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988.00000n -1.3629m

989.00000n 655.5949m

990.00000n -1.5033m

991.00000n 655.7135m

992.00000n -1.2690m

993.00000n 655.5144m

994.00000n -1.8021m

995.00000n 655.8313m

996.00000n -1.5590m

997.00000n 655.6500m

998.00000n -1.3033m

999.00000n 655.0870m

1.00000u -1.2900m

1.00100u 655.8728m

1.00200u -1.4805m

1.00300u 656.3806m

1.00400u -1.3126m

1.00500u 656.6558m

1.00600u -1.3564m

1.00700u 656.0419m

1.00800u -1.2089m

1.00900u 656.3498m

1.01000u -1.7489m

1.01100u 654.9390m

1.01200u -1.5225m

1.01300u 656.5236m

1.01400u -1.5313m

1.01500u 654.6928m

1.01600u -1.4272m

1.01700u 655.8503m

1.01800u -1.6055m

1.01900u 655.1027m

1.02000u -1.3498m

1.02100u 655.4336m

1.02200u -1.5714m

1.02300u 655.5332m

1.02400u -1.3404m

1.02500u 655.9900m

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1.02700u 655.4819m

1.02800u -1.5581m

1.02900u 656.0457m

1.03000u -1.5017m

1.03100u 656.2107m

1.03200u -1.3132m

1.03300u 655.4729m

1.03400u -1.5789m

1.03500u 655.6449m

1.03600u -1.3222m

1.03700u 654.9404m

1.03800u -1.5156m

1.03900u 656.7518m

1.04000u -1.2976m

1.04100u 655.9962m

1.04200u -1.6863m

1.04300u 655.3877m

1.04400u -1.5953m

1.04500u 654.9740m

1.04600u -1.2297m

1.04700u 655.5996m

1.04800u -1.2887m

1.04900u 656.0160m

1.05000u -1.5375m

1.05100u 654.7154m

1.05200u -1.3629m

1.05300u 655.5925m

1.05400u -1.5033m

1.05500u 655.7135m

1.05600u -1.2690m

1.05700u 655.5152m

1.05800u -1.8025m

1.05900u 655.8305m

1.06000u -1.5575m

1.06100u 655.6493m

1.06200u -1.3029m

1.06300u 655.0872m

1.06400u -1.2899m

1.06500u 655.8915m

1.06600u -1.4806m

1.06700u 656.3807m

1.06800u -1.3126m

1.06900u 656.6558m

1.07000u -1.3564m

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1.07200u -1.2089m

1.07300u 656.4687m

1.07400u -1.6117m

1.07500u 655.7718m

1.07600u -1.4734m

1.07700u 655.4624m

1.07800u -1.3994m

1.07900u 656.2339m

1.08000u -1.2666m

1.08100u 655.5358m

1.08200u -1.5243m

1.08300u 655.6971m

1.08400u -1.2713m

1.08500u 654.9951m

1.08600u -1.4625m

1.08700u 656.8060m

1.08800u -1.2442m

1.08900u 655.7684m

1.09000u -1.7893m

1.09100u 655.4425m

1.09200u -1.4747m

1.09300u 655.3439m

1.09400u -1.4507m

1.09500u 654.5246m

1.09600u -1.4230m

1.09700u 656.0396m

1.09800u -1.6324m

1.09900u 655.2373m

1.10000u -1.4116m

1.10100u 655.5808m

1.10200u -1.5577m

1.10300u 655.7298m

1.10400u -1.3534m

1.10500u 655.4791m

1.10600u -1.7969m

1.10700u 655.9438m

1.10800u -1.6385m

1.10900u 656.0408m

1.11000u -1.3892m

1.11100u 656.2186m

1.11200u -1.3056m

1.11300u 655.5366m

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1.11500u 655.7028m

1.11600u -1.3117m

1.11700u 654.9529m

1.11800u -1.5044m

1.11900u 656.7642m

1.12000u -1.2854m

1.12100u 656.0085m

1.12200u -1.6744m

1.12300u 655.3981m

1.12400u -1.5833m

1.12500u 654.9857m

1.12600u -1.2182m

1.12700u 655.6113m

1.12800u -1.2773m

1.12900u 656.0289m

1.13000u -1.5233m

1.13100u 654.6985m

1.13200u -1.3511m

1.13300u 655.5756m

1.13400u -1.4918m

1.13500u 655.7252m

1.13600u -1.2575m

1.13700u 656.0391m

1.13800u -1.1527m

1.13900u 656.7125m

1.14000u -1.0171m

1.14100u 656.5520m

1.14200u -964.0831u

1.14300u 656.5538m

1.14400u -964.1555u

1.14500u 656.5539m

1.14600u -964.0696u

1.14700u 656.5538m

1.14800u -964.0931u

1.14900u 656.5535m

1.15000u -964.3130u

1.15100u 656.5536m

1.15200u -964.2155u

1.15300u 656.5536m

1.15400u -964.3032u

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1.15600u -964.2713u

1.15700u 656.5536m

1.15800u -964.2505u

1.15900u 656.5536m

1.16000u -964.2813u

1.16100u 656.5536m

1.16200u -964.2840u

1.16300u 656.5536m

1.16400u -964.2849u

1.16500u 656.5536m

1.16600u -964.2712u

1.16700u 656.5536m

1.16800u -964.2446u

1.16900u 656.5536m

1.17000u -964.2680u

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1.17300u 656.5536m

1.17400u -964.2859u

1.17500u 656.5536m

1.17600u -964.2405u

1.17700u 656.5535m

1.17800u -964.2362u

1.17900u 656.5535m

1.18000u -964.2400u

1.18100u 656.5535m

1.18200u -964.2378u

1.18300u 656.5535m

1.18400u -964.2767u

1.18500u 656.5535m

1.18600u -964.2826u

1.18700u 656.5535m

1.18800u -964.2742u

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1.19800u -964.2990u

1.19900u 656.5535m

1.20000u -964.2905u

y

x

time power

total

0. 1.1714m

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2.00000n 1.2397m

3.00000n 1.5825k

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16.00000n 1.2424m

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20.00000n 1.4849m

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114.00000n 1.6306m

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117.00000n 1.5818k

118.00000n 1.3248m

119.00000n 1.5812k

120.00000n 1.2793m

121.00000n 1.5828k

122.00000n 1.5407m

123.00000n 1.5813k

124.00000n 1.3796m

125.00000n 1.5813k

126.00000n 1.4548m

127.00000n 1.5823k

128.00000n 1.3285m

129.00000n 1.5815k

130.00000n 1.6658m

131.00000n 1.5818k

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133.00000n 1.5809k

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153.00000n 1.5809k

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158.00000n 1.3604m

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161.00000n 1.5817k

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169.00000n 1.5822k

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173.00000n 1.5818k

174.00000n 1.4269m

175.00000n 1.5832k

176.00000n 1.1590m

177.00000n 1.5818k

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181.00000n 1.5808k

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197.00000n 1.5809k

198.00000n 1.3511m

199.00000n 1.5814k

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217.00000n 1.5815k

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221.00000n 1.5827k

222.00000n 1.2565m

223.00000n 1.5829k

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225.00000n 1.5823k

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229.00000n 1.5827k

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233.00000n 1.5818k

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241.00000n 1.5813k

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243.00000n 1.5826k

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255.00000n 1.5832k

256.00000n 1.1468m

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258.00000n 1.6185m

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261.00000n 1.5808k

262.00000n 1.3131m

263.00000n 1.5812k

264.00000n 1.2677m

265.00000n 1.5828k

266.00000n 1.5291m

267.00000n 1.5819k

268.00000n 1.3682m

269.00000n 1.5813k

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272.00000n 1.3170m

273.00000n 1.5815k

274.00000n 1.7407m

275.00000n 1.5818k

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280.00000n 1.1930m

281.00000n 1.5808k

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330.00000n 1.3909m

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333.00000n 1.5818k

334.00000n 1.4270m

335.00000n 1.5832k

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338.00000n 1.6309m

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340.00000n 1.6594m

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342.00000n 1.3248m

343.00000n 1.5812k

344.00000n 1.2793m

345.00000n 1.5828k

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363.00000n 1.5829k

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367.00000n 1.5813k

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370.00000n 1.7998m

371.00000n 1.5819k

372.00000n 1.6353m

373.00000n 1.5810k

374.00000n 1.5647m

375.00000n 1.5818k

376.00000n 1.3369m

377.00000n 1.5819k

378.00000n 1.5523m

379.00000n 1.5822k

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381.00000n 1.5810k

382.00000n 1.4547m

383.00000n 1.5811k

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385.00000n 1.5805k

386.00000n 1.7291m

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389.00000n 1.5817k

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395.00000n 1.5823k

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399.00000n 1.5832k

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1.13600u 1.2940m

1.13700u 1.5828k

1.13800u 1.1677m

1.13900u 1.5833k

1.14000u 968.7658u

1.14100u 1.5830k

1.14200u 962.6200u

1.14300u 1.5830k

1.14400u 962.5967u

1.14500u 1.5830k

1.14600u 962.6003u

1.14700u 1.5830k

1.14800u 962.5900u

1.14900u 1.5830k

1.15000u 962.5839u

1.15100u 1.5830k

1.15200u 962.5810u

1.15300u 1.5830k

1.15400u 962.5790u

1.15500u 1.5830k

1.15600u 962.5772u

1.15700u 1.5830k

1.15800u 962.5757u

1.15900u 1.5830k

1.16000u 962.5745u

1.16100u 1.5830k

1.16200u 962.5736u

1.16300u 1.5830k

1.16400u 962.5730u

1.16500u 1.5830k

1.16600u 962.5730u

1.16700u 1.5830k

1.16800u 962.5733u

1.16900u 1.5830k

1.17000u 962.5743u

1.17100u 1.5830k

1.17200u 962.5756u

1.17300u 1.5830k

1.17400u 962.5771u

1.17500u 1.5830k

1.17600u 962.5785u

1.17700u 1.5830k

1.17800u 962.5794u

1.17900u 1.5830k

1.18000u 962.5799u

1.18100u 1.5830k

1.18200u 962.5803u

1.18300u 1.5830k

1.18400u 962.5804u

1.18500u 1.5830k

1.18600u 962.5806u

1.18700u 1.5830k

1.18800u 962.5806u

1.18900u 1.5830k

1.19000u 962.5807u

1.19100u 1.5830k

1.19200u 962.5808u

1.19300u 1.5830k

1.19400u 962.5807u

1.19500u 1.5830k

1.19600u 962.5807u

1.19700u 1.5830k

1.19800u 962.5807u

1.19900u 1.5830k

1.20000u 962.5808u

y

***** job concluded


******


****** job statistics summary tnom= 25.000 temp= 25.000 *****

****** Machine Information ******

CPU:

model name : Intel(R) Xeon(R) CPU X5650 @ 2.67GHz

cpu MHz : 1862.000

OS:

Linux version 2.6.32-504.12.2.el6.x86_64 ([email protected]) (

gcc version 4.4.7 20120313 (Red Hat 4.4.7-11) (GCC) ) #1 SMP Wed Mar 11 22:03:1

4 UTC 2015

****** HSPICE Threads Information ******

Command Line Threads Count : 1

Available CPU Count : 24

Actual Model Evaluation(Load) Threads Count : 1

Actual Solver Threads Count : 1

****** Circuit Statistics ******

# nodes = 1337 # elements = 294

# resistors = 0 # capacitors = 0 # inductors = 0

# mutual_inds = 0 # vccs = 0 # vcvs = 0

# cccs = 0 # ccvs = 0 # volt_srcs = 2

# curr_srcs = 0 # diodes = 0 # bjts = 0

# jfets = 0 # mosfets = 292 # U elements = 0

# T elements = 0 # W elements = 0 # B elements = 0

# S elements = 0 # P elements = 0 # va device = 0

# vector_srcs = 10

****** Runtime Statistics (seconds) ******

analysis time # points tot. iter conv.iter

op point 0.15 1 105

transient 736.94 1201 798535 93062 rev= 2611

readin 0.02

errchk 0.00

setup 0.01

output 0.01

peak memory used 81.56 megabytes

total cpu time 737.13 seconds

total elapsed time 739.33 seconds

job started at 22:20:26 04/29/2015

job ended at 22:32:45 04/29/2015

lic: Release hspice token(s)

4-Bit ALU Circuit Glitch Reduction for Power …agrawvd/COURSE/E6270_Spr15/PROJECT/REPORTS/...4-Bit...

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