4-1 EE 319K Introduction to Embedded Systems Lecture 4: Arithmetic overflow, Branches, Control...

4-1

EE 319KIntroduction to Embedded Systems

Lecture 4: Arithmetic overflow, Branches, Control Structures,

Abstraction & Refinement

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

4-2

AgendaRecap

DebuggingI/O

o Switch and LED interfacingC Programming

o Random number generator, NOT gate in Keil

OutlineArithmetic OverflowConditional BranchesConditional and Iterative Statements

oif, while, for (In assembly and C)Abstraction & Refinement

o Device DriverBard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

4-3

Condition Codes

C set after an unsigned addition if the answer is wrongC cleared after an unsigned subtract if the answer is wrongV set after a signed addition or subtraction if the answer is wrong

Bit Name Meaning after add or sub

N negative result is negative

Z zero result is zero

V overflow signed overflow

C carry unsigned overflow


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0

64

128

192

255

96160

+64

32224

+64

0

64

128

192

255

96+64 224+64

8-bit unsigned number wheel

C bit Cleared

C bit Set

The carry bit, C, is set after an unsigned addition when the result is incorrect.

The carry bit, C, is clear after an unsigned subtraction when the result is incorrect.


4-5

160-64 32-64

8-bit unsigned number wheel

C bit Set C bit Cleared

-64

-640

64

128

192

255

96160

32224

0

64

128

192

255

The carry bit, C, is set after an unsigned addition when the result is incorrect.

The carry bit, C, is clear after an unsigned subtraction when the result is incorrect.


4-6

Trick (unsigned)

1. Convert both numbers to unsigned2. Perform addition or subtraction3. Does the result fit as an unsigned?

• No -> addition C=1, subtraction C=0

• Yes -> addition C=0, subtraction C=1

For example: 255 + 5 = 260, C = 1 and the actual answer is 260-256 = 4


4-7

-32+64 96+64

8-bit signed number wheel

V bit Cleared V bit Set

-1+64

0

64

127

-64

-128

32-32

96-96

-1 0

64

127

-64

-128 +64

The overflow bit, V, is set after a signed addition or subtraction when the result is incorrect.


4-8

32-64 -96-64

8-bit signed number wheel

V bit Cleared V bit Set

-64

-64-1 0

64

127

-64

-128

32-32

96-96

-1 0

64

127

-64

-128

The overflow bit, V, is normally set when we cross over from 127 to -128 while adding or cross over from -128 to 127 while subtracting.


4-9

Trick (signed)

1. Convert both numbers to signed2. Perform addition or subtraction3. Does the result fit as a signed?

• No -> V=1• Yes -> V=0

8-bitExamples: 10 – 5 = 5,

V=0-100 – 100 = -200, V=1


4-10

Addition Summary

Let the 32-bit result R be the result of the 32-bit addition X+Y.

N bit is set if unsigned result is above 231-1 or if signed result is negative. N = R31

Z bit is set if result is zero V bit is set after a signed addition if result is incorrect

C bit is set after an unsigned addition if result is incorrect

313131313131 &&&& | RMXRMXV

313131313131 &&& || XRRMMXC


4-11

Subtraction Summary

Let the 32-bit result R be the result of the 32-bit subtraction X-Y.

N bit is set if unsigned result is above 231-1 or if signed result is negative. N = R31

Z bit is set if result is zero V bit is set after a signed subtraction if result is incorrect

C bit is clear after an unsigned subtraction if result is incorrect

313131313131 &&&& | RMXRMXV

31&31|31&31|31&31 XRRMMXC


4-12

Trick Question

Answer = 159NZVC = 1010

When the subtraction (32 – 129) is performed in an 8-bit system what is the result and the status of

the NZVC bits?


4-13Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

Unsigned Promotion

Promotion involves increasing the precision of the input numbers, and performing the operation at that higher precision

Then truncate the result back to the original precision

Decimal 8-bit 32-bit 224 1110,0000 0000,0000,0000,0000,0000,0000,1110,0000 + 64 +0100,0000 +0000,0000,0000,0000,0000,0000,0100,0000 288 0010,0000 0000,0000,0000,0000,0000,0001,0010,0000


Unsigned Ceiling and Floor

Unsigned add

R =A +B

R=255

RR >255R < 255

end

Promote A to APromote B to B

3232

32 32 32

R=R

323232

32

ok overflow

Unsigned sub

R =A -B

R=0

RR < 0R > 0


3232

32 32 32

R=R

323232

32

ok underflow

end


Signed Promotion

To promote a signed number, we duplicate the sign bit

Decimal 8-bit 32-bit -96 1010,0000 1111,1111,1111,1111,1111,1111,1010,0000 -64 -0100,0000 -0000,0000,0000,0000,0000,0000,0100,0000 -160 0110,0000 1111,1111,1111,1111,1111,1111,0110,0000


Signed Ceiling and Floor

Signed add

R =A +B

R=127

RR >127R < -128

end


3232

32 32 32

R = -128

323232

underflow overflow

Signed sub

R =A -B


3232

32 32 32

R=R32

R=127

RR >127R < -128

end

R = -128

323232

underflow overflow

R=R32

4-17

Conditional Branch Instructions

Unsigned conditional branchfollow SUBS CMN or CMP

BLO target ; Branch if unsigned less than (if C=0, same as BCC)BLS target ; Branch if unsigned less than or equal to (if C=0 or Z=1)

BHS target ; Branch if unsigned greater than or equal to (if C=1, same as BCS)

BHI target ; Branch if unsigned greater than (if C=1 and Z=0)

CMP R0,R1

BLOR0<R1

targetNext instruction

R0≥R1


4-18

Conditional Branch Instructions

Signed conditional branchfollow SUBS CMN or CMP

BLT target ; if signed less than (if (~N&V | N&~V)=1, i.e. if N≠V)

BGE target ; if signed greater than or equal to (if (~N&V | N&~V)=0, i.e. if N=V)

BGT target ; if signed greater than (if (Z | ~N&V | N&~V)=0, i.e. if Z=0 and N=V)

BLE target ; if signed less than or equal to (if (Z | ~N&V | N&~V)=1, i.e. if Z=1 or N≠V)

CMP R0,R1

BLTR0<R1

targetNext instruction

R0≥R1


4-19

Equality Test

Program 5.8. Conditional structures that test for equality.


Assembly code C code LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G == 7 ? BNE next1 ; if not, skip BL GEqual7 ; G == 7 next1

uint32_t G; if(G == 7){ GEqual7(); }

LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G != 7 ? BEQ next2 ; if not, skip BL GNotEqual7 ; G != 7 next2

if(G != 7){ GNotEqual7(); }

4-20

Unsigned Conditional Structures


Assembly code C code LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G > 7? BLS next1 ; if not, skip BL GGreater7 ; G > 7 next1

uint32_t G; if(G > 7){ GGreater7(); }

LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G >= 7? BLO next2 ; if not, skip BL GGreaterEq7 ; G >= 7 next2

if(G >= 7){ GGreaterEq7(); }

LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G < 7? BHS next3 ; if not, skip BL GLess7 ; G < 7 next3

if(G < 7){ GLess7(); }

LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G <= 7? BHI next4 ; if not, skip BL GLessEq7 ; G <= 7 next4

if(G <= 7){ GLessEq7(); }

Program 5.9. Unsigned conditional structures.

4-21

Signed Conditional Structures


Assembly code C code LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G > 7? BLE next1 ; if not, skip BL GGreater7 ; G > 7 next1

int32_t G; if(G > 7){ GGreater7(); }

LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G >= 7? BLT next2 ; if not, skip BL GGreaterEq7 ; G >= 7 next2

if(G >= 7){ GGreaterEq7(); }

LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G < 7? BGE next3 ; if not, skip BL GLess7 ; G < 7 next3

if(G < 7){ GLess7(); }

LDR R2, =G ; R2 = &G LDR R0, [R2] ; R0 = G CMP R0, #7 ; is G <= 7? BGT next4 ; if not, skip BL GLessEq7 ; G <= 7 next4

if(G <= 7){ GLessEq7(); }

Program 5.11. Signed conditional structures.

4-22

If-then-else

G1<=G2

isLessEq isGreater

G1>G2


LDR R2, =G1 ; R2 = &G1 LDR R0, [R2] ; R0 = G1 LDR R2, =G2 ; R2 = &G2 LDR R1, [R2] ; R1 = G2 CMP R0, R1 ; is G1 > G2 ? BHI high ; if so, skip to high low BL isLessEq ; G1 <= G2 B next ; unconditional high BL isGreater ; G1 > G2 next

uint32_t G1,G2; if(G1>G2){ isGreater(); } else{ isLessEq(); }

4-23

While Loops

LDR R4, =G1 ; R4 -> G1 LDR R5, =G2 ; R5 -> G2loop LDR R0, [R5] ; R0 = G2 LDR R1, [R4] ; R1 = G1 CMP R0, R1 ; is G2 <= G1? BLS next ; if so, skip to next BL Body ; body of the loop B loop next

uint32_t G1,G2;while(G2 > G1){ Body();}

G2<=G1Body

G2>G1


4-24

For Loops

i >= 100 Process

i < 100

i = 0

i

i = i+1

for(i=0; i<100; i++){ Process();}

i == 0 Process

i != 0

i = 100

i

i = i-1

for(i=100; i!=0; i--){ Process();}


4-25

For Loops

MOV R4, #0 ; R4 = 0loop CMP R4, #100 ; index >= 100? BHS done ; if so, skip to done BL Process ; process function* ADD R4, R4, #1 ; R4 = R4 + 1 B loop done

for(i=0; i<100; i++){ Process();}

MOV R4, #100 ; R4 = 0loop BL Process ; process function SUBS R4, R4, #1 ; R4 = R4 - 1 BNE loop done

for(i=100; i!=0; i--){ Process();}

Count up

Count down


4-26

System Design

What does being in a state mean? List state parameters

What is the starting state of the system? Define the initial state

What information do we need to collect? List the input data

What information do we need to generate? List the output data

How do we move from one state to another? Actions we could do

What is the desired ending state? Define the ultimate goal


4-27

System Design

Successive RefinementStepwise RefinementSystematic Decomposition


4-28

System Design

Start with a task and decompose the task into a set of simpler subtasks

Subtasks are decomposed into even simpler sub-subtasks

Each subtask is simpler than the task itself

Make design decisionsdocument decisions and subtask

requirementsUltimately, subtask is so simple, it can

be converted to software


4-29

System Design

Four building blocks:“do A then do B” → sequential“do A and B in either order” → sequential

(parallel)“if A, then do B” → conditional“for each A, do B” → iterative“do A until B” → iterative“repeat A over & over forever” → iterative

(condition always true)“on external event do B” → interrupt“every t msec do B” → interrupt


4-30

Successive Refinement


4-31

Successive Refinement

Successive refinement example for iterative approachBard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

4-32

Abstraction - Device Driver

Abstraction allows us to modularize our code and give us the option to expose what we want users to see and hide what we don’t want them to see.

A Device Driver is a good example where abstraction is used to expose public routines that we want users of the driver to call and use private routines to hide driver internals from the user (more on private routines later)


LED Driver (PE0)

LED_Init

LED_Off

LED_On

LED_Toggle

A user simply has to knowwhat a routine expects and what it returns in order to call it (calling convention). Internals do not matter to caller

4-33

Port E LED AbstractionPE0 EQU 0x4005C004 ;bit-specific address Port E bit 0LED_Init LDR R1, =SYSCTL_RCGCGPIO_R ; R1 -> SYSCTL_RCGCGPIO_R LDR R0, [R1] ; previous value ORR R0, R0, #0x00000010 ; activate clock for Port E STR R0, [R1] NOP NOP ; allow time to finish activating LDR R1, =GPIO_PORTE_DIR_R ; R1 -> GPIO_PORTE_DIR_R LDR R0, [R1] ; previous value ORR R0, R0, #0x01 ; PE0 output STR R0, [R1] ; set direction register LDR R1, =GPIO_PORTE_AFSEL_R ; R1 -> GPIO_PORTE_AFSEL_R LDR R0, [R1] ; previous value BIC R0, R0, #0x01 ; disable alt funct STR R0, [R1] ; set alternate function register LDR R1, =GPIO_PORTE_DEN_R ; R1 -> GPIO_PORTE_DEN_R LDR R0, [R1] ; previous value ORR R0, R0, #0x01 ; enable PE0 digital port STR R0, [R1] ; set digital enable register BX LR

Program 4.3. Software interface for an LED on PE0 (SSR_xxx.zip).Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

4-34

Port E LED Abstraction

LED_Off LDR R1, =PE0 ; R1 is 0x4005C004 MOV R0, #0 STR R0, [R1] ; affect just PE0 BX LRLED_On LDR R1, =PE0 ; R1 is 0x4005C004 MOV R0, #1 STR R0, [R1] ; affect just PE0 BX LRLED_Toggle LDR R1, =PE0 ; R1 is 0x4005C004 LDR R0, [R1] ; previous value EOR R0, R0, #1 ; flip bit 0 STR R0, [R1] ; affect just PE0 BX LR

Program 4.3. Software interface for an LED on PE0 (SSR_xxx.zip).


4-1 EE 319K Introduction to Embedded Systems Lecture 4: Arithmetic overflow, Branches, Control...

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