3D TECHNOLOGIES WAFER SERVICES AT LETI FOR ...LETI CONFIDENTIAL CMP annual meeting| Parès Gabriel |...

3D TECHNOLOGIES WAFER SERVICES AT LETI FOR CMP MULTI-PROJECT-WAFER

LETI CONFIDENTIAL CMP annual meeting| Parès Gabriel

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Top chip : 45 nm

Bottom chip (130nm)

Interco

TSV

Board

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AGENDA


Introduction: 3D at Leti

Leti 3D stacks proposed in CMP MPW offer -illustrations

3D technology modules• Process• Illustrations• Design Rules

Work flow

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ABOUT CEA-LETI

Grenoble, France

~100 people working on 3D IC and 3D Packaging Full 200mm & 300mm 3D capabilities

1,700 researchers

50 start‐ups & 365 industrial partners

Over 2,200 patents

250 M€ annual budget

French R&D institute in microelectronics & nanotechnologies from


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MEMS 200Microtech for biology

CMOS 200 mm

Nanotech 300 + 3D 300

Design / layout

Nanoscale Characterization

B2i / applications building

Photonics

LETI organization and Lab overview


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LETI organization and Lab overview

DCOS[silicon component]

DOPT[optical sensors]

DACLE[IC design]

DTSI[Si platform]

SCME[CMOS][3DIC]

SCMS[sensors] [MEMS][μ-systems] [interposers][3D packaging - Integration] Lab for packaging / interposer / 3D integration

LETI

SCPE[Power][Energy] LPI

DTBS[Biology- health]


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IRT NANOELEC – PROGRAMME 3D

• Objectif: Valider une plateforme générique d’intégration 3D (conception, technologies etcaractérisation), permettant le prototypage d’applications.

• Moyens :– Développer les technologies génériques pour l’intégration haute densité– Développement des outils de conception et de méthodologies de tests à l’échelle de la

plaque et du système packagé – Validation sur des démonstrateurs technologiques

+ …. (conf.)

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To solve the following issues : Form factor decrease :

X & Y axis Z axis

Performances improvement Decrease R, C, signal delay Increase device bandwidth Decrease power consumption

Heterogeneous integration Integration of heterogeneous components in the same system

Cost decrease Si surface decrease Reuse of existing Packaging, BEOL & FEOL lines

WHY DO WE NEED 3D INTEGRATION ?


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High performance computing

FPGA Mobile 3D Imaging

High-end servers

From Fujitsu

- 3D stack on interposer- ~150 - 200W

- 4 levels of BE

- 20 Watts- 28 Gbps

- PoP still there!!- Supply chain- 5-10 Watts- 12 - 50 Gbps

- 3D technology for tracker

- <40µm pixels- Read out

circuit at the back

- Ultra fine routing at the interposer backside

Passive /active

3D/2.5D: A “GENERIC” SOLUTION?


HD interposers Coarse interposers

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Particles detectors:Mmw platform:Power amplifier (PA)

4G with TSV:X-rays/particles dead zone free detectors

High perf. Passives (Capa 1µf/mm2)

14x17mm2 detector, Medipix 130nm CMOS

60µm TSV40% size decrease vs. organic

6,5 x 6,5 mm260µm TSV

Active interposersPassive interposers

Medical applications radar, military, space

Fondamental physics

Consumers

3x3 mm2130nm SOI CMOS

60µm TSV

75µm TSV

TSV-LAST COARSE INTERPOSERS DEVELOPMENTS AT LETI (2010 -2014)


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3D ‘GENERIC’ TECHNOLOGY TOOLBOX

Die to Die Die to Substrate Die PlacementThrough Silicon Via

Solder balls

Copper Pillars

µinserts

µtubes

Cu-Cu

Solder balls

Copper pillar

Wire Bonding TSV First

TSV Middle& BS AR10

TSV Last AR1

High precisionP&P

Self Assembly

Wafer To Wafer

Thick Polymer molding

Thin Polymer molding

Thin Oxideplanarization

Handling

Temp. Bonding (slide off)

Temp Bonding(Zonebond)

Face to Face Face to back 3 level stack1 active layer

TSV Last AR2

TSV Last AR3

TSV Last High density

WLUF

Classic Underfill

Permanentbonding

Temp. bonding(Peeling)

WL Molding

DTW Cu-Cu


High throuputP&P

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Passivation

RDL

wafer provided by costumer

Top dies wafer (provided by costumer)

BGA or package (provided by costumer

or OPEN3D)

TSV

Front side UBM

Back side UBM

Bumps

Micro‐bumps

Micro pillars

TECHNOLOGICAL OPEN3DTM OFFER OVERVIEW

Wafers (bottom and/or top dies) provided by costumerTechnological modules implemented by OPEN3DTM : • Through Silicon via (TSV)• Redistribution layer (RDL)• Under Bump Metallization (UBM)

• 3D Interconnections• Components stacking• Packaging with partner collaboration

OPEN3DTM inputs

Costumer inputs


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CMP MPW 3D OPTIONS

Bottom die

Top die Wire bonding

Flip chip stacking +WB

Active interposer

Top die

BGA substrate

Top die

Passive Si interposer

Top die

Passive Si interposer

Top die

TSV last/RDL

Die-to-die

Die-to-substrate

Die-to-passive interposer

active die

Flip chip stacking + TSV last/RDL

BGA substrate

FS RDL/Bumps

µbumps

TSV/BS RDL/Bumps

µbumps

TSV/BS RDL/Bumps


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Bottom dieor interposerCMOS130

Top dieCMOS065

Wire bonding

3D INTERCO FOR FLIP-CHIP ASSEMBLY

3D technological modules fabrication at wafer level with MPW design• Top die: µ-bumps Bottom die: UBM or copper pillarsComponents stacking• Die-to-die• Die-to-wafer• Die-to-passive interposer• Die-to-BGA substrateTechnology nodes offer: • 200 mm: CMOS130, BICMOS9, AMS techno• 300 mm: CMOS65/FDSOI28 (all options)Flip chip by pick&place and solder reflow (collective or thermo-compression): Leti or outsourced

Example

Top die with µbumps Flip-chip assembly


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Micro‐bumps Morphological illustrations

Micro‐bumps before reflow Micro‐bumps after reflow

Micro‐bumps DRM & schematic

Wafer size : 200 mm

Micro‐bumps material : Cu post / SnAg 305 solder

Minimum pitch : 50 µm

Minimum micro‐bumps diameter : 25 µm

Micro‐bumps thickness (typical): Cu 10µm / SnAg 10µm

Top metal

Top passivation

Cu post

Solder alloyMicro‐bumps

Micro‐bumps on C65 D= 25 µm

Micro‐bumps on FDSOI28 D= 18 µm

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OPEN 3D™ TECHNOLOGICAL OFFER MICRO-BUMPS


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Landing micro‐pillars Morphological

Landing micro‐bumps DRM & schematic

Wafer size : 200 mm

Landing micro‐bumps material : Cu post / NiAu protection possible


Minimum landing micro‐bumps diameter : 25 µm

Typical landing micro‐bumps thickness : Cu 10µm / NiAu 1.2µm

Landing micro‐bumps with protective layer Landing micro‐bumps w/o protective layer Landing micro‐pillar on top metal

Top metal

Top passivation

Cu post

Protective layer

Landing micro‐pillars

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OPEN 3D™ TECHNOLOGICAL OFFER LANDING MICRO-PILLARS


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Au capping

Ni diffusion barrier

Cu base

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UBM DRM & schematic

Wafer size : 200 mm

UBM material : TiNiAu

UBM thickness : 1 µm

UBM minimun width : 25 µm

UBM minimun pitch : 50 µm

TSV

Metal 1

RDL

Passivation

Backside UBM

Frontside UBM

UBM Morphological illustration

Backside and frontside UBM possible

On top of Alu or Copper Pad

Different shape possible :

‐ Square

‐ Polygons

‐ Circle

OPEN 3D™ TECHNOLOGICAL OFFER UBM


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Bumps characteristics

Pillars Morphological & electrical results

Bumps

R (m) Elec. Yield

Bumps 50 100 %

Bumps cross section

Solder bump

TSV

Bumps DRM & schematic

Wafer size : 200 mm

Pillars material : Cu stud / SnAg solder


Pillars diameter : 65 µm

Pillars thickness : Cu 35‐40 µm / SnAg 25‐30 µm

TSV

Metal 1

RDL

Passivation

Cu stud

Solder alloyPillars

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OPEN 3D™ TECHNOLOGICAL OFFERSOLDER BUMPS


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Organic substrate

Silicon interposer

Chip 1Chip 2

10µm

Cu TSV

Si-IP

SnAg Solder

Ni

Cu wiring

K. Miyairi et al. IMAPS San Diego 2012J. Charbonnier et al., ESTC Amsterdam 2012

Chip

Si-IP

SAC SolderNi

Cu

DIE-TO-INTERPOSER = ΜBUMPS/ΜPILLARS INTERPOSER TO SUBSTRATE = SOLDER BUMPS

Solder bumps

µbumps/µpillars


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Si interposer CMOS65 with TSV‐last

TSV-LAST AND BACK SIDE RDL FAN-OUT IN SILICON INTERPOSER

Technological modules fabrication at wafer level with MPW design• Front side : Alu pad finish (WB) or µ-pillars (Cu/TiAu) or UBM (TiNiAu) for Flip-chip assembly• Wafer thinning on temporary carrier at 120µm• Back side: TSV, RDL, UBM or solder bumps Components stacking• Die-to-die• Die-to-waferTechnology nodes offer: • 200 mm CMOS130 /BiCMOS9• 300 mm CMOS65

Flip chip by pick&place and solder reflow (collective or thermo-compression)

Top die FDSOI28nm

Passivation

RDL

Front side

Back side UBM

Bumps


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TSV characteristics

TSV DRM & schematicWafer size : 200 mm

Wafer thickness : 120 µm

TSV type : via last / Cu liner

Minimum pitch : 120 µm (for 60µm TSV)

TSV diameter : 60 µm

Aspect Ratio (AR) : from 1:2

TSV Metal liner

Top metal

Dielectric liner

Metal 1

RDL

Passivation

TSV‐last AR 2:1

TSV geometry R (m) C (pF) Elec. Yield Insul. (M) I leak (A)

TSV60 / 120 19.1 0.82 100 % > 1001.3 10‐9 @10V3.1 10‐9 @50V

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TSV morphological & electrical results

Electrical tests results

OPEN 3D™ TECHNOLOGICAL OFFER TSV-LAST


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VIAS LAST / MEDIUM DENSITYMETALLIZATION

Metalization : requires to use low temperature processes (< 250°C / < 200 °C)

Barrier / seed layer deposition : PVD/CVD Ti/Cu deposition

Source : K. Crofton / Aviza / Semicon 2009

Electroplating Cu liner or Cu filling

Choice of electrolyte : 2 or 3 additives

DC or pulse current

Hydrodynamic conditions

Source : Dow

Source : CEA-LETI


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TSV-LAST EXAMPLE

TSV top:oxide liner = 1.5-1.8 µmCu liner= 7.5 µmpassivation cap = 14 µm

TSV bottom cornerOxide liner = 0.43 µmCu liner= 3.7 µm

TSV bottomCu liner = 3 µm


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RDL Morphological & electrical results

Backside Cu RDLRDL characteristics

Insolation between lines I leak @10V (A) Elec. Yield

RDL > 6.0 G 1.6 10‐9 100 %

RDL DRM & schematicWafer size : 200 mm

RDL material : Cu

RDL thickness : 4‐8 µm

RDL minimun width : 20 µm

RDL minimun space : 20 µm

Passivation layer : Polymer (several materials available) or mineral

TSV

Metal 1

RDL

Passivation

Cu RDL integration : Solder bumps on RDL + passivation

Solder bump

RDL

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OPEN 3D™ TECHNOLOGICAL OFFER BACK SIDE RDL


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EXAMPLE 1 = ACTIVE SI INTERPOSERWITH PARTITIONING

Analog & digital partitioning : 45 nm on 130 nm

Technology node splitting : Advanced for digital / Mature for Analog

+ Cost : no need to use advanced techno for mature components

Top chip : 45 nm

Bottom chip (130nm)

Interco

TSV

Board

Source : CEA-LETI / ST Micro BS pillars

TSVInter strata pillars

Final componentLETI CONFIDENTIAL CMP annual meeting| Parès Gabriel

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TSV Medipix3/RX results – 2012‐2014

Electrical Tests

P01-Résistance cumulée Chaine de 2 TSV (VSS)

0

10

20

30

40

50

60

70

80

90

100

5.20E-01 5.40E-01 5.60E-01 5.80E-01 6.00E-01 6.20E-01 6.40E-01

Ohms

% Test RDL

Test Final

2 TSV chain resistance

Contact UBM TSV:

Technology

TSV 60µm x120µm

Back side UBM

Thin wafer debonded on tape

Medipix wafer after front side UBM

Accoustic image of the bonding

interface

RDL Cu 7 µm

Functionnal tests on ASICS

TSV Last for Hybrid Pixel Detectors: Application to Particle Physics and Imaging ExperimentsD. Henry(1), J. Alozy(2), A. Berthelot(1), R. Cuchet(1), C. Chantre(1), M. Campbell(2) ECTC 2013

5 lots run at LETI

EXAMPLE 2 = PIXEL SENSOR


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Die to die, Die to wafer, Die to substrate, multi dies heterogeneous stacking

Die size : 0.5x0.5 to 15x15 mm Die thickness : 50 to 725 µm* (* size/thickness not independent)

Wafer size : 200 & 300 mm Wafer thickness : 100 to 725 µm

Solder bumps interconnect : Cu stud / SnAg 305 solder on UBM (TiNiAu) or Cu/TiAu

Minimum pitch : 40 µm Solder pillar diameter : 20-80 µm

stand off : 10-60 µm

Underfilling : Capillary

Chip stacking illustration

solder bumps

SET FC 300

Datacon

EVG 560

Die 35 µm

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Yield FC daisy chain

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µbump Cu/SnAgD=25 µm

Bump Cu/SnAgD= 250 µm

OPEN 3D™ TECHNOLOGICAL OFFER FLIP-CHIP STACKING


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DIE-TO-WAFER STACKING WITH ΜBUMPS/UBM

50%

55%

60%

65%

70%

75%

80%

85%

90%

95%

100%

0 200 400 600 800 1000 1200

Yield vs Nb of µbumps

y = 0.1657xR² = 0.9977

0

20

40

60

80

100

120

140

160

180

200

0 200 400 600 800 1000 1200

Daisy chain Resistance (Ω) = f(nb of µbumps)

Wafer yield = 94%


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Design & Layout & DRC

LETI3D Technology implementation

TSV

Interconnections

Components stacking

Metalization

3D Electrical Tests

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CMP MPW wafer service

Dicing & Packaging

Wafer reception at LETI

3D modules identification order form

3D WORK FLOW WITH CMP

Wafer fabrication in foundry


Merci de votre attention

3D TECHNOLOGIES WAFER SERVICES AT LETI FOR ...LETI CONFIDENTIAL CMP annual meeting| Parès Gabriel |...

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