3D IC The New Edge of design

Subhash ChandraStudent Member, IEEE

BIT MuzaffarnagarU.P, India

csubhash07@gmail.com

Abstract- The unprecedented growth of the Information technology firm is demanding Very Large Scale (VLSI) circuit with increasing functionality and performance at the min. cost and power dissipation. VLSI circuits are aggressively scaled to meet this demand, which in turn has some serious problem for the semiconductorfirm. Additionally heterogeneous integration of different technologies increasingly desirable, for which planer (2-D) IC`s may not be suitable. 3-D ICs are an attractive chip architecture that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip (SoC). The multi-layer chip industry opens up a whole new world of design. With the Introduction of 3-D ICs, the world of chips may never look the same again

Keywords: SoC, VLSI, 2D IC, Heat energy

I.INTRODUCTION

There is a saying in real estate; when land get expensive, multi-storied buildings are the alternative solution. We have a similar situation in the chip industry. For the past thirty years, chip designers have considered whether building integrated circuits multiple layers might create cheaper, more powerful chips. Performance of deep-sub micrometer very large scale integrated (VLSI)[1] circuits is being increasingly dominated by the interconnects due to increasing wire pitch and increasing die size. Additionally, heterogeneous integration[2] of different technologies on one single chip is becoming increasingly desirable, for which planar (2-D) ICs[3] may not be suitable. The three dimensional (3-D) chip design strategy exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize system on a chip (SoC)[4] design. By simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs)[5], significant improvement in performance and reduction in wire-limited chip area can be achieved.

In the 3-Ddesign architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.What is 3D-IC?A chip in three-dimensional integrated circuit (3D-IC) technology iscomposed of two or more layers of active electronic components, integrated both vertically and horizontally.

II.MOTIVATION FOR 3-D IC`s

Continuous scaling of VLSI circuits is reducing gate delays butrapidly increasing interconnect delays. A significant fraction of the total powerconsumption can be due to the wiring network used for clock distribution, whichis usually realized using long global wires.Furthermore, increasing drive for the integration of disparate signals(digital, analog, RF) and technologies (SOI, SiGe, GaAs, and so on) isintroducing various SoC design concepts, for which existing planner (2-D) ICdesign may not be suitable.INTERCONNECT LIMITED VLSI PERFORMANCEIn single Si layer (2-D) ICs, chip size is continuously increasing despitereductions in feature size made possible by advances in IC technology such aslithography and etching. This is due to the ever growing demand for functionalityand highperformance, which causes increased complexity of chip design,requiring more and more transistors to be closely packed and connected. Smallfeature sizes have dramatically improved device performance. The impact of thisminiaturization on the performance of interconnect wire, however, has been lesspositive. Smaller wire cross sections, smaller wire pitch, and longer line totraverse larger chips have increase the resistance and capacitance of these lines,resulting in a significant increase in signal propagation (RC) delay. Asinterconnect scaling continues, RC delay is increasingly becoming the dominantfactor determining the performance of advanced IC’s.PHYSICAL LIMITATIONS OF Cu INTERCONNECTS

At 250 nm technology node, Cu with low-k dielectric was introduced toalleviate the adverse effect of increasing interconnect delay.However,below130nm technology node, substantial interconnect delays would result in spite ofintroducing these new materials, which in turn will severely limit the chipperformance. Further reduction in interconnect delay is not possible.This problem is especially acute for global interconnects[6], which compriseabout 10% of total wiring in current architectures. Therefore, it is apparent thatmaterial limitations will ultimately limit the performance improvement astechnology scales. Also, the problem of long lossylines[7] cannot be fixed bysimply widening the metal lines and by using thicker interlayer dielectric, sincethis will leas to an increase in the number of metal layers. This will result in anincrease in complexity, reliability and cost.

III. 3D ARCHITECTURE

Three-dimensional integration to create multilayer Si ICs[8] is a concept that can significantly improve interconnect performance ,increase transistor packingdensity, and reduce chip area and power dissipation. Additionally 3D ICs can be very effective large scale on chip integration of different systems. In 3D design architecture, and entire(2D) chips is divided into a number of blocks is placed on separate layer of Si that arestacked on top of each other. Each Si layer in the 3D structure can have multiple layer of

interconnects(VILICs) and common global interconnects.

IV.CHALLENGES FOR 3-D INTEGRATION

A) THERMAL ISSUES IN 3-D ICs An extremely important issue in 3-D ICs is heat dissipation. Thermal effect s are already known to significantly impact interconnected/device reliability and performance in high-performance 2-D ICs. The problem isexpected to be exacerbated by the reduction in chip size, assuming that samepower generated in a 2-D chip will now be generated in a smaller 3-D chip,resulting in a sharp increase in the power and density Analysis of thermalproblems in 3-D circuits is therefore necessary to comprehend the limitations ofthis technology and also to evaluate the thermal robustness of different 3-Dtechnology and design options.It is well known that most of the heat energy[9] in integrated circuits arisesdue to transistor switching. This heat energy is typically conducted through thesilicon substrate to the package and then to the ambient by a heat sink .Withmulti layer device designs, devices in the upper layer will also generate asignificant fraction of the heat .Furthermore, all the active layers will beinsulated from each other by layers of dielectrics[10] (LTO, HSQ, polyamide, etc.)which typically have much lower thermal conductivity than Si .Hence ,the heatdissipationissue can become even more acute for 3-D ICs and can causedegradation in device performance ,and reduction in chip reliability due toincreased junction leakage, electro migration failures ,and by accelerating otherfailure mechanisms.

B) RELIABLITY ISSUES IN 3-D ICsThree dimensional IC s will possibly introduce some new reliabilityproblems. These reliability issues may arise due to the electro thermal andthermo mechanical effects between various active layers and the interfacesbetween the active layers, which can also influence existing IC reliability hazardssuch a electro migration and chip performance. Additionally, heterogeneousintegration of technologies using 3-d architecture will increase the need tounderstand mechanical and thermal behavior of new material of new materialinterfaces and thin film material thermal and mechanical properties.

V.AREA AND PERFORMANCE ESTIMATION OF 3D ICs

Now we present a methodology that can be used to provide an initialestimate of the area and performance of high speed logic circuits fabricated

usingmultiple silicon layer IC technology. The approach is based on the empiricalrelationship known as Rent’s Rule [11].Rent’s Rule:It correlates the number of signal input and output (I/O) pins T, to the number of gates N, in a random logic network and is given by the following expressions:T=kNP -------------(i)Here k & P denote the average number of fan out per gate and the degree of wiring complexity (with P=1 representing the most complex wiring network), respectively, and are empirically derived as constants for a given generation of ICs.ESTIMATING 2-D AND 3-D CHIP AREAIn integrated circuits that are wire-pitch limited in size, the area require by the wiring network is assumed to be much greater than the area required by the logic gates. For the purpose of minimizing silicon real estate and signal propagation delays, the wiring network is segmented into separate tiers that arephysically fabricated in multiple layers. An interconnect tier is categorized by factors such as metal line pitch andcross-section, maximum allowable signal delay and communication mode (suchas intra block, or inter block). A tier can have more than one layer of metalinterconnects if necessary, and each tier or layer is connected to the rest of thewiring network and the logic gates by vertical vias. The tier closest to the logicdevices (referred to as the local tier) is normally for short distance intra blockcommunications.Metal lines in this tier will normally be the shortest. They will alsonormally have the finest pitch. The tier furthest away from the device layer(referred to as global tier) is responsible for long distance across chip inter blockcommunications, clocking and power distribution. Since this tier is populated bythe longest of wires, the metal pitch is the largest to minimize signal propagationdelays. A typical modern IC interconnects architecture will define three wiringtiers: local, semi-global, and global. The semi-global tier is normallyresponsible for inter block communications across intermediate distances.

The area of the chip is determined by the total wiring requirement. Interms of gate pitch, the total area required by the interconnect wiring can be expressed asArequired=√Ac(PlocLtotal_loc+PsemiLtotal_semi+PglobLtotal_glob)/NWhere,Ac- Chip area;N- number of gates;Ploc- local pitch;Psemi- semi global pitch;Pglobal- global pitch;Ltotal_loc- total lengths of local interconnects;Ltotal_semi- total length of semi global interconnects;Ltotal_glob- total length of global interconnects;The total interconnects length for any tier can be found by integrating thewire-length distribution within the boundaries that define the tier. Hence iffollows thatLtotal_loc= X ∫ li (l) dlLtotal_semi=X ∫ li (l) dlLtotal_glob = X ∫ li (l) dlWhere X is a correction factor that converts the point –to – point interconnectlength to wiring net length (using a linear net model, X=4/(f.o. + 3)

VI.ADVANTAGES OF 3D ARCHITECTURE

The 3D architecture offers extra flexibility in system design, placementand routing. For instance, logic gates on a critical path can be placed very closeto each other using multiple active layers. This would result in a significantreduction in RC delay and can greatly enhance the performance of logicalcircuits. The 3D chip design technology can be exploited to build SoCs by placingcircuits with different voltage and performance requirements in differentlayers. The 3D integration can reduce the wiring ,thereby reducing thecapacitance, power dissipation and chip area and therefore improve chipperformance.

Additionally the digital and analog components in the mixed-signalsystems can be placed on different Si layers thereby achieving better noiseperformance due to lower electromagnetic interference between suchcircuits blocks. From an integration point of view, mixed-technology assimilation couldbe made less complex and more cost effective by fabricating suchtechnologies on separate substrates followed by physical bonding.

VII.APPLICATIONS

Portable electronic digital cameras, digital audio players, PDAs, smartcellular phones, and handheld gaming devices are among the fastest growingtechnology market for both business and consumers. To date, one of the largestconstraints to growth has been affordable storage, creating the marketingopportunity for ultra low cost internal and external memory. These applicationsshare characters beyond rapid market growth.Portable devices all require small form factors, battery efficiency,robustness, and reliability. Both the devices and consumable media are extremelyprice sensitive with high volumes coming only with the ability to hit low pricepoints. Device designers often trade application richness to meet tight costtargets. Existing mask ROM and NAND flash non volatiletechnology[12] forcedesigners and product planners to make the difficult choice between low cost orfield programmability and flexibility. Consumers value the convenience and easeof views of readily available low cost storage. The potential to dramaticallylower the cost of digital storage weapons many more markets than those listedabove. Manufacturers of memory driven devices can now reach price pointspreviously inaccessible and develop richer, easier to use products.

VIII.CONCLUSION

The 3 D memory will just the first of a new generation of dense,inexpensive chips that promise to make digital recording media both cheap andconvenient enough to replace the photographic film and audio tape. We canunderstand that 3-D ICs are an attractive chip architecture, that can alleviate theinterconnect related problems such as delay and power dissipation and can alsofacilitate integration of heterogeneous technologies in one chip. The multilayerchip building technology opens up a whole new world of design like a cityskyline transformed by skyscrapers, the world of chips may never look at thesame again.

REFERENCES[1] Neil H. E Weste, David Harris, “CMOS VLSI Design”[2]Daniel Lu, C. P. Wong “Materials for Advanced Packaging”, Page-5[3]Guo Qi Zhang “More than moore: Creating high value micro/nano electronic system”, page no-20, 1.2.6[4]Micharl j.Dimario,“system of system collabrarative formation” page no-170[5] Dissertation abstract international ,Stanford university 2003(VILICs)[6]Nadine Azémard, Johan Vounckx “Integrated circuit and system design: Power and timeing modeling”, page no-181[7] Gianluca setti, Riccardo ravatti “Proceeding of the IEEE workshop on Nonlinear dynamic of electronic system” , page no-283[8] Corl. Clarys, “ULSI process integration III: Proceeding of the international symposium” , Electrochemical Society, page no-202[9] Y. S. Touloukian, Thermophysical properties ofMatter, TPRC Data Series Vol. 1- 4[10] deborah D.L chung “Material for electronic packing”, page no-194[11] Rao R Tummala ,Eugened j Rumazewski, “Microelectronic packing handbook: Technologies drivers”, pages- (1-22), part 1-2[12] Giovanni campardo, David Novosel,“VLSI design of non-volatile memories” ,page no-xxiii