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Department of the Computer Sciences Student name: ID: Section: Q. 1a) : Determine wither the following sentences are True(T) or False(F) [ :5] Sentence T/ F 1 The Hamming error correcting code is used to detect and correct the hard failure error only. F 2 The most powerful feature in SDRAM is that its access is synchronized with an external clock. T 3 Rambus DRAM is bus addresses up to 320 SRAM chips and rated at 1.6Gbps F 4 SDRAM can only send data once per clock, while the DRAM can send double data per clock F 5 The CDRAM memory integrates small SRAM cache onto generic SRAM chip F 1b) Choose the correct Answer: 1. ………………. Is the time between presenting the address and getting the valid data a. Access time b. Memory cycle time c. Transfer rate d. None of the above 2. How many check bits are needed if the Hamming error correction code is used to detect single bit errors in a 16-bit data word? a. 4 b. 6 c. 5 d. 7 3. ……….. can send data twice per clock cycle a. DRAM b. SDRAM c. DDRSDRAM d. None of the above 4. In …………… bits stored as on/off switched a. RAM 1 10 Princess Noura Bint Abdulrahman University CS323-Computer Architecture Faculty of Computer and Information Sciences
Transcript of cs207d.yolasite.comcs207d.yolasite.com/resources/Q 3B ANSWER.docx · Web viewPrincess Noura Bint...
Department of the Computer Sciences
Student name:ID: Section:
Q. 1a) : Determine wither the following sentences are True(T) or False(F) [ :5]
Sentence T/F1 The Hamming error correcting code is used to detect and correct the hard
failure error only.F
2 The most powerful feature in SDRAM is that its access is synchronized with an external clock.
T
3 Rambus DRAM is bus addresses up to 320 SRAM chips and rated at 1.6Gbps F4 SDRAM can only send data once per clock, while the DRAM can send double
data per clockF
5 The CDRAM memory integrates small SRAM cache onto generic SRAM chip F1b) Choose the correct Answer:
1. ………………. Is the time between presenting the address and getting the valid data
a. Access timeb. Memory cycle timec. Transfer rated. None of the above
2. How many check bits are needed if the Hamming error correction code is used to detect single bit errors in a 16-bit data word?
a. 4b. 6c. 5d. 7
3. ……….. can send data twice per clock cyclea. DRAMb. SDRAMc. DDRSDRAMd. None of the above
4. In …………… bits stored as on/off switcheda. RAMb. DRAMc. SRAMd. EROM
5. In ……………… because CPU knows when data will be ready, so CPU does not have to wait, it can do something else
a. DRAMb. SDRAMc. DDRSDRAMd. None of the above
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Princess Noura Bint Abdulrahman University CS323-Computer Architecture Faculty of Computer and Information Sciences Q 3 A-duration: 20 min
Second Semester 1434/1435H
Department of the Computer Sciences
Student name:ID: Section:
Q.2a) What are the difference between DRAM and SRAM in terms of characteristics such as speed, size, and cost?
SRAM DRAM• Bits stored as on/off switches• No charges to leak• No refreshing needed when
powered• More complex construction• Larger per bit• More expensive• Does not need refresh circuits• Faster• Cache• Digital
— Uses flip-flops
• Bits stored as charge in capacitors
• Charges leak• Need refreshing even when
powered• Simpler construction• Smaller per bit• Less expensive• Need refresh circuits• Slower• Main memory• Essentially analogue
— Level of charge determines value
Q. 2b) Brifly define the seven RAID levels?Answer yourself
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Princess Noura Bint Abdulrahman University CS323-Computer Architecture Faculty of Computer and Information Sciences Q 3 A-duration: 20 min
Second Semester 1434/1435H
