39532 Instruction Set - University of Sydney

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Section 31. Instruction Set

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HIGHLIGHTS

This section of the manual contains the following major topics:

31.1 Introduction .................................................................................................................. 31-2

31.2 Data Memory Map ....................................................................................................... 31-3

31.3 Instruction Formats ...................................................................................................... 31-9

31.4 Special Function Registers as Source/Destination .................................................... 31-12

31.5 Fast Register Stack.................................................................................................... 31-13

31.6 Q Cycle Activity.......................................................................................................... 31-13

31.7 Instruction Descriptions ............................................................................................. 31-14

31.8 Design Tips .............................................................................................................. 31-136

31.9 Related Application Notes........................................................................................ 31-137

31.10 Revision History ....................................................................................................... 31-138

2000 Microchip Technology Inc. DS39532A-page 31-1

PIC18C Reference Manual

31.1 Introduction

The PIC18CXXX instruction set adds many enhancements to the previous PICmicro instructionsets, while maintaining an easy migration from these PICmicro instruction sets. Most instructionsare a single program memory word (16-bits), but to address customer requests, some newinstructions have been added that require two program memory locations. The Instruction SetSummary, shown in Table 31-1, lists the instructions recognized by the Microchip assembler(MPASM). Table 31-2 gives the instruction description conventions.

Each instruction is divided into an OPCODE that specifies the instruction type and one or moreoperands which further specify the operation of the instruction.

The instruction set is highly orthogonal and is grouped into four basic categories:

• Byte-oriented operations• Bit-oriented operations• Literal operations• Control operations

Most byte-oriented instructions have three operands:

1. The File Register (specified by the value of ’f’)

2. The destination of the result (specified by the value of ’d’)

3. The accessed memory (specified by the value of ’a’)

'f' represents a File Register Designator and 'd' represents a Destination Designator. The FileRegister Designator specifies which File Register is to be used by the instruction. The accessindicator ’a’ specifies if the BSR selects the bank or if the access bank is used.

The destination designator specifies where the result of the operation is to be placed. If 'd' is zero,the result is placed in the WREG Register. If 'd' is one, the result is placed in the File Registerspecified in the instruction.

All bit-oriented instructions have three operands:

1. The File Register (specified by the value of ’f’)

2. The bit in the File Register (specified by the value of ’b’)

3. The accessed memory (specified by the value of ’a’)

'b' represents a bit field designator that selects the number of the bit affected by the operation,while 'f' represents the number of the file in which the bit is located. The access indicator ’a’ spec-ifies if the BSR selects the bank or if the access bank is used.

The literal instructions may use some of the following operands:

• A literal value to be loaded into a File Register (specified by the value of ’k’)• The desired FSR Register to load the literal value into (specified by the value of ’f’)• No operand required (specified by the value of ’—’)

The control instructions may use some of the following operands:

• A program memory address (specified by the value of ’n’)• The mode of the CALL or RETURN instructions (specified by the value of ’s’)• The mode of the Table Read and Table Write instructions (specified by the value of

’m’)• No operand required (specified by the value of ’—’)

All instructions are a single word except for three double word instructions. These three instruc-tions were made double word instructions so that all the required information is available in these32 bits. In the second word, the 4-MSb’s, are ’1’s. If this second word is executed as an instruction(by itself), it will execute as a NOP.

All single word instructions are executed in a single instruction cycle, unless a conditional test istrue or the program counter is changed as a result of the instruction. In these cases, the executiontakes two instruction cycles with the additional instruction cycle(s) executed as a NOP.

The double word instructions (that do not modify the PC) execute in two instruction cycles.

One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the programcounter is changed as a result of an instruction, the instruction execution time is 2 µs. Two wordbranch instructions (if true) would take 3 µs.

DS39532A-page 31-2 2000 Microchip Technology Inc.

Section 31. Instruction SetIn

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31.2 Data Memory Map

The Data Memory Map has 16 banks of 256 bytes. The Instruction Set and architecture allowsoperations across all banks (such as MOVFF). A Segment of Bank 0 and a segment of Bank 15comprise the access bank. See Section 31.2.1 for description of the access bank.

Figure 31-1: The Data Memory Map and the Access Bank

31.2.1 Access Bank

The access bank is an architectural enhancement that is very useful for C compiler codeoptimization. The techniques used by the C compiler may also be useful for programs written inassembly.

This data memory region can be used for

• Intermediate computational values• Local variables of subroutine• Faster context saving/switching of variables• Common variables• Faster evaluation/control of SFRs (no banking)

The access bank is comprised of 2 segments: Segment 0 and Segment 1. Segment 0 is the RAMthat is mapped in Bank 0. Segment 1 is the SFRs that are mapped in Bank 15. Each Segmentcan be of different sizes. The sum of RAM mapped by Segment 0 and Segment 1 is 256 bytes.

When forced in the access bank (a = ’0’), the last address in Segment 0 is followed by the firstaddress in Segment 1. Segment 1 maps the Special Function Registers so that these registerscan be accessed without any software overhead. This is useful for testing status flags and mod-ifying control bits.

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory MapBSR<3:0>

= 0000b

= 0001b

= 1110b

= 1111b

00h

FFh

00h

FFh

Access Bank

When the instructions ’a’ bit = 0,The BSR is ignored and this Access Bank isused.The Segment 0 General Purpose RAM is fromBank 0.The Segment 1 Special Function Registers isfrom Bank 15.

When a = 1,the BSR is used to specify the RAMlocation that the instruction uses.

Bank nSegment 0

Segment 1

Segment 1

Segment 0

Device DependentSegment Boundary


Example 31-1 shows how registers are affected depending on the value of the access bit. Reg-ister MYREG has an 8-bit address. This address specifies the location in the specified bank toperform the operation. The specified bank is either the bank specified by the Bank Select Regis-ter (BSR) (when a = 1), or the access bank (when a = 0).

Example 31-1:Operation of Destination and Access Bits

;; The following symbols are defined in the Microchip supplied; device header file:;; For destination bit:; F = 1 ; Result is placed in File Register; W = 0 ; Result is placed in WREG Register;; For access bit:; B = 1 ; Register used specified by BSR Bank Register; A = 0 ; Register used is in Access Bank;; MYREG is a register with an 8-bit address value between 0h and FFh.; For this example we will assign MYREG to bank 5, though it could; be in any (or all) banks.;

MOVLB 5 ; BSR points to RAM bank 5;; Contents of; Addr(MYREG) in; MYREG access bank WREG

; Starting Value 0x7F 0x5A x;

DECF MYREG, F, B ; 0x7E --- ---DECF MYREG, F, A ; --- 0x59 ---

;DECF MYREG, W, B ; --- --- 0x7DDECF MYREG, W, A ; --- --- 0x58

Note: If the register is specified with the full 12-bit address, the assembler will automati-cally force the access bit to a ’0’ (when the address is in the access RAM area) or a’1’ (for all other addresses).



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The common assembler usage should be that all RAM and SFR addresses are 12-bit. Thismeans that the assembler can determine from the address of the register, whether the accessbit needs to be set or cleared. Example 31-2 shows this, as well as forcing the use of the accessbank.

Example 31-2:Code

;; The following symbols are defined in the Microchip supplied; device header file:;; For destination bit:; F = 1 ; Result is placed in File Register; W = 0 ; Result is placed in WREG Register;; For access bit:; B = 1 ; Register used specified by BSR Bank Register; A = 0 ; Register used is in Access Bank;; Register Name Address; Loop_CNTR 0x000; MYREG 0x524; SFR1 0xA9F;

MOVLB 5 ; BSR points to RAM bank 5; Addr 24; a-bit MYREG Loop_CNTR SFR1 WREG Bank0

; Starting Value --- 0x7F 0x7F 0x7F x 0xA9;

DECF Loop_CNTR, F ; 0 --- 0x7E --- --- ---DECF MYREG, F ; 1 0x7E --- --- --- ---DECF SFR1, F ; 0 --- --- 0x7E --- ---

;;

DECF Loop_CNTR, W ; 0 --- --- --- 0x7D ---DECF MYREG, W ; 1 --- --- --- 0x7D ---DECF SFR1, W ; 0 --- --- --- 0x7D ---

INCF MYREG, F, A ; 0 --- --- --- --- 0xAAINCF MYREG, W, A ; 0 --- --- --- 0x7F ---


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Table 31-1: PIC18CXXX Instruction Set Summary

Mnemonic,Operands

Description Cycles16-Bit Instruction Word Status

AffectedNotes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONSADDWFADDWFCANDWFCLRFCOMFCPFSEQCPFSGTCPFSLTDECFDECFSZDCFSNZINCFINCFSZINFSNZIORWFMOVFMOVFF

MOVWFMULWFNEGFRLCFRLNCFRRCFRRNCFSETFSUBFWB

SUBWFSUBWFB

SWAPFTSTFSZXORWF

f, d, af, d, af, d, af, af, d, af, af, af, af, d, af, d, af, d, af, d, af, d, af, d, af, d, af, d, afs, fd

f, af, af, af, d, af, d, af, d, af, d, af, af, d, a

f, d, af, d, a

f, d, af, af, d, a

Add WREG and fAdd WREG and Carry bit to fAND WREG with fClear fComplement fCompare f with WREG, skip =Compare f with WREG, skip >Compare f with WREG, skip <Decrement fDecrement f, Skip if 0Decrement f, Skip if Not 0Increment fIncrement f, Skip if 0Increment f, Skip if Not 0Inclusive OR WREG with fMove fMove fs (source) to 1st word

fd (destination) 2nd wordMove WREG to fMultiply WREG with fNegate fRotate Left f through CarryRotate Left f (No Carry)Rotate Right f through CarryRotate Right f (No Carry)Set fSubtract f from WREG withborrowSubtract WREG from fSubtract WREG from f withborrowSwap nibbles in fTest f, skip if 0Exclusive OR WREG with f

111111 (2 or 3)1 (2 or 3)1 (2 or 3)11 (2 or 3)1 (2 or 3)11 (2 or 3)1 (2 or 3)112

111111111

11

11 (2 or 3)1

001000100001011000010110011001100000001001000010001101000001010111001111011000000110001101000011010001100101

01010101

001101100001

01da00da01da101a11da001a010a000a01da11da11da10da11da10da00da00daffffffff111a001a110a01da01da00da00da100a01da

11da10da

10da011a10da

ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

ffffffff

ffffffffffff

ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

ffffffff

ffffffffffff

C, DC, Z, OV, NC, DC, Z, OV, NZ, NZZ, NNoneNoneNoneC, DC, Z, OV, NNoneNoneC, DC, Z, OV, NNoneNoneZ, NZ, NNone

NoneNoneC, DC, Z, OV, NC, Z, NZ, NC, Z, NZ, NNoneC, DC, Z, OV, N

C, DC, Z, OV, NC, DC, Z, OV, N

NoneNoneZ, N

1, 2, 31, 2, 31,2, 32, 31, 2, 34421, 2, 3, 41, 2, 3, 41, 21, 2, 3, 41, 2, 41, 21, 21, 22

2

1, 21, 21, 21, 21, 221, 2

1, 21, 2

1, 2, 42

BIT-ORIENTED FILE REGISTER OPERATIONSBCFBSFBTFSCBTFSSBTG

f, b, af, b, af, b, af, b, af, d, a

Bit Clear fBit Set fBit Test f, Skip if ClearBit Test f, Skip if SetBit Toggle f

111 (2 or 3)1 (2 or 3)1

10011000101110100111

bbbabbbabbbabbbabbba

ffffffffffffffffffff

ffffffffffffffffffff

NoneNoneNoneNoneNone

1, 21, 23, 43, 41, 2

Note 1: When a PORT Register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will bethat value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input andis driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 Register (and, where applicable, d = 1), the prescaler will be clearedif assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The sec-ond cycle is executed as a NOP.

4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP,unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that alprogram memory locations have a valid instruction.

5: If the table write starts the write cycle to internal program memory, the write continues until terminated.


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CONTROL OPERATIONSBCBNBNCBNNBNOVBNZBOVBRABZCALL

CLRWDTDAWGOTO

NOPNOPPOPPUSHRCALLRESETRETFIE

RETLWRETURNSLEEP

nnnnnnnnnn, s

——n

————n

s

ks—

Branch if CarryBranch if NegativeBranch if Not CarryBranch if Not NegativeBranch if Not OverflowBranch if Not ZeroBranch if OverflowBranch UnconditionallyBranch if ZeroCall subroutine 1st word

2nd wordClear Watchdog TimerDecimal Adjust WREGGo to address 1st word

2nd wordNo OperationNo OperationPop top of return stack (TOS)Push top of return stack (TOS)Relative CallSoftware device RESETReturn from interrupt enable

Return with literal in WREGReturn from SubroutineGo into standby mode

1 (2)1 (2)1 (2)1 (2)1 (2)1 (2)1 (2)21 (2)2

112

1111212

221

1110111011101110111011101110110111101110111100000000111011110000111100000000110100000000

000000000000

00100110001101110101000101000nnn0000110skkkk000000001111kkkk0000xxxx000000001nnn00000000

110000000000

nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnkkkkkkkk00000000kkkkkkkk0000xxxx00000000nnnn11110001

kkkk00010000

nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnkkkkkkkk01000111kkkkkkkk0000xxxx01100101nnnn1111000s

kkkk001s0011

NoneNoneNoneNoneNoneNoneNoneNoneNoneNone

TO, PDCNone

NoneNoneNoneNoneNoneAllGIE/GIEH,PEIE/GIELNoneNoneTO, PD

4

Table 31-1: PIC18CXXX Instruction Set Summary (Continued)

Mnemonic,Operands


AffectedNotes

MSb LSb







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LITERAL OPERATIONSADDLWANDLWIORLWLFSR

MOVLBMOVLWMULLWRETLWSUBLWXORLW

kkkf, k

kkkkkk

Add literal and WREGAND literal with WREGInclusive OR literal with WREGMove literal (12-bit) 1st word

to FSRx 2nd wordMove literal to BSR<3:0>Move literal to WREGMultiply literal with WREGReturn with literal in WREGSubtract WREG from literalExclusive OR literal with WREG

1112

111211

00000000000011101111000000000000000000000000

11111011100111100000000111101101110010001010

kkkkkkkkkkkk00ffkkkk0000kkkkkkkkkkkkkkkkkkkk

kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk

C, DC, Z, OV, NZ, NZ, NNone

NoneNoneNoneNoneC, DC, Z, OV, NZ, N

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONSTBLRD*TBLRD*+TBLRD*-TBLRD+*TBLWT*TBLWT*+TBLWT*-TBLWT+*

Table ReadTable Read with post-incrementTable Read with post-decrementTable Read with pre-incrementTable WriteTable Write with post-incrementTable Write with post-decrementTable Write with pre-increment

22222 (5)

2 (5)

2 (5)

2 (5)

00000000000000000000000000000000

00000000000000000000000000000000

00000000000000000000000000000000

10001001101010111100110111101111

NoneNoneNoneNoneNoneNoneNoneNone

Table 31-1: PIC18CXXX Instruction Set Summary (Continued)

Mnemonic,Operands


AffectedNotes

MSb LSb

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31.3 Instruction Formats

Figure 31-2 shows the three general formats that the instructions can have. As can be seen fromthe general format of the instructions, the opcode portion of the instruction word varies from 3-bitsto 6-bits of information. This is what allows the Enhanced Instruction Set to have 75 instructions.

All instruction examples use the following format to represent a hexadecimal number:

0xhh

where h signifies a hexadecimal digit.

To represent a binary number:

00000100b

where b is a binary string identifier.

Figure 31-2: General Format for Instructions

Note: Any unused opcode is Reserved. Use of any reserved opcode may cause unex-pected operation.

Byte-oriented File Register operations

15 10 9 8 7 0

d = 0 for result destination to be WREG Register

OPCODE d a f (FILE #)

d = 1 for result destination to be File Register (f)a = 0 to force Access Bank

Bit-oriented File Register operations

15 12 11 9 8 7 0

OPCODE b (BIT #) a f (FILE #)

b = 3-bit position of bit in File Register (f)

Literal operations

15 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Byte to Byte move operations (2-word)

15 12 11 0

OPCODE f (Source FILE #)

CALL, GOTO, and Branch operations

15 8 7 0

OPCODE n<7:0> (literal)

n = 20-bit immediate value

a = 1 for BSR to select bankf = 8-bit File Register address

a = 0 to force Access Banka = 1 for BSR to select bankf = 8-bit File Register address

15 12 11 0

1111 n<19:8> (literal)

15 12 11 0

1111 f (Destination FILE #)

f = 12-bit File Register address

Control operations

Example Instruction

ADDWF MYREG, W, B

MOVFF MYREG1, MYREG2

BSF MYREG, bit, B

MOVLW 0x7F

GOTO label


Table 31-2: Instruction Description Conventions

Field Description

a RAM access bita = 0: RAM location in access bank (BSR Register is ignored)a = 1: RAM bank is specified by BSR Register

bbb Bit address within an 8-bit File Register (0 to 7)

BSR Bank Select Register. Used to select the current RAM bank.

d Destination select bit;d = 0: store result in WREG,d = 1: store result in File Register f.

dest Destination either the WREG Register or the specified register file location

f 8-bit Register file address (0x00 to 0xFF)

fs 12-bit Register file address (0x000 to 0xFFF). This is the source address.

fd 12-bit Register file address (0x000 to 0xFFF). This is the destination address.

k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)

label Label name

mm The mode of the TBLPTR Register for the Table Read and Table Write instructionsOnly used with Table Read and Table Write instructions:

* No Change to Register (such as TBLPTR with Table reads and writes)

*+ Post-Increment Register (such as TBLPTR with Table reads and writes)

*- Post-Decrement Register (such as TBLPTR with Table reads and writes)

+* Pre-Increment Register (such as TBLPTR with Table reads and writes)

n The relative address (2’s complement number) for relative branch instructions, orthe direct address for Call/Branch and Return instructions

PRODH Product of Multiply high byte

PRODL Product of Multiply low byte

s Fast Call / Return mode select bit.s = 0: do not update into/from Shadow Registerss = 1: certain registers loaded into/from Shadow Registers

u Unused or Unchanged

WREG Working Register (accumulator)

x Don't care (0 or 1)The assembler will generate code with x = 0. It is the recommended form of use forcompatibility with all Microchip software tools.

TBLPTR 21-bit Table Pointer (points to a Program Memory location)

TABLAT 8-bit Table Latch

TOS Top of Stack

INDF Any one of the indirect addressing registers, such as INDF0, INDF1, or INDF2

FSR Any one of the file select register pairs, such as FSR0H:FSR0L, FSR1H:FSR1L, orFSR2H:FSR2L


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Table 31-3: Indirect Addressing Symbols

PC Program Counter

PCL Program Counter Low Byte

PCH Program Counter High Byte

PCLATH Program Counter High Byte Latch

PCLATU Program Counter Upper Byte Latch

GIE Global Interrupt Enable bit

WDT Watchdog Timer

TO Time-out bit

PD Power-down bit

C,DC,Z,OV,N

ALU status bits Carry, Digit Carry, Zero, Overflow, Negative

[ ] Optional

( ) Contents of

→ Assigned to

< > Register bit field

∈ In the set of

italics User defined term (font is courier)

Field Description

*FSRn Selects INDFn Register

*FSRn++ Selects POSTINCn Register*FSRn-- Selects POSTDECn Register

*(++FSRn) Selects PREINCn Register*(FSRn+W) Selects PLUSWn Register

Table 31-2: Instruction Description Conventions (Continued)

Field Description


31.4 Special Function Registers as Source/Destination

The Section 31. Instruction Set’s Orthogonal Instruction Set allows read and write of all File Reg-isters, including Special Function Registers. The user should be aware of some special situationswhich are explained in the following subsections.

31.4.1 STATUS Register as Destination

If an instruction writes to the STATUS Register, the Z, C, DC, OV, and N bits may be set or clearedas a result of the instruction and overwrite the original data bits. For example, executing CLRFSTATUS will clear Register STATUS, and then set the Z bit leaving 0000 0100b in the register.

31.4.2 Bit Manipulation

All bit manipulation instructions will first read the entire register, operate on the selected bit andthen write the result back to (read-modify-write (R-M-W)) the specified register. The user shouldkeep this in mind when operating on some Special Function Registers, such as the Port Pin Reg-ister.

31.4.3 PCL as Source or Destination

Read, write or read-modify-write (R-M-W) on PCL may have the following results:

Read PCL: PCL → destination ; Reading PCL causes the followingPCH → PCLATHPCU → PCLATU

Write PCL: 8-bit destination value → PCL ; Writing PCL causes the followingPCLATH → PCHPCLATU → PCU

Read-Modify-Write: PCL→ ALU operand ; R-M-W of PCL causes the followingPCH → PCLATHPCU → PCLATU

; PCL data is modified8-bit result → PCL ; result is written back to PCLPCLATH → PCHPCLATU → PCU

Where PCH = program counter high byte (not an addressable register),PCLATH = Program counter high holding latch,PCU = program counter upper byte (not an addressable register),PCLATU = Program counter upper holding latch,destination = Register file ’f ’.

Note: Status bits that are manipulated by the device (including the interrupt flag bits) areset or cleared in the Q1 cycle, so there is no issue with executing R-M-W instructionson registers that contain these bits.



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31.5 Fast Register Stack

At times it is desirable to be able to quickly access and return from a function. This function maybe called as a subroutine, or an interrupt routine of the device. To reduce the overhead foraccessing/returning from these functions, the architecture has the ability to save three key regis-ters in a one deep Register Stack. These registers are:

• WREG Register• BSR (Bank Select Register) Register• STATUS Register

The two events that cause these registers to be loaded onto the Fast Register Stack are:

• A fast call (CALL K, fast)(where the fast bit is set (’1’))• Any interrupt occurs

These Fast Stack Registers are not accessible for reading or writing. When doing the return fromthese subroutine, the values can be restored into their registers executing the fast return:

• RETFIE fast (where the fast bit is set (’1’))• RETURN fast (where the fast bit is set (’1’))

When s (fast) = ’0’, the Fast Register Stack is not used, when s (fast) = ’1’, the Fast RegisterStack is used.

31.6 Q Cycle Activity

Each instruction cycle (Tcy) is comprised of four Q clocks (also called Q cycles). These arereferred to as Q1, Q2, Q3, or Q4. The Q cycles provide the timing/designation for the Decode,Read, Process Data, Write etc., of each instruction cycle. The Figure 31-3 shows the relationshipof the Q cycles to the instruction cycle.

The four Q cycles that make up an instruction cycle (Tcy) can be generalized as:

Q1: Instruction Decode Cycle or forced No OperationQ2: Instruction Read Cycle or No OperationQ3: Process the DataQ4: Instruction Write Cycle or No Operation

Some actions occur on the edge between the end of one Q cycle and the start of the next Q cycle.An example would be a Q2-Q3 action. This action occurs on the clock edge between the end ofQ2 cycle and the beginning of the Q3 cycle.

The clock source for the Q cycle is normally the device oscillator clock (TOSC). But the clocksource is software selectable. So the Q cycle may be independent of the device oscillator cycle(TOSC).

In the full description of each instruction, the detailed Q cycle operation for the instruction will beshown.

Figure 31-3: Q Cycle Activity

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Tcy1 Tcy2 Tcy3

TOSC



31.7 Instruction Descriptions

ADDLW Add Literal to WREG

Syntax: [ label ] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (WREG) + k → WREG

Status Affected: C, DC, Z, OV, N

Encoding: 0000 1111 kkkk kkkk

Description: The eight bit literal ’k’ is added to the contents of the WREG and the resultis placed in the WREG.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Readliteral 'k'

Processdata

Write toWREG

Register

Example1 ADDLW 0x19 ; Add 19h to value in WREG

Before InstructionWREG = 0x18C, DC, Z, OV, N = x

After InstructionWREG = 0x31C = 0DC = 1Z = 0OV = 0N = 0

Example 2 ADDLW MYREG ; Add the value of the; address for MYREG Register; to WREG

Before InstructionWREG = 0x60

Address of MYREG † = 0x37† MYREG is a symbol for a data memory locationC, DC, Z, OV, N = x

After InstructionWREG = 0x97C = 0DC = 0Z = 0OV = 1N = 1



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Example 3 ADDLW HIGH (LU_TABLE) ; Add high byte of address; LU_TABLE to WREG


Address of LU_TABLE † = 0x9375† LU_TABLE is a label for an address in program memoryC, DC, Z, OV, N = x

After InstructionWREG = 0xA3C = 0DC = 0Z = 0OV = 0N = 1

Example 4 ADDLW PCL ; Add value of the address; of Program Counter Low; byte (PCL) to WREG


Address of PCL † = 0xFF8 (only low 8-bits are used)† PCL is the symbol for the Program Counter low byte locationC, DC, Z, OV, N = x

After InstructionWREG = 0xFAC = 0DC = 0Z = 0OV = 0N = 0

Example 5 ADDLW Offset ; Add the value of symbol; Offset to WREG

Before InstructionWREG = 0x10Offset = 0x02C, DC, Z, OV, N = x

After InstructionWREG = 0x12Offset = 0x02C = 0DC = 0Z = 0OV = 0N = 0



ADDWF Add WREG and f

Syntax: [ label ] ADDWF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (WREG) + (f) → destination


Encoding: 0010 01da ffff ffff

Description: Add the contents of the WREG Register to the contents of Register 'f'.

The ’d’ bit selects the destination for the operation.If 'd' is 1; the result is stored back in the File Register 'f'.If 'd' is 0; the result is stored in the WREG Register.

The ’a’ bit selects which bank is accessed for the operation.If ’a’ is 1; the bank specified by the BSR Register is used.If ’a’ is 0; the access bank is used.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode ReadRegister 'f'

Processdata

Write todestination

Example 1 ADDWF FSR0L, 1, 1 ; Add value in WREG to; value in the; FSR0H:FSR0L Register

Case 1: Before InstructionWREG = 0x17FSR0H:FSR0L = 0x2C2C, DC, Z, OV, N = x

After InstructionWREG = 0x17FSR0H:FSR0L = 0x2D9C = 0DC = 0Z = 0OV = 0N = 1

Case 2: Before InstructionWREG = 0x17FSR0H:FSR0L = 0x2FFC, DC, Z, OV, N = x

After InstructionWREG = 0x17FSR0H:FSR0L = 0x316C = 0DC = 0Z = 0OV = 0N = 0



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Example 2 ADDWF INDF0, 1, 1 ; Add value in WREG to; value in the register; pointed to (addressed); by the FSR0H:FSR0L; Register

Before InstructionWREG = 0x17FSR0H:FSR0L = 0x6C2Contents of Address (FSR0) = 0x20C, DC, Z, OV, N = x

After InstructionWREG = 0x17FSR0H:FSR0L = 0x6C2Contents of Address (FSR0) = 0x37C = 0DC = 0Z = 0OV = 0N = 0

Example 3 ADDWF INDF0, 1, 0 ; Add value in WREG to; value in the register; pointed to (addressed); by the FSR0H:FSR0L; Register

Before InstructionWREG = 0x17FSR0H:FSR0L = 0x0C2Contents of Address (FSR0) = 0x20C, DC, Z, OV, N = x

After InstructionWREG = 0x17FSR0H:FSR0L = 0x0C2Contents of Address (FSR0) = 0x37C = 0DC = 0Z = 0OV = 0N = 0



Example 4 ADDWF PCL, 1, 1 ; Add the value in WREG to; the current value in the; low byte of the program; counter (PCL)

Case 1: Before InstructionWREG = 0x10PCL = 0x37C, DC, Z, OV, N = x

After InstructionWREG = 0x10PCL = 0x47C = 0DC = 0Z = 0OV = 0N = 0

Case 2: Before InstructionWREG = 0x10PCL = 0xF7PCH = 0x08C, DC, Z, OV, N = x

After InstructionWREG = 0x10PCL = 0x07PCH = 0x08C = 1DC = 0Z = 0OV = 0N = 0



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Example 5 ADDWF MYREG, 1 ; Add the value in WREG to; the current value in; MYREG; (assembler determines; that MYREG requires; access bit to be set)

Case 1: Before InstructionBSR = 0x01WREG = 0x10MYREG = 0x37C, DC, Z, OV, N = x

After InstructionBSR = 0x01WREG = 0x10MYREG = 0x47C = 0DC = 0Z = 0OV = 0N = 0

; In Bank 1

; In Bank 1

Case 2: Before InstructionBSR = 0x01WREG = 0x10MYREG = 0xF7C, DC, Z, OV, N = x

After InstructionBSR = 0x01WREG = 0x10MYREG = 0x07C = 1DC = 0Z = 0OV = 0N = 0

; In Bank 1

; In Bank 1



ADDWFC Add WREG and Carry bit to f

Syntax: [ label ] ADDWF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (WREG) + (f) + (C) → destination



Description: Add the contents of the WREG Register and the Carry bit to the contents ofRegister 'f'.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 ADDWFC FSR0L, 0, 1 ; Add WREG, C bit, and FSR0L; value (Destination WREG)

Case 1: Before InstructionWREG = 0x17FSR0H:FSR0L = 0x9C2C = 0DC, Z, OV, N = x

After InstructionWREG = 0xD9FSR0H:FSR0L = 0x9C2C = 0DC = 0Z = 0OV = 0N = 1

Case 2: Before InstructionWREG = 0x17FSR0H:FSR0L = 0x7C2C = 1DC, Z, OV, N = x

After InstructionWREG = 0xDAFSR0H:FSR0L = 0x7C2C = 0DC = 0Z = 0OV = 0N = 1



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Example 2 ADDWFC INDF0, 1, 1 ; Add WREG and the Carry; bit to the value pointed; to by the FSR0H:FSR0L; (Destination: File; Register)

Before InstructionWREG = 0x17FSR0H:FSR0L = 0x0C2Contents of Address (FSR0H:FSR0L) = 0x20C = 0DC, Z, OV, N = x

After InstructionWREG = 0x17FSR0H:FSR0L = 0x0C2Contents of Address (FSR0H:FSR0L) = 0x37C = 0DC = 0Z = 0OV = 0N = 0

Example 3 ADDWFC PCL, 1, 1 ; Add WREG and the Carry; bit to the PCL Register

Case 1: Before InstructionWREG = 0x10PCL = 0x38C = 0DC, Z, OV, N = x

After InstructionWREG = 0x10PCL = 0x48C = 0DC = 0Z = 0OV = 0N = 0

Case 2: Before InstructionWREG = 0x10PCL = 0xF8PCH = 0x08C = 0DC, Z, OV, N = x

After InstructionWREG = 0x10PCL = 0x08PCH = 0x08C = 1DC = 0Z = 0OV = 0N = 0



ANDLW AND Literal with WREG

Syntax: [ label ] ANDLW k


Operation: (WREG).AND. (k) → W

Status Affected: Z, N


Description: The contents of WREG Register are AND’d with the eight bit literal 'k'. Theresult is placed in the WREG Register.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write toWREG

Register

Example 1 ANDLW 0x5F ; And constant to WREG

Before InstructionWREG = 0xA3Z, N = x

After InstructionWREG = 0x03Z = 0N = 0

; 0101 1111 (0x5F); 1010 0011 (0xA3);---------- ------; 0000 0011 (0x03)

Example 2 ANDLW MYREG ; And address of MYREG; to WREG

Before InstructionWREG = 0xA3

Address of MYREG † = 0x37Z, N = x† MYREG is a symbol for a

data memory locationAfter Instruction

WREG = 0x23Z = 0N = 0

; 0011 0111 (0x37); 1010 0011 (0xA3);---------- ------; 0010 0011 (0x23)



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Example 3 ANDLW HIGH(LU_TABLE)

; And the high byte of; address LU_TABLE; with WREG


Address of LU_TABLE †

= 0x9375Z, N = x† LU_TABLE is a label for an

address in program memoryAfter Instruction

WREG = 0x83Z = 0N = 1

; 1010 0011 (0xA3)

; 1001 0011 (0x93);---------- ------

; 1000 0011 (0x83)

Example 4 ANDLW LOW (LU_TABLE); And the low byte of; address LU_TABLE; with WREG



= 0x9375Z, N = x† LU_TABLE is a label for an

address in program memoryAfter Instruction

WREG = 0x21Z = 0N = 0

; 1010 0011 (0xA3)

; 0111 0101 (0x75);---------- ------

; 0010 0001 (0x21)



ANDWF AND WREG with f

Syntax: [ label ] ANDWF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (WREG).AND. (f) → destination



Description: The contents of the WREG Register are AND’d with the contents of Regis-ter 'f'.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 ANDWF REG1, 1, 1 ; And WREG with REG1

Before InstructionWREG = 0x17REG1 = 0xC2Z, N = x

After InstructionWREG = 0x17REG1 = 0x02Z = 0N = 0

; 0001 0111 (0x17); 1100 0010 (0xC2);---------- ------

; 0000 0010 (0x02)

Example 2 ANDWF REG1, 0, 1 ; And WREG with REG1; (destination WREG)

Before InstructionWREG = 0x17REG1 = 0xC2Z, N = x

After InstructionWREG = 0x02REG1 = 0xC2Z = 0N = 0

; 0001 0111 (0x17); 1100 0010 (0xC2);---------- ------

; 0000 0010 (0x02)



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Example 3 ANDWF INDF0, 1, 1 ; And WREG with value pointed; by FSR0H:FSR0L (FSR0)

Case 1: Before InstructionWREG = 0x17FSR0H:FSR0L

= 0xFC2Contents of Address

(FSR0) = 0x5AZ, N = x

After InstructionWREG = 0x17FSR0H:FSR0L

= 0xFC2Contents of Address

(FSR0) = 0x12Z = 0N = 0

; 0001 0111 (0x17)

; 0101 1010 (0x5A);---------- ------

; 0001 0010 (0x12)

Case 2: Before InstructionWREG = 0x00FSR0H:FSR0L

= 0x4C2Contents of Address

(FSR0) = 0x5AZ, N = x

After InstructionWREG = 0x00FSR0H:FSR0L

= 0x4C2Contents of Address

(FSR0) = 0x00Z = 1N = 0

; 0000 0000 (0x00)

; 0101 1010 (0x5A);---------- ------

; 0000 0000 (0x00)



BC Branch if Carry

Syntax: [ label ] BC n

Operands: -128 ≤ f ≤ 127

Operation: If carry bit is ’1’(PC + 2) + 2n → PC

Status Affected: None

Encoding: 1110 0010 nnnn nnnn

Description: If the Carry bit is ’1’, then the program will branch.

The 2’s complement number ’2n’ (the offset) is added to the PC. Since thePC will have incremented to fetch the next instruction, the new address willbe (PC+2)+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1 (2)

Q Cycle Activity:If Branch

Q1 Q2 Q3 Q4

Decode Readliteral 'n'

Processdata

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

If No Branch

Q1 Q2 Q3 Q4


Processdata

Nooperation

Example 1 HERENOT_C

C_CODE

BC••GOTO••

C_CODE

MORE_CODE

;; If C bit is not set; execute this code.;; else if C bit is set; this code will execute

Case 1: Before InstructionPC = address HEREC = 0

After InstructionPC = address NOT_C


After InstructionPC = address C_CODE



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Example 2 HERENO_CPLUS0PLUS1PLUS2PLUS3PLUS4PLUS5PLUS6

BCGOTO•••••••

$ + OFFSETPROCESS_CODE

; If carry bit is set,; branch to HERE+OFFSET


After InstructionPC = address NO_C


After InstructionPC = address HERE + OFFSET

Example 3 MIN6MIN5MIN4MIN3MIN2MIN1MIN0HERENO_C

•••••••BCGOTO

$ - OFFSETPROCESS_CODE

; If carry bit is set,; branch to HERE-OFFSET


After InstructionPC = address NO_C


After InstructionPC = address HERE - OFFSET

Note: Assembler will convert the specified address label into the offset to be used.


BCF Bit Clear f

Syntax: [ label ] BCF f, b, a

Operands: 0 ≤ f ≤ 2550 ≤ b ≤ 7a ∈ [0,1]

Operation: 0 → f


Encoding: 1001 bbba ffff ffff

Description: Bit 'b' in Register 'f' of the specified bank is cleared.


Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

WriteRegister 'f'

Example 1 BCF MYREG, 7, 1 ; Clear bit 7 in Register; MYREG

Before InstructionMYREG = 0xC7

After Instruction

MYREG = 0x47

; 1100 0111

; 0100 0111


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Example 2 BCF INDF0, 3, 0 ; Clear bit 7 in the register; pointed to by the FSR0; (FSR0H:FSR0L) Register

Before InstructionFSR0 = 0x3C2Contents of Address

(FSR0) = 0x2FAfter Instruction

FSR0 = 0x3C2Contents of Address

(FSR0) = 0x27

; 0010 1111

; 0010 0111



BN Branch if Negative

Syntax: [ label ] BN n

Operands: -128 ≤ f ≤ 127

Operation: If negative bit is ’1’(PC + 2) + 2n → PC



Description: If the Negative bit is ’1’, then the program will branch.


Words: 1

Cycles: 1 (2)


Q1 Q2 Q3 Q4


Processdata

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

If No Branch

Q1 Q2 Q3 Q4


Processdata

Nooperation

Example 1 HERENOT_N

N_CODE

BN••GOTO••

N_CODE

MORE_CODE

; If N bit is not set; execute this code.;;; else if N bit is set; this code will execute

Case 1: Before InstructionPC = address HEREN = 0

After InstructionPC = address NOT_N


After InstructionPC = address N_CODE



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Example 2 HERENOT_NPLUS0PLUS1PLUS2PLUS3PLUS4PLUS5PLUS6

BNGOTO•••••••


; If negative bit is set,; branch to HERE + OFFSET


After InstructionPC = address NOT_N



Example 3 MIN6MIN5MIN4MIN3MIN2MIN1MIN0HERENO_N

•••••••BNGOTO


; If negative bit is set,; branch to HERE - OFFSET


After InstructionPC = address NO_N






BNC Branch if Not Carry

Syntax: [ label ] BNC n

Operands: -128 ≤ f ≤ 127

Operation: If carry bit is ’0’(PC + 2) + 2n → PC



Description: If the Carry bit is ’0’, then the program will branch.


Words: 1

Cycles: 1 (2)


Q1 Q2 Q3 Q4


Processdata

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

If No Branch

Q1 Q2 Q3 Q4


Processdata

Nooperation

Example 1 HERECARRY

NC_CODE

BNC••GOTO••

NC_CODE

MORE_CODE

; If C bit is set; execute this code.;;; else if C bit is clear; this code will execute


After InstructionPC = address NC_CODE


After InstructionPC = address CARRY



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Example 2 HERECARRYPLUS0PLUS1PLUS2PLUS3PLUS4PLUS5PLUS6

BNCGOTO•••••••


; If carry bit is clear,; branch to HERE + OFFSET





Example 3 MIN6MIN5MIN4MIN3MIN2MIN1MIN0HERECARRY

•••••••BNCGOTO


; If carry bit is clear,; branch to HERE - OFFSET








BNN Branch if Not Negative

Syntax: [ label ] BNN n

Operands: -128 ≤ f ≤ 127

Operation: If negative bit is ’0’(PC + 2) + 2n → PC



Description: If the Negative bit is ’0’, then the program will branch.


Words: 1

Cycles: 1 (2)


Q1 Q2 Q3 Q4


Processdata

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

If No Branch

Q1 Q2 Q3 Q4


Processdata

Nooperation

Example 1 HERENEG

POS_CODE

BNN••GOTO••

POS_CODE

MORE_CODE

; If N bit is set; execute this code.;;; else if N bit is clear; this code will execute


After InstructionPC = address POS_CODE


After InstructionPC = address NEG



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Example 2 HERENEGPLUS0PLUS1PLUS2PLUS3PLUS4PLUS5PLUS6

BNNGOTO•••••••


; If negative bit is clear,; branch to HERE + OFFSET





Example 3 MIN6MIN5MIN4MIN3MIN2MIN1MIN0HERENEG

•••••••BNNGOTO


; If negative bit is clear,; branch to HERE - OFFSET








BNOV Branch if Not Overflow

Syntax: [ label ] BNOV n

Operands: -128 ≤ f ≤ 127

Operation: If overflow bit is ’0’(PC + 2) + 2n → PC



Description: If the Overflow bit is ’0’, then the program will branch.


Words: 1

Cycles: 1 (2)


Q1 Q2 Q3 Q4


Processdata

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

If No Branch

Q1 Q2 Q3 Q4


Processdata

Nooperation

Example 1 HEREOVFL

NOV_CODE

BNOV••GOTO••

NOV_CODE

MORE_CODE

; If overflow bit is set; execute this code.;;; else if overflow bit is; clear this code will; execute

Case 1: Before InstructionPC = address HEREOV = 0

After InstructionPC = address NOV_CODE


After InstructionPC = address OVFL



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Example 2 HEREOVFLPLUS0PLUS1PLUS2PLUS3PLUS4PLUS5PLUS6

BNOVGOTO•••••••


; If overflow bit is clear,; branch to HERE + OFFSET





Example 3 MIN6MIN5MIN4MIN3MIN2MIN1MIN0HEREOVFL

•••••••BNOVGOTO


; If overflow bit is clear,; branch to HERE - OFFSET








BNZ Branch if Not Zero

Syntax: [ label ] BNZ n

Operands: -128 ≤ f ≤ 127

Operation: If zero bit is ’0’(PC + 2) + 2n → PC



Description: If the Zero bit is ’0’, then the program will branch.


Words: 1

Cycles: 1 (2)


Q1 Q2 Q3 Q4


Processdata

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

If No Branch

Q1 Q2 Q3 Q4


Processdata

Nooperation

Example 1 HEREZERO

Z_CODE

BNZ••GOTO••

Z_CODE

MORE_CODE

; If Z bit is set; execute this code.;;; else if Z bit is clear; this code will execute

Case 1: Before InstructionPC = address HEREZ = 0

After InstructionPC = address Z_CODE


After InstructionPC = address ZERO



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Example 2 HEREZEROPLUS0PLUS1PLUS2PLUS3PLUS4PLUS5PLUS6

BNZGOTO•••••••


; If zero bit is clear,; branch to HERE + OFFSET





Example 3 MIN6MIN5MIN4MIN3MIN2MIN1MIN0HEREZERO

•••••••BNZGOTO


; If zero bit is clear,; branch to HERE - OFFSET








BOV Branch if Overflow

Syntax: [ label ] BOV n

Operands: -128 ≤ f ≤ 127

Operation: If overflow bit is ’1’(PC + 2) + 2n → PC



Description: If the Overflow bit is ’1’, then the program will branch.


Words: 1

Cycles: 1 (2)


Q1 Q2 Q3 Q4


Processdata

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

If No Branch

Q1 Q2 Q3 Q4


Processdata

Nooperation

Example 1 HEREOVFL

OV_CODE

BOV••GOTO••

OV_CODE

MORE_CODE

; If OV bit is clear; execute this code.;;; else if OV bit is set; this code will execute




After InstructionPC = address OV_CODE



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Example 2 HEREOVFLPLUS0PLUS1PLUS2PLUS3PLUS4PLUS5PLUS6

BOVGOTO•••••••


; If overflow bit is set,; branch to HERE + OFFSET





Example 3 MIN6MIN5MIN4MIN3MIN2MIN1MIN0HEREOVFL

•••••••BOVGOTO


; If OV bit is set,; branch to HERE - OFFSET







BRA Branch Unconditional

Syntax: [ label ] BRA n

Operands: -1024 ≤ f ≤ 1023

Operation: (PC + 2) + 2n → PC


Encoding: 1101 0nnn nnnn nnnn

Description: The 2’s complement number ’2n’ (the offset) is added to the PC. Since thePC will have incremented to fetch the next instruction, the new address willbe (PC+2)+2n. This instruction is a two-cycle instruction.

Words: 1

Cycles: 2


Q1 Q2 Q3 Q4


Processdata

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

If No Branch

Q1 Q2 Q3 Q4


Processdata

Nooperation

Example 1 HERE

THERE

BRA••••

THERE ; Branch to a program memory; location (THERE); this location must be; < 1023 locations forward

Before InstructionPC = address HERE

After InstructionPC = address THERE

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Example 2 THERE

HERE

••••BRA THERE

; Branch to a program memory; location (THERE); this location must be; < 1024 locations backward


After InstructionPC = address THERE

Example 3 HERE BRA $ ; Branch to program memory; location (HERE).; Infinite Loop


After InstructionPC = address HERE

BSF Bit Set f

Syntax: [ label ] BSF f, b, a

Operands: 0 ≤ f ≤ 2550 ≤ b ≤ 7a ∈ [0,1]

Operation: 1 → f



Description: Bit 'b' in Register 'f' is set.


Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

WriteRegister 'f'

Example 1 BSF FLAG_REG, 7 ; Set bit 7 in Register; FLAG_REG; (assembler determines; that FLAG_REG requires; access bit to be set)

Before InstructionFLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

; 0000 1010

; 1000 1010

Example 2 BSF INDF0, 3, 0 ; Set bit 3 in the register; pointed to by the FSR0; (FSR0H:FSR0L) Register

Before InstructionWREG = 0x17FSR0 = 0x0C2Contents of Address

(FSR0)= 0x20After Instruction

WREG = 0x17FSR0 = 0x0C2Contents of Address

(FSR0) = 0x28

; 0010 0000

; 0010 1000

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BTFSC Bit Test File, Skip if Clear

Syntax: [ label ] BTFSC f, b, a

Operands: 0 ≤ f ≤ 2550 ≤ b ≤ 7a ∈ [0,1]

Operation: Skip if (f) = 0



Description: If bit 'b' in Register 'f' is '0' then the next instruction is skipped.If bit 'b' is '0' then the next instruction (fetched during the current instructionexecution) is discarded, and a NOP is executed instead, making this a2-cycle instruction.


Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Nooperation

If skip (2nd cycle):

Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

If skip and followed by a two word instruction:

Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Example 1 HEREFALSETRUE

BTFSCGOTO•••

FLAG, 4, 1PROCESS_CODE

; Test bit 4 of Register; FLAG, and skip if; clear

Case 1: Before InstructionPC = address HEREFLAG = xxx0 xxxx

After InstructionSince FLAG<4> = 0PC = address TRUE


After InstructionSince FLAG<4> = 1PC = address FALSE

BTFSS Bit Test File, Skip if Set

Syntax: [ label ] BTFSS f, b, a

Operands: 0 ≤ f ≤ 2550 ≤ b < 7a ∈ [0,1]

Operation: Skip if (f) = 1



Description: If bit 'b' in Register 'f' is '1' then the next instruction is skipped.If bit 'b' is '1', then the next instruction (fetched during the current instructionexecution) is discarded and a NOP is executed instead, making this a2-cycle instruction.


Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Example 1 HEREFALSETRUE

BTFSSGOTO•••

FLAG, 4, 0PROCESS_CODE

; Test bit 4 of Register; FLAG, and skip if set


After InstructionSince FLAG<4> = 0PC = address FALSE


After InstructionSince FLAG<4> = 1PC = address TRUE

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BTG Bit Toggle f

Syntax: [ label ] BTG f, b, a

Operands: 0 ≤ f ≤ 2550 ≤ b ≤ 7a ∈ [0,1]

Operation: (f) → f



Description: Bit 'b' in Register 'f' is toggled.


Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

WriteRegister 'f'

Example 1 BTG LATC, 7, 1 ; Toggle the value of bit 7; in the LATC Register

Before InstructionLATC = 0x0A

After Instruction

LATC = 0x8A

; 0000 1010

; 1000 1010

Example 2 BTG INDF0, 3, 1 ; Toggle the value of bit 3; in the register pointed to; by the value in the FSR0; (FSR0H:FSR0L) Register

Before InstructionFSR0 = 0xAC2Contents of Address

(FSR0)= 0x20After Instruction

FSR0 = 0xAC2Contents of Address

(FSR0)= 0x28

; 0010 0000

; 0010 1000


BZ Branch if Zero

Syntax: [ label ] BZ n

Operands: -128 ≤ f ≤ 127

Operation: If zero bit is ’1’(PC + 2) + 2n → PC



Description: If the Zero bit is ’1’, then the program will branch.

The 2’s complement number ’2n’ (the offset) is added to the PC. Since thePC will have incremented to fetch the next instruction, the new address willbe PC+2+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1 (2)


Q1 Q2 Q3 Q4


Processdata

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

If No Branch

Q1 Q2 Q3 Q4


Processdata

Nooperation

Example 1 HEREZERO

Z_CODE

BZ••GOTO••

Z_CODE

MORE_CODE

; If zero bit is clear; execute this code.;;; else if zero bit is set; this code will execute




After InstructionPC = address Z_CODE



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Example 2 HERENZEROPLUS0PLUS1PLUS2PLUS3PLUS4PLUS5PLUS6

BZGOTO•••••••


; If zero bit is set,; branch to HERE + OFFSET


After InstructionPC = address NZERO



Example 3 MIN6MIN5MIN4MIN3MIN2MIN1MIN0HERENZERO

•••••••BZGOTO


; If zero bit is set,; branch to HERE - OFFSET


After InstructionPC = address NZERO





CALL Call Subroutine

Syntax: [ label ] CALL k, s

Operands: 0 ≤ k ≤ 1048575s ∈ [0,1]

Operation: (PC)+ 4 → TOS,k → PC<20:1>,0 → PC<0>,if s = 1

(WREG) → WREGS,(STATUS) → STATUSS,(BSR) → BSRS


Encoding:

1st word (k<7:0>)2nd word (k<19:8>)

11101111

110sk19kkk

k7kkkkkkk

kkkk0kkkk8

Description: Subroutine call of entire 2M byte memory range. First, return address (PC+4) is pushed onto the return stack (20-bits wide).

If ’s’ = 1, the WREG, STATUS and BSR Registers are also pushed intotheir respective Shadow Registers, WREGS, STATUSS and BSRS.

If 's' = 0, no update occurs.

Then the 20-bit value ’k’ is loaded into PC<20:1>. CALL is a two-cycleinstruction.

Words: 2

Cycles: 2

Q Cycle Activity:

1st cycle:

Q1 Q2 Q3 Q4


Processdata

Nooperation

2nd cycle:

Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


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Example 1 HERE CALL THERE, 1 ; Call subroutine THERE.; This is a fast call so; the BSR, WREG, and STATUS; Registers are forced onto; the Fast Register Stack

Before InstructionPC = Address HERE

After InstructionTOS = Address HERE+4PC = Address THEREWREGS = WREGBSRS = BSRSTATUSS = STATUS

Example 2 HERE CALL THERE, 0 ; Call subroutine THERE.; This is NOT a fast call

Before InstructionPC = Address HEREWREGS = 0x45BSRS = 0x29STATUSS = 0x01

After InstructionTOS = Address HERE+4PC = Address THEREWREGS = 0x45 (unchanged)BSRS = 0x29 (unchanged)STATUSS = 0x01 (unchanged)



CLRF Clear f

Syntax: [ label ] CLRF f, a

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: 00h → f1 → Z

Status Affected: Z

Encoding: 0110 101a ffff ffff

Description: The contents of Register 'f' are cleared and the Z bit is set.


Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

WriteRegister 'f'

Example 1 CLRF FLAG_REG, 1 ; Clear Register FLAG_REG

Before InstructionFLAG_REG = 0x5AZ = x

After InstructionFLAG_REG = 0x00Z = 1

Example 2 CLRF INDF0, 1 ; Clear the register pointed; to by the FSR0; (FSR0H:FSR0L) Register


(FSR0) = 0xAAZ = x

After InstructionFSR0 = 0x0C2Contents of Address

(FSR0) = 0x00Z = 1



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CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT0 → WDT prescaler count,1 → TO1 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0100

Description: CLRWDT instruction clears the Watchdog Timer. It also clears thepostscaler count of the WDT. Status bits TO and PD are set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Nooperation

Processdata

ClearWDT

Counter

Example CLRWDT ; Clear the Watchdog; Timer count value

Before InstructionWDT counter = xWDT postscaler

count = 0WDT postscaler = 1:128TO = xPD = x

After InstructionWDT counter = 0x00WDT postscaler

count = 0WDT postscaler = 1:128TO = 1PD = 1

Note: The CLRWDT instruction does not affect the assignment of the WDT postscaler.



COMF Complement f

Syntax: [ label ] COMF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) → destination



Description: The contents of Register 'f' are 1’s complemented.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 COMF REG1, 0, 1 ; Complement the value in; Register REG1 and place the; result in the WREG Register

Case 1: Before InstructionREG1 = 0x13Z, N = x

After InstructionREG1 = 0x13WREG = 0xECZ = 0N = 1

; 0001 0011

; 1110 1100

Case 2: Before InstructionREG1 = 0xFFZ, N = x

After InstructionREG1 = 0xFFWREG = 0x00Z = 1N = 0

; 1111 1111

; 0000 0000

Case 3: Before InstructionREG1 = 0x00Z, N = x

After InstructionREG1 = 0x00WREG = 0xFFZ = 0N = 1

; 0000 0000

; 1111 1111



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Example 2 COMF INDF0, 1, 1 ; Complement the value in the; register pointed to by the; FSR0 (FSR0H:FSR0L); Register, placing the; result in that register

Before InstructionFSR0 = 0xFC2Contents of Address

(FSR0) = 0xAAZ, N = x

After InstructionFSR0 = 0xFC2Contents of Address

(FSR0) = 0x55Z = 0N = 0

; 1010 1010

; 0101 0101

Example 3 COMF REG1, 1, 1 ; Complement the value in; Register REG1 and place the; result in Register REG1

Before InstructionREG1 = 0xFFZ, N = x

After InstructionREG1 = 0x00Z = 1N = 0

; 1111 1111

; 0000 0000



CPFSEQ Compare f with WREG, Skip if Equal (f = WREG)

Syntax: [ label ] CPFSEQ f, a

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (f) - (WREG)skip if (f) = (WREG)



Description: Compares the contents of Register 'f' to the contents of WREG Register byperforming an unsigned subtraction.

If 'f' = WREG then the fetched instruction is discarded and a NOP is exe-cuted instead, making this a two-cycle instruction.


Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation



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Example HERENEQUALEQUAL

CPFSEQGOTO•••

FLAG, 1PROCESS_CODE

; Compare the value in; Register FLAG to the; WREG Register and skip; the next program memory; location if they are; equal

Case 1: Before InstructionPC = address HEREFLAG = 0x5AWREG = 0x5A

After InstructionPC = address EQUAL

; FLAG - WREG = 0x00

; The two values were; Equal

Case 2: Before InstructionPC = address HEREFLAG = 0xA5WREG = 0x5A

After InstructionPC = address NEQUAL

; FLAG - WREG = 0x4B

; The two values were; Not Equal



CPFSGT Compare f with WREG, Skip if Greater Than (f > WREG)

Syntax: [ label ] CPFSGT f, a

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (f) - (WREG)skip if (f) > (WREG); (unsigned comparison)



Description: Compares the contents of data memory location 'f' to the contents ofWREG Register by performing an unsigned subtraction.

If 'f' > WREG then the fetched instruction is discarded and a NOP is exe-cuted instead, making this a two-cycle instruction.


Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation



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Example HERENGTGT

CPFSGTGOTO•••

FLAG, 1PROCESS_CODE

; Compare the value in; Register FLAG to the; WREG Register and skip; the next program memory; location if; FLAG > WREG


After InstructionPC = address NGT


; The two values were; Equal (Not Greater Than)

Case 2: Before InstructionPC = address HEREFLAG = 0xA5WREG = 0x5A

After InstructionPC = address GT


; FLAG > WREG, Skip; the next instruction


CPFSLT Compare f with WREG, Skip if Less Than (f < WREG)

Syntax: [ label ] CPFSLT f, a

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (f) - (WREG); (unsigned comparison)skip if (f) < (WREG)



Description: Compares the contents of data memory location 'f' to the contents ofWREG Register by performing an unsigned subtraction.

If 'f' < WREG then the fetched instruction is discarded and an NOP is exe-cuted instead making this a two-cycle instruction.


Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

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Example HERENLTLT

CPFSLTGOTO•••

FLAG, 1PROCESS_CODE

; Compare the value in; Register FLAG to the; WREG Register and skip; the next program memory; location if; FLAG < WREG


After InstructionPC = address NLT


; the two values were; Equal (Not less than)

Case 2: Before InstructionPC = address HEREFLAG = 0x5AWREG = 0xA5

After InstructionPC = address LT


; FLAG < WREG, Skip; the next instruction

DAW Decimal Adjust WREG Register

Syntax: [ label ] DAW

Operands: None

Operation: If [WREG<3:0> >9] or [DC = 1] then(WREG<3:0>) + 6 → WREG<3:0>;

else(WREG<3:0>) → WREG<3:0>;

If [WREG<7:4> >9] or [C = 1] then(WREG<7:4>) + 6 → WREG<7:4>;

else(WREG<7:4>) → WREG<7:4>;

Status Affected: C

Encoding: 0000 0000 0000 0111

Description: DAW adjusts the eight bit value in WREG resulting from the earlier additionof two variables (each in packed BCD format) and produces a correctpacked BCD result.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode ReadRegister

REG

Processdata

Write toREG


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Example HERE DAW ; Decimal Adjust WREG

Case 1: Before InstructionWREG = 0x0FC = x

After InstructionWREG = 0x15C = 0

; 0x0F is 15 decimal

Case 2: Before InstructionWREG = 0x68C = x

After InstructionPC = 0x04C = 1

; 0x68 is 104 decimal

; Carry to indicate; decimal rollover

Case 3: Before InstructionWREG = C6C = x

After InstructionPC = 98C = 1

;; 0xC6 is 198 decimal

; Carry to indicate; decimal rollover



DECF Decrement f

Syntax: [ label ] DECF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) - 1 → destination



Description: Decrement the contents of Register 'f'.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 DECF CNT, 1, 1 ; Decrement Register CNT

Before InstructionCNT = 0x01C, DC, OV, N = xZ = 0

After InstructionCNT = 0x00C = 0DC = 0Z = 1OV = 0N = 0



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Example 2 DECF INDF0, 1, 1 ; Decrement the register; pointed to by the FSR; (FSR0H:FSR0L) Register


(FSR0) = 0x01C, DC, OV, N = xZ = 0


(FSR0) = 0x00C = 0DC = 0Z = 1OV = 0N = 0

Example 3 DECF CNT, 0, 1 ; Decrement Register CNT; WREG is destination

Before InstructionCNT = 0x10WREG = xZ = 0

After InstructionCNT = 0x10WREG = 0x0FC = 0DC = 1Z = 0OV = 0N = 0



DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]]a ∈ [0,1]

Operation: (f) - 1 → destination; skip if result = 0



Description: The contents of Register 'f' are decremented. If the result is 0, then thenext instruction (fetched during the current instruction execution) is dis-carded and a NOP is executed instead, making this a 2 cycle instruction.



Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

If skip and followed by 2 word instruction

Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation



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Example HERE

CONTINUE

DECFSZGOTO••

CNT, 1, 1LOOP

; Decrement Register CNT,; if CNT then equals 0; skip the next; instruction

Case 1: Before InstructionPC = address HERECNT = 0x01

After InstructionCNT = 0x00PC = address CONTINUE


After InstructionCNT = 0x01PC = address HERE + 2



DCFSNZ Decrement f, Skip if Not 0

Syntax: [ label ] DCFSNZ f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]]a ∈ [0,1]

Operation: (f) - 1 → destination; skip if result ≠ 0



Description: The contents of Register 'f' are decremented. If the result is not 0, thenthe next instruction (fetched during the current instruction execution) isdiscarded and a NOP is executed instead, making this a 2-cycle instruc-tion.



Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation



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Example HERE

CONTINUE

DCFSNZGOTO••

CNT, 1, 1LOOP

; Decrement Register CNT,; if CNT does not equal 0; skip the next instruction


After InstructionCNT = 0x00PC = address HERE + 2


After InstructionCNT = 0x01PC = address CONTINUE


GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 1048575

Operation: k → PC<20:1>0 → PC<0>,


Encoding:

1st word (k<7:0>)2nd word (k<19:8>)

11101111

1111k19kkk

k7kkkkkkk

kkkk0kkkk8

Description: GOTO allows an unconditional branch anywhere within the entire 2M bytememory range. The 20-bit immediate value ’k’ is loaded into PC<20:1>.GOTO is always a two-cycle instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

1st cycle:

Q1 Q2 Q3 Q4

Decode Readliteral

'k'<7:0>

Processdata

Nooperation

2nd cycle:

Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


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Example 1 HERE GOTO THERE ; Goto address THERE

After InstructionPC = Address THERE

Example 2 HERE GOTO $-2 ; GOTO address HERE - 2

After InstructionPC = Address HERE -2

Example 3 HERE GOTO $ ; GOTO address HERE; (infinite loop)

After InstructionPC = Address HERE

Example 4 HERE GOTO HERE ; GOTO address HERE; (infinite loop)

After InstructionPC = Address HERE



INCF Increment f

Syntax: [ label ] INCF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) + 1 → destination



Description: The contents of Register 'f' are incremented.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 INCF CNT,1, 1 ; Increment Register CNT

Before InstructionCNT = 0xFFC, DC, Z, OV, N = x

After InstructionCNT = 0x00C = 1DC = 1Z = 1OV = 0N = 0

; 1111 1111

; 0000 0000



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Example 2 INCF INDF0, 1, 1 ; Increment Register; indirectly; (FSR0 (FSR0H:FSR0L) points; to address to increment)


(FSR0) = 0xFFC, DC, Z, OV, N = x


(FSR0) = 0x00C = 1DC = 1Z = 1OV = 0N = 0

; 1111 1111

; 0000 0000

Example 3 INCF CNT, 0, 1 ; Increment Register CNT; place result in WREG

Before InstructionCNT = 0x10WREG = xC, DC, OV, N = xZ = 0

After InstructionCNT = 0x10WREG = 0x11C = 0DC = 0Z = 0OV = 0N = 0

; 0001 0000

; 0001 0001



INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) + 1 → destination, skip if result = 0



Description: The contents of Register 'f' are incremented. If the result is 0, then the nextinstruction (fetched during the current instruction execution) is discardedand a NOP is executed instead, making this a 2-cycle instruction.



Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation



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Example 1 HERENZEROZERO

INCFSZGOTO••

CNT, 1, 1LOOP

; Increment Register CNT,; if CNT then equals 0; skip the next; instruction

Case 1: Before InstructionPC = address HERECNT = 0xFF

After InstructionCNT = 0x00PC = address ZERO


After InstructionCNT = 0x01PC = address NZERO


INCFSZGOTO•••

CNT, 1, 0LOOP

; Increment Register CNT,; if CNT equals 0; skip the next; instruction

Case 1: Before InstructionPC = address HERECNT = 0xFF ; In access bank


Case 2: Before InstructionPC = address HERECNT = 0x00 ; In access bank




INFSNZ Increment f, Skip if Not 0

Syntax: [ label ] INFSNZ f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) + 1 → destination, skip if result ≠ 0



Description: The contents of Register 'f' are incremented. If the result is not 0, then thenext instruction (fetched during the current instruction execution) is dis-carded and a NOP is executed instead, making this a 2-cycle instruction.



Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation



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Example 1 HEREZERONZERO

INFSNZGOTO••

CNT, 1, 1LOOP

; Increment Register CNT,; if CNT does not equal 0; skip the next instruction

Case 1: Before InstructionPC = address HERECNT = 0xFF




Example 2 HEREZERONZERO

INFSNZGOTO•••

CNT, 1, 0LOOP

; Increment Register CNT,; if CNT does not equal 0; skip the next instruction

Case 1: Before InstructionPC = address HERECNT = 0xFF ; In access bank


Case 2: Before InstructionPC = address HERECNT = 0x00 ; In access bank




IORLW Inclusive OR Literal with WREG

Syntax: [ label ] IORLW k


Operation: (WREG).OR. k → WREG



Description: The contents of the WREG Register is OR’d with the eight bit literal 'k'. Theresult is placed in the WREG Register.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write toWREG

Register

Example 1 IORLW 0x35 ; bit wise OR 35h with the; WREG Register

Before InstructionWREG = 0x9AZ, N = x

After InstructionWREG = 0xBFZ = 0N = 1

; 0011 0101 (35h); 1001 1010

; 1011 1111

Example 2 IORLW MYREG ; bit wise OR the value of; the address of Register; MYREG with the WREG; Register

Before InstructionWREG = 0x9A

Address of MYREG †

= 0x37† MYREG is a symbol for adata memory locationZ, N = x

After InstructionWREG = 0xBFZ = 0N = 1

;; 1001 1010;; 0011 0111

; 1011 1111



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Example 3 IORLW HIGH (LU_TABLE) ; bit wise OR the value of; the high byte of address; LU_TABLE with the WREG; Register

Before InstructionWREG = 0x9A


= 0x9375† LU_TABLE is a label for anaddress in program memoryZ, N = x

After InstructionWREG = 0x9BZ = 0N = 1

; 1001 1010

; 1001 0011 (93h)

; 1001 1011

Example 4 IORLW 0x00 ; bit wise OR 00h with the; WREG Register

Before InstructionWREG = 0x00Z, N = x


; 0000 0000 (literal); 0000 0000

; 0000 0000



IORWF Inclusive OR WREG with f

Syntax: [ label ] IORWF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (WREG).OR. (f) → destination



Description: Inclusive OR the WREG Register with the contents of Register 'f'.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 IORWF INDF0, 1, 1 ; Comment

Before InstructionWREG = 0x17FSR0 = 0xDC2Contents of Address

(FSR0) = 0x30Z, N = x

After InstructionWREG = 0x17FSR0 = 0xDC2Contents of Address

(FSR0) = 0x37Z = 0N = 0

; 0001 0111

; 0011 0000

; 0011 0111



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Example 2 IORWF RESULT, 1, 1 ; bit wise OR the WREG; Register with the; Register RESULT.

Case 1: Before InstructionRESULT = 0x13WREG = 0x91Z, N = x

After InstructionRESULT = 0x93WREG = 0x91Z = 0N = 1

; 0001 0011; 1001 0001

; 1001 0011

Case 2: Before InstructionRESULT = 0x00WREG = 0x00Z, N = x

After InstructionRESULT = 0x00WREG = 0x00Z = 1N = 0

; 0000 0000; 0000 0000

; 0000 0000

Example 3 IORWF RESULT, 1, 0 ; bit wise OR the WREG; Register with the; register in the Access; bank at address of RESULT; Register.

Case 1: Before InstructionRESULT = 0x13(RESULT) in access bank

= 0xC8WREG = 0x91Z, N = x

After InstructionRESULT = 0x13(RESULT) in access bank

= 0xD9WREG = 0x91Z = 0N = 1

; 1100 1000; 1001 0001

; 1101 1001

Case 2: Before InstructionRESULT = 0x00(RESULT) in access bank

= 0x11WREG = 0x00Z, N = x

After InstructionRESULT = 0x00(RESULT) in access bank

= 0x11WREG = 0x00Z = 0N = 0

; 0001 0001; 0000 0000

; 0001 0001



LFSR Load 12-bit Literal to FSR

Syntax: [ label ] LFSR f, k

Operands: 0 ≤ f ≤ 20 ≤ k ≤ 4095

Operation: k → FSRx


Encoding:

1st word2nd word

11101111

11100000

00ffk7kkk

k11kkk8kkkk0

Description: The 12-bit literal 'k' is loaded into the File Select Register (FSR Register)pointed to by 'f':f = 00 → FSR0f = 01 → FSR1f = 10 → FSR2f = 11 → Reserved

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Readliteralk11:k8

Processdata

Write toFSRxHRegister

k11:k8

Decode Readliteral k7:k0

Processdata

Write toFSRxL

Registerk7:k0

Example 1 LFSR 2, 0x123 ; Load the 12-bit FSR2 with; 123h

Before InstructionFSR0H = 0x05FSR0L = 0xA5FSR1H = 0x05FSR1L = 0xA5FSR2H = 0x05FSR2L = 0xA5

After InstructionFSR0H = 0x05FSR0L = 0xA5FSR1H = 0x05FSR1L = 0xA5FSR2H = 0x01FSR2L = 0x23



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Example 2 LFSR 0, 0xFE3 ; Load the 12-bit FSR0 with; FE3h


After InstructionFSR0H = 0x0FFSR0L = 0xE3FSR1H = 0x05FSR1L = 0xA5FSR2H = 0x05FSR2L = 0xA5

Example 3 LFSR 1, 0xFE3 ; Load the 12-bit FSR1 with; FE3h


After InstructionFSR0H = 0x05FSR0L = 0xA5FSR1H = 0x0FFSR1L = 0xE3FSR2H = 0x05FSR2L = 0xA5



MOVF Move f

Syntax: [ label ] MOVF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: f → destination



Description: The contents of Register 'f' is moved to a destination dependent upon thestatus of the ’d’ and ’a’ bits.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write toWREG

Register

Example 1 MOVF MYREG, 0, 1 ; Copy the contents of; Register MYREG to the WREG; Register

Before InstructionMYREG = 0x22WREG = 0xFFZ, N = x

After InstructionMYREG = 0x22WREG = 0x22Z = 0N = 0

Example 2 MOVF MYREG, 1, 1 ; Copy the contents of; Register MYREG to itself; (affects the status bits)

Before InstructionMYREG = 0x00WREG = 0x10Z, N = x




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Example 3 MOVF MYREG, 1, 0 ; Copy the contents of; Register MYREG in the; access bank to itself; (affects the status bits)

Case 1: Before InstructionMYREG = 0x00WREG = 0x10Z, N = x


; In access bank

; In access bank

Case 2: Before InstructionMYREG = 0x80WREG = 0x10Z, N = x


; In access bank

; In access bank



MOVFF Move f to f

Syntax: [ label ] MOVFF fs, fd

Operands: 0 ≤ fs ≤ 40950 ≤ fd ≤ 4095

Operation: (fs) → fd


Encoding:

1st word (source)2nd word

(destination)

11001111

ffffffff

ffffffff

ffffffff

Description: The contents of Source Register 'fs' are moved to Destination Register 'fd'.Location of source 'fs' can be anywhere in the 4096 byte data space (000hto FFFh), and location of destination 'fd' can also be anywhere from 000h toFFFh.

MOVFF is particularly useful for transferring a data memory location to aPeripheral Register (such as the transmit buffer or an I/O port) withoutaffecting the WREG Register.

Note: The MOVFF instruction cannot use the PCL, TOSU, TOSH, andTOSL as the Destination Register

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode ReadSource

Register f

Processdata

Nooperation

Decode Nooperation

Nooperation

Write todestinationRegister f

Example 1 MOVFF REG1, REG2 ; Copy the contents of; Register REG1 to Register; REG2

Before InstructionREG1 = 0x33REG2 = 0x11

After InstructionREG1 = 0x33REG2 = 0x33

Example 2 MOVFF REG2, REG1 ; Copy the contents of; Register REG2 to Register; REG1

Before InstructionREG1 = 0x33REG2 = 0x11

After InstructionREG1 = 0x11REG2 = 0x11


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MOVLB Move Literal to low nibble in BSR

Syntax: [ label ] MOVLB k


Operation: k → BSR<3:0>


Encoding: 0000 0001 0000 kkkk

Description: The 4-bit literal 'k' is loaded into the Bank Select Register (BSR).

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Writeliteral ’k’to BSR

Example 1 MOVLB 5 ; Modify Least Significant; nibble of BSR Register; to value 5

Before InstructionBSR = 0x02

After InstructionBSR = 0x05

Example 2 MOVLB 9 ; Modify Least Significant; nibble of BSR Register; to value 9

Before InstructionBSR = 0x0F

After InstructionBSR = 0x09


MOVLW Move Literal to WREG

Syntax: [ label ] MOVLW k


Operation: k → WREG



Description: The eight bit literal 'k' is loaded into WREG Register.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write toWREG

Register

Example 1 MOVLW 0x5A ; Load the WREG Register; with the value 5Ah

Before InstructionWREG = x

After InstructionWREG = 0x5A

Example 2 MOVLW MYREG ; Load the WREG Register; with the value of the; address of MYREG


Address of MYREG † = 0x37† MYREG is a symbol for a data memory location

After InstructionWREG = 0x37

Example 3 MOVLW HIGH (LU_TABLE) ; Load the WREG Register; with the value of the high; byte of address LU_TABLE


Address of LU_TABLE † = 0x9375† LU_TABLE is a label for an address in program memory

After InstructionWREG = 0x93



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MOVWF Move WREG to f

Syntax: [ label ] MOVWF f, a

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (WREG) → f



Description: Move data from WREG Register to Register 'f'.


Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode ReadWREG

Register

Processdata

WriteRegister 'f'

Example 1 MOVWF OPTION_REG, 1; Copy the value in the WREG; Register to the; OPTION_REG Register

Before InstructionOPTION_REG = 0xFFWREG = 0x4F

After InstructionOPTION_REG = 0x4FWREG = 0x4F

Example 2 MOVWF INDF0, 1 ; Copy the value in the WREG; Register to the; FSR0 (FSR0H:FSR0L); Register

Before InstructionWREG = 0x17FSR0 = 0x5C2Contents of Address (FSR0) = 0x00

After InstructionWREG = 0x17FSR0 = 0x5C2Contents of Address (FSR0) = 0x17



MULLW Multiply Literal with WREG

Syntax: [ label ] MULLW k


Operation: (WREG) x k → PRODH:PRODL



Description: An unsigned multiplication is carried out between the contents of WREGand the 8-bit literal 'k'. The 16-bit result is placed in PRODH:PRODL Regis-ter Pair. PRODH contains the high byte.

WREG is unchanged.

None of the status flags are affected.

Neither an overflow nor carry is possible in this operation. A zero result ispossible but not detected.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

WriteRegistersPRODH:PRODL

Example 1 MULLW 0xC4 ; Multiply the WREG Register; with the constant value; C4h

Before InstructionWREG = 0xE2PRODH = xPRODL = x

After InstructionWREG = 0xE2PRODH = 0xADPRODL = 0x08

Example 2 MULLW FACTOR ; Multiply the WREG Register; with the constant value; FACTOR

Before InstructionFACTOR = 0xC4WREG = 0xE2PRODH = xPRODL = x

After InstructionWREG = 0xE2PRODH = 0xADPRODL = 0x08



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MULWF Multiply WREG with f

Syntax: [ label ] MULWF f, a

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (WREG) x (f) → PRODH:PRODL



Description: An unsigned multiplication is carried out between the contents of WREGand the value in Register File Location 'f'. The 16-bit result is placed in thePRODH:PRODL Register Pair. PRODH contains the high byte.

Both WREG and 'f' are unchanged.

None of the status flags are affected.

Neither an overflow nor carry is possible in this operation. A zero result ispossible but not detected.


Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

WriteRegistersPRODH:PRODL

Example MULWF MYREG, 1 ; Multiple the WREG; Register with the value; in MYREG Register

Before InstructionWREG = 0xE2MYREG = 0xB5PRODH = xPRODL = x

After InstructionWREG = 0xE2MYREG = 0xB5PRODH = 0x9FPRODL = 0xCA



NEGF Negate f

Syntax: [ label ] NEGF f, a

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: ( f ) + 1 → (f)



Description: Location ’f’ is negated using two’s complement. The result is placed in thedata memory location 'f'.


Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

WriteRegister ’f’

Example 1 NEGF MYREG, 1 ; 2’s complement the value in; MYREG

Case 1: Before InstructionMYREG = 0x3AC, DC, Z, OV, N = x

After InstructionMYREG = 0xC6C = 0DC = 0Z = 0OV = 0N = 1

; 0011 1010

; 1100 0110

Case 2: Before InstructionMYREG = 0xB0C, DC, Z, OV, N = x

After InstructionMYREG = 0x50C = 0DC = 1Z = 0OV = 0N = 0

; 1011 0000

; 0101 0000

Case 3: Before InstructionMYREG = 0x00C, DC, Z, OV, N = x

After InstructionMYREG = 0x00C = 1DC = 1Z = 1OV = 0N = 0

; 0000 0000

; 0000 0000



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NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation


Encoding:

DefaultUsed with 2 word

instructions

00001111

0000xxxx

0000xxxx

0000xxxx

Description: No operation.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Nooperation

Nooperation

Nooperation

Example HERE NOP ; This instruction cycle; does nothing; (No Operation)


After InstructionPC = address HERE + 2



POP POP Top of Return Stack

Syntax: [ label ] POP

Operands: None

Operation: (TOS) → bit bucket


Encoding: 0000 0000 0000 0110

Description: The Top of Stack (TOS) value is pulled off the return stack and is discarded.The TOS value then becomes the previous value that was pushed onto thereturn stack.

This instruction is provided to enable the user to manage the return stack toincorporate a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Nooperation

Nooperation

POP TOSvalue

Example HERE POP ; Modify the Top of Stack; (TOS). The TOS points to; what was one level down

Before InstructionTOS = 0x0031A2Stack (1 level down) = 0x014332

After InstructionTOS = 0x014332PC = HERE + 2



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PUSH PUSH Top of Return Stack

Syntax: [ label ] PUSH

Operands: None

Operation: PC → (TOS)


Encoding: 0000 0000 0000 0101

Description: The previous Top of Stack (TOS) value is pushed down on the stack. ThePC is pushed onto the top of the return stack.

This instruction is provided to enable the user to manage the return stack toincorporate a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode PUSH PConto return

stack

Nooperation

Nooperation

Example HERE PUSH ; PUSH current Program; Counter value onto the; hardware stack

Before InstructionPC = 0x000124TOS = 0x00345A

After InstructionPC = 0x000126TOS = 0x000124Stack (1 level down)

= 0x00345A


RCALL Relative Call

Syntax: [ label ] RCALL n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC + 2) → TOS,(PC + 2) + 2n → PC


Encoding: 1101 1nnn nnnn nnnn

Description: Subroutine call with a jump up to 1K from the current location. First, thereturn address (PC+2) is pushed onto the stack. Then the 2’s complementnumber ’2n’ is added to the PC. Since the PC will have incremented to fetchthe next instruction, the new address will be PC+2+2n. This instruction is atwo-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Readliteral ’n’,Push PCto stack

ProcessData

Write toPC

Nooperation

Nooperation

Nooperation

Nooperation

Example 1 HERE RCALL Sub1 ; Call a program memory; location (Sub1); this location must be; < 1024 locations forward or; > 1025 locations backward

Before InstructionPC = Address (HERE)TOS = 0x0031A2

After InstructionPC = Address (Sub1)TOS = Address (HERE + 2)Stack (1 level down)

= 0x0031A2

Example 2 HEREPLUS0PLUS1PLUS2PLUS3PLUS4PLUS5PLUS6

RCALL•••••••

$ + OFFSET ; Call to HERE+OFFSET


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Example 3 MIN6MIN5MIN4MIN3MIN2MIN1MIN0HERENEXT

•••••••RCALL $ - OFFSET

; Call to HERE-OFFSET





RESET Reset Device

Syntax: [ label ] RESET

Operands: None

Operation: Force all registers and flag bitsthat are affected by a MCLR resetto their reset condition.

Status Affected: All

Encoding: 0000 0000 1111 1111

Description: This instruction provides a way to execute a software reset.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Nooperation

Nooperation

Startreset



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Example HERE RESET ; Do a software reset

Before InstructionPC = address HEREC, DC, Z, OV, N = x

After InstructionPC = 0x000000SFRs = See reset sectionGPRs = u (unchanged)



RETFIE Return from Interrupt

Syntax: [ label ] RETFIE s

Operands: s ∈ [0,1]

Operation: (TOS) → PC,if IPEN = 0 (compatibility mode)

1 → GIEif IPEN = 1

GIEH GEIL1 1 1 → Invalid1 0 1 → GIEL0 1 1 → GIEH0 0 1 → GIEH

if s = 1(WREGS) → WREG(STATUSS) → STATUS(BSRS) → BSR

if s = 0(WREGS) → unchanged(STATUSS) → unchanged(BSRS) → unchanged

In both cases PCLATU, PCLATH are unchanged.

Status Affected: GIE/GIEH,PEIE/GIEL

Encoding: 0000 0000 0001 000s

Description: Return from Interrupt. Stack is popped and Top of Stack (TOS) is loadedinto the PC. Interrupts are enabled by setting either the high or low priorityglobal interrupt enable bits (GIEH or GIEL).

If ’s’ = 1, the contents of the Shadow Registers WREGS, STATUSS andBSRS are loaded into their corresponding registers, WREG, STATUSand BSR.

If ’s’ = 0, no update of these registers occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

1st cycle:

Q1 Q2 Q3 Q4

Decode Nooperation

Set GIEHor GIEL

POP PCfrom stack

2nd cycle:

Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation



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Example 1 HERE RETFIE 0 ; Return from interrupt,; enable interrupts

Before InstructionPC = address HEREGIE/GIEH, PEIE/GIEL = xWREG = xBSR = xSTATUS = x

After InstructionPC = TOSGIE/GIEH, PEIE/GIEL = 1WREG = unchangedBSR = unchangedSTATUS = unchanged

Example 2 HERE RETFIE 1 ; Return from interrupt,; enable interrupts.; This is a fast return so; the BSR, WREG, and STATUS; Registers are restored; with the values in the; Fast Register Stack

Before InstructionPC = address HEREGIE/GIEH, PEIE/GIEL = xWREG = xBSR = xSTATUS = x

After InstructionPC = TOSGIE/GIEH, PEIE/GIEL = 1WREG = WREGSBSR = BSRSSTATUS = STATUSS



RETLW Return with Literal in W

Syntax: [ label ] RETLW k


Operation: k → WREG;TOS → PCPCLATU and PCLATH are unchanged



Description: The WREG Register is loaded with the eight bit literal 'k'. The programcounter is loaded from the Top of Stack (the return address). The upper andhigh address latches (PCLATU:PCLATH) remain unchanged. This is a two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

1st cycle:

Q1 Q2 Q3 Q4


Processdata

POP PCfrom stack,

write toWREG

2nd cycle:

Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation



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Example HERE

TABLE

CALL•••ADDWFRETLWRETLW•••RETLW

TABLE

PCk1k2

kn

; WREG contains table offset; value WREG now has table; value

; WREG = offset; Begin table,; Return with constant in WREG

; End of table

Before InstructionWREG = x

After InstructionWREG = value of kxPC = TOS = Address HERE + 2



RETURN Return from Subroutine

Syntax: [ label ] RETURN s

Operands: s ∈ [0,1]

Operation: (TOS) → PCif s = 1

(WREGS) → WREG(STATUSS) → STATUS(BSRS) → BSR

if s = 0(WREGS) → unchanged(STATUSS) → unchanged(BSRS) → unchanged

In both cases PCLATU and PCLATH are unchanged


Encoding: 0000 0000 0001 001s

Description: Return from subroutine. The stack is popped and the Top of Stack(TOS) is loaded into the program counter.If ’s’ = 1, the contents of the Shadow Registers WREGS, STATUSS andBSRS are loaded into their corresponding registers, WREG, STATUSand BSR.If ’s’ = 0, no update of these registers occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

1st cycle:

Q1 Q2 Q3 Q4

Decode Nooperation

Processdata

POP PCfrom stack

2nd cycle:

Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Example 1 HERE RETURN 0 ; Return from subroutine.

Before InstructionPC = address HEREWREG = xBSR = xSTATUS = x

After InstructionPC = TOSWREG = unchangedBSR = unchangedSTATUS = unchanged



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Example 2 HERE RETURN 1 ; Return from subroutine.; This is a fast return so; the BSR, WREG, and STATUS; Registers are restored; with the values in the; Fast Register Stack

Before InstructionPC = address HEREWREG = xBSR = xSTATUS = x

After InstructionPC = TOSWREG = WREGSBSR = BSRSSTATUS = STATUSS



RLCF Rotate Left f through Carry

Syntax: [ label ] RLCF f, d, a

Operands: 0 ≤ f ≤ 127d ∈ [0,1]a ∈ [0,1]

Operation: See description below

Status Affected: C, Z, N


Description: The contents of Register 'f' are rotated one bit to the left through the CarryFlag.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Register fC

Example 1 RLCF REG1, 0, 1 ; Rotate the value in REG1; 1 bit position left and; the carry bit loads into; bit 0. Then place the; result in the WREG; Register

Before InstructionREG1 = 1110 0110C = 0Z, N = x

After InstructionREG1 = 1110 0110WREG = 1100 1100C = 1Z = 0N = 1



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Example 2 RLF INDF0, 1, 1 ; Rotate the value in the; register pointed by the; FSR0 (FSR0H:FSR0L); Register 1 bit position; left and place the result; back into that register; Carry loads into bit 0

Case 1: Before InstructionFSR0 = 0x0C2Contents of Address

(FSR0) = 0011 1010C = 1Z, N = x


(FSR0) = 0111 0101C = 0Z = 0N = 0


(FSR0) = 1011 1001C = 0Z, N = x


(FSR0) = 0111 0010C = 1Z = 0N = 0



RLNCF Rotate Left f (No Carry)

Syntax: [ label ] RLNCF f, d, a

Operands: 0 ≤ f ≤ 127d ∈ [0,1]a ∈ [0,1]




Description: The contents of Register 'f' are rotated one bit to the left. The Carry Flagbit is not affected.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 RLNCF REG1, 0, 1 ; Rotate the value in REG1; 1 bit position left and; bit 7 loads into bit 0.; Then place the result in; the WREG Register

Before InstructionREG1 = 1110 0110Z, N = x

After InstructionREG1 = 1110 0110WREG = 1100 1101Z = 0N = 1

Register f



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Example 2 RLNCF INDF0, 1, 1 ; Rotate the value in the; register pointed by the; FSR0 (FSR0H:FSR0L); Register 1 bit position left; and place the result in the; back into that register.; bit 7 loads into bit 0.


(FSR0) = 0011 1010Z, N = x


(FSR0) = 0111 0100Z = 0N = 0


(FSR0) = 1011 1001Z, N = x


(FSR0) = 0111 0011Z = 0N = 0



RRCF Rotate Right f through Carry

Syntax: [ label ] RRCF f, d, a

Operands: 0 ≤ f ≤ 127d ∈ [0,1]a ∈ [0,1]


Status Affected: C, Z, N


Description: The contents of Register 'f' are rotated one bit to the right through the CarryFlag.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Register fC

Example 1 RRCF REG1, 0, 1 ; Rotate the value in REG1; 1 bit position right and; the carry bit loads into; bit 7. Then place the; result in the WREG; Register

Before InstructionREG1 = 1110 0110WREG = xxxx xxxxC = 0Z, N = x

After InstructionREG1 = 1110 0110WREG = 0111 0011C = 0Z = 0N = 0



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Example 2 RRCF INDF0, 1, 1 ; Rotate the value in the; register pointed by the; FSR0 (FSR0H:FSR0L); Register 1 bit position; right and place the result; in the back into that; register.; Carry loads into bit 7.


(FSR0) = 0011 1010C = 1Z, N = x


(FSR0) = 1001 1101C = 0Z = 0N = 1


(FSR0) = 0011 1001C = 0Z, N = x


(FSR0) = 0001 1100C = 1Z = 0N = 0



RRNCF Rotate Right f (No Carry)

Syntax: [ label ] RRNCF f, d, a

Operands: 0 ≤ f ≤ 127d ∈ [0,1]a ∈ [0,1]




Description: The contents of Register 'f' are rotated one bit to the right. The Carry Flagbit is not affected.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 RRNCF REG1, 0, 1 ; Rotate the value in REG1; 1 bit position right and; bit 0 loads into bit 7.; Then place the result in; the WREG Register

Before InstructionREG1 = 1110 0110WREG = xZ, N = 1

After InstructionREG1 = 1110 0110WREG = 0111 0011Z = 0N = 0

Register f



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Example 2 RRNCF INDF0, 1, 1 ; Rotate the value in the; register pointed by the; FSR (FSR0H:FSR0L); Register 1 bit; position right and place; the result back into; that register.; bit 0 loads into bit 7.


(FSR0) = 0011 1010Z, N = x


(FSR0) = 0001 1101Z = 0N = 0


(FSR0) = 0011 1001Z, N = x


(FSR0) = 1001 1100Z = 0N = 1



SETF Set f

Syntax: [ label ] SETF f, a

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: FFh → f



Description: The contents of the specified register are set.


Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

WriteRegister 'f'

Example 1 SETF FLAG_REG, 1 ; Set all the bits in; Register FLAG_REG

Before InstructionFLAG_REG = 0x5A

After InstructionFLAG_REG = 0xFF

Example 2 SETF INDF0, 1 ; Set all the bits in the; register pointed to by the; FSR (FSR0H:FSR0L) Register


(FSR0) = 0xAAAfter Instruction


(FSR0) = 0xFF



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SLEEP Enter SLEEP mode

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h → WDT,0 → WDT prescaler count,1 → TO,0 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0011

Description: The power-down status bit, PD is cleared. Time-out status bit, TO is set.Watchdog Timer and its prescaler count are cleared.The processor is put into SLEEP mode with the oscillator stopped.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Nooperation

Nooperation

Go tosleep

Example: SLEEP ; Turn off the device; oscillator. This is the; lowest power mode

Before InstructionTO = ?PD = ?

After InstructionTO = 1 †PD = 0

† If WDT causes wake-up, this bit is cleared

Note: The SLEEP instruction does not affect the assignment of the WDT prescaler.



SUBFWB Subtract f from WREG with borrow

Syntax: [ label ] SUBFWB f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (WREG) – (f) – (C) → destination



Description: Subtract Register 'f' and carry flag (borrow) from W (2’s complementmethod).



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode ReadRegister ’f ’

Processdata

Write todestination

Example 1 SUBFWB MYREG, 1, 1 ; WREG - MYREG - borrow bit

Before InstructionMYREG = 0x37WREG = 0x10C, DC, Z, OV, N = xC = 0

After InstructionMYREG = 0xA8WREG = 0x10C = 0DC = 0Z = 0OV = 0N = 1

; result is negative



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Example 2: SUBFWB MYREG, 1, 1 ; WREG - MYREG - borrow bit

Case 1: Before Instruction

MYREG = 0x03WREG = 0x02C = 1DC, Z, OV, N = x

After Instruction

MYREG = 0xFFWREG = 0x02C = 0DC = 0Z = 0OV = 0N = 1 ; result is negative



After Instruction

MYREG = 0x00WREG = 0x02C = 1DC = 1Z = 1OV = 0N = 0

; result is zero



After Instruction

MYREG = 0x02WREG = 0x03C = 1DC = 1Z = 0OV = 0N = 0

; result is positive



SUBLW Subtract W from Literal

Syntax: [ label ] SUBLW k


Operation: k - (WREG) → WREG



Description: The WREG Register is subtracted (2’s complement method) from the eightbit literal 'k'. The result is placed in the WREG Register.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write toWREG

Register

Example 1 SUBLW OFFSET ; Subtract the value in; WREG from the constant; OFFSET

Before InstructionWREG = 0x37OFFSET = 0x10C, DC, Z, OV, N = x

After InstructionWREG = 0xD9C = 0DC = 0Z = 0OV = 0N = 1




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Example 2: SUBLW 0x02 ; Subtract WREG Register; from 2h


WREG = 0x01C, DC, Z, OV, N = x

After Instruction

WREG = 0x01C = 1DC = 1Z = 0OV = 0N = 0




After Instruction

WREG = 0x00C = 1DC = 1Z = 1OV = 0N = 0

; result is zero



After Instruction

WREG =0xFFC = 0DC = 0Z = 0OV = 0N = 1




SUBWF Subtract W from f

Syntax: [ label ] SUBWF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) - (WREG) → destination



Description: Subtract (2’s complement method) WREG Register from Register 'f'.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1: SUBWF REG1, 1, 1 ; Subtract the value in the; WREG Register from REG1,; placing the result in REG1


REG1 = 3WREG = 2C, DC, Z, OV, N = x

After Instruction

REG1 = 1WREG = 2C = 1DC = 1Z = 0OV = 0N = 0




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After Instruction

REG1 = 0WREG = 2C = 1DC = 1Z = 1OV = 0N = 0

; result is zero



After Instruction

REG1 = 0xFFWREG = 2C = 0DC = 0Z = 0OV = 0N = 1




SUBWFB Subtract W from f with Borrow

Syntax: [ label ] SUBWFB f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) - (WREG) - (C) → destination



Description: Subtract (2’s complement method) WREG Register from Register 'f' withborrow.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1: SUBWF REG1, 1, 1 ; Subtract the value in the; WREG Register from REG1,; placing the result in REG1


REG1 = 3WREG = 2C = 1DC, Z, OV, N = x

After Instruction

REG1 = 1WREG = 2C = 1DC = 1Z = 0OV = 0N = 0




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After Instruction

REG1 = 0WREG = 2C = 1DC = 1Z = 1OV = 0N = 0

; result is zero



After Instruction

REG1 = 0xFFWREG = 2C = 0DC = 0Z = 0OV = 0N = 1



SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f<3:0>) → destination<7:4>,(f<7:4>) → destination<3:0>



Description: The upper and lower nibbles of Register 'f' are exchanged.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 SWAPF REG1, 0, 1 ; Swap the high and low; nibble of Register REG1; and place the result in; the WREG Register

Before Instruction

REG1 = 0xA5WREG = x

After Instruction

REG1 = 0xA5WREG = 0x5A


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Example 2 SWAPF INDF0, 1, 1 ; Swap the high and low; nibble of register pointed; to by the FSR; (FSR0H:FSR0L) Register,; placing the result back; into that register


(FSR0) = 0x20After Instruction


(FSR0) = 0x02

Example 3 SWAPF REG1, 1, 1 ; Swap the high and low; nibble of Register REG1; placing the result back; into that register

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0x5A



TBLRD Table Read

Syntax: [ label ] TBLRD[*, *+, *-, or +*]

Operands: 0 ≤ m ≤ 3

Operation: if TBLRD *,(Prog Mem (TBLPTR)) → TABLAT;TBLPTR - No Change;

if TBLRD *+,(Prog Mem (TBLPTR)) → TABLAT;(TBLPTR) +1 → TBLPTR;

if TBLRD *-,(Prog Mem (TBLPTR)) → TABLAT;(TBLPTR) -1 → TBLPTR;

if TBLRD +*,(TBLPTR) +1 → TBLPTR;(Prog Mem (TBLPTR)) → TABLAT;


Encoding: 0000 0000 0000 10mm * → mm = 00*+ → mm = 01*- → mm = 10+* → mm = 11

Description: This instruction is used to read the contents of Program Memory. Toaddress the program memory a pointer called Table Pointer (TBLPTR) isused.

The TBLPTR (a 21-bit pointer) points to each byte in the program memory.TBLPTR has a 2 Mbyte address range. The LSb of the TBLPTR selectswhich byte of the program memory location to access.

TBLPTR[0] = 0: Least Significant byte of Program Memory WordTBLPTR[0] = 1: Most Significant byte of Program Memory Word

The Program Memory word address is the same as the TBLPTR address,except that the LSb of TBLPTR (TBLPTR[0]) is always forced to ’0’.

The TBLRD instruction can modify the value of TBLPTR as follows:

• no change• post-increment• post-decrement• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

1st cycle:

Q1 Q2 Q3 Q4

Decode Nooperation

Nooperation

Nooperation

2nd cycle:

Nooperation

Nooperation

(TablePointer onAddress

bus)

Nooperation

Nooperation(OE goes

low)



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Example 31-3:Program Memory Contents for Examples

Word Address(points to low byte)

Data Word Word Address(points to low byte)

Data Word

MSb LSb MSb LSb

0x00A356 0x12 0x34 0x000000 0x01 0x00

0x00A358 0x56 0x28 0x000002 0x03 0x02

0x00A35A 0xAA 0x55 0x000004 0x05 0x04

0x00A35C 0xFF 0xFE 0x000006 0x07 0x06

0x00A35E 0xB1 0x00 0x000008 0x08 0x07

Example 1 TBLRD*+ ; Read byte addressed by; TBLPTR, then increment; TBLPTR

Before InstructionTABLAT = xTBLPTR = 0x00A356Contents of Address (TBLPTR)= 0x34

After InstructionTABLAT = 0x34TBLPTR = 0x00A357

Example 2 TBLRD+* ; Increment TBLPTR, then; Read byte addressed by; TBLPTR

Before InstructionTABLAT = xTBLPTR = 0x00A357Contents of Address (TBLPTR)= 0x12Contents of Address (TBLPTR + 1)= 0x28


Example 3 TBLRD*- ; Read byte addressed by; TBLPTR, then decrement; TBLPTR



Example 4 TBLRD* ; Read byte addressed by; TBLPTR. TBLPTR is unchanged





TBLWT Table Write

Syntax: [ label ] TBLWT[*, *+, *-, +*]

Operands: 0 ≤ m ≤ 3

Operation: if TBLWT*,

(TABLAT) → Prog Mem (TBLPTR) or Holding Register1;TBLPTR - No Change;

if TBLWT*+,

(TABLAT) → Prog Mem (TBLPTR) or Holding Register1;(TBLPTR) +1 → TBLPTR;

if TBLWT*-,

(TABLAT) → Prog Mem (TBLPTR) or Holding Register1;(TBLPTR) -1 → TBLPTR;

if TBLWT+*,(TBLPTR) +1 → TBLPTR;

(TABLAT) → Prog Mem (TBLPTR) or Holding Register1;

Note 1: The use of a Holding Register(s) is device specific. Please referto the Device Data Sheet for information on the operation of theTBLWT instruction with the Program Memory.


Encoding: 0000 0000 0000 11mm * → mm = 00*+ → mm = 01*- → mm = 10+* → mm = 11

Description: This instruction is used to program the contents of Program Memory. Toaddress the program memory a pointer called Table Pointer (TBLPTR) isused.

The TBLPTR (a 21-bit pointer) points to each byte in the program memory.TBLPTR has a 2 MBtye address range. The LSb of the TBLPTR selectswhich byte of the program memory location to access.

TBLPTR[0] = 0: Least Significant byte of Program Memory WordTBLPTR[0] = 1: Most Significant byte of Program Memory Word

The Program Memory word address is the same as the TBLPTR address,except that the LSb of TBLPTR (TBLPTR[0]) is always forced to ’0’.

The TBLWT instruction can modify the value of TBLPTR as follows:

• no change• post-increment• post-decrement• pre-increment

Words: 1

Cycles: 2 (many if long write to internal program memory)

Q Cycle Activity:

1st cycle:

Q1 Q2 Q3 Q4

Decode Nooperation

Nooperation

Nooperation

2nd cycle:

Nooperation

Nooperation

(Table Pointeron Address

bus)

Nooperation

Nooperation

(Table Latch onAddress bus,WR goes low)



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Example 31-4:Program Memory Contents for Examples

Word Address(points to low byte)

OriginalData Word

(before)

Example 1Data Word

(after)

Example 2Data Word

(after)

Example 3Data Word

(after)

Example 4Data Word

(after)

MSb LSb MSb LSb MSb LSb MSb LSb MSb LSb

0x00A356 0x12 0x34 0x12 0x55 0x12 0x34 0xAA 0x34 0x12 0x34

0x00A358 0x56 0x28 0x56 0x28 0x56 0xAA 0x56 0x28 0x5A 0x28

0x00A35A 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55

TABLAT 0x55 0xAA 0xAA 0x5A

Example 1 TBLWT*+ ; Write byte addressed by; TBLPTR, then increment TBLPTR

Before InstructionTABLAT = 0x55TBLPTR = 0x00A356Contents of (TBLPTR) = 0x34

After InstructionTBLPTR = 0x00A357Contents of (TBLPTR) = 0x55

Example 2 TBLWT+* ; Increment TBLPTR, then Write; byte addressed by TBLPTR

Before InstructionTABLAT = 0xAATBLPTR = 0x00A357Contents of (TBLPTR) = 0x12Contents of (TBLPTR + 1) = 0x28

After InstructionTBLPTR = 0x00A358Contents of (TBLPTR) = 0x12Contents of (TBLPTR + 1) = 0xAA

Example 3 TBLWT*- ; Write byte addressed by; TBLPTR, then decrement TBLPTR

Before InstructionTABLAT = 0xAATBLPTR = 0x00A357Contents of (TBLPTR) = 0x12

After InstructionTBLPTR = 0x00A356Contents of (TBLPTR) = 0xAA

Example 4 TBLWT* ; Write byte addressed by; TBLPTR. TBLPTR is unchanged

Before InstructionTABLAT = 0x5ATBLPTR = 0x00A359Contents of (TBLPTR) = 0x56

After InstructionTBLPTR = 0x00A359Contents of (TBLPTR) = 0x5A



TSTFSZ Test f, Skip if 0

Syntax: [ label ] TSTFSZ f, a

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: Skip if (f) = 0



Description: If Register 'f' = 0, the next instruction fetched is discarded and a NOP isexecuted (two NOPs if the fetched instruction is a two-cycle instruction).


Words: 1

Cycles: 1 (2 or 3)

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation


Q1 Q2 Q3 Q4

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Nooperation

Example 1A HERENZEROZERO

TSTFSZ••

REG1, 1 ; If Register REG1 is zero; then skip the next; program memory address

Before Instruction

REG1 = 0xAFPC = Address (HERE)

After Instruction

PC = Address (NZERO)



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TSTFSZ••


Before Instruction

REG1 = 0x00PC = Address (HERE)

After Instruction

PC = Address (ZERO)


TSTFSZ••


Case 1 Before Instruction

REG1 = 0xAFAddress of REG1 = 0x9A, Bank 30x9A, Bank 15 = 0x00PC = Address (HERE)

After Instruction

PC = Address (ZERO)

Case 2 Before Instruction

REG1 = 0x00Address of REG1 = 0x9A, Bank 30x9A, Bank 15 = 0xAFPC = Address (HERE)

After Instruction

PC = Address (NZERO)


TSTFSZ••

INDF0, 1 ; If Register pointed to by; FSR0 (FSR0H:FSR0L) is; zero, then skip the next; program memory address

Case 1 Before InstructionFSR0 = 0x6C2Contents of Address

(FSR0) = 0xAFPC = Address (HERE)


(FSR0) = 0xAFPC = Address (NZERO)

Case 2 Before InstructionFSR0 = 0x6C2Contents of Address (FSR0) = 0x00PC = Address (HERE)

After InstructionFSR0 = 0x6C2Contents of Address (FSR0) = 0x00PC = Address (ZERO)



XORLW Exclusive OR Literal with W

Syntax: [ label] XORLW k


Operation: (WREG).XOR. k → W



Description: The contents of the WREG Register are XOR’ed with the eight bit literal 'k'.The result is placed in the WREG Register.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write toWREG

Register

Example 1 XORLW 0xAF ; Exclusive OR the value; in WREG with AFh

Before Instruction

WREG = 0xB5Z, N = x

; 1011 0101 (0xB5); 1010 1111 (0xAF)

After Instruction ; --------- ------

WREG = 0x1AZ = 0N = 0

; 0001 1010 (0x1A)

Example 2 XORLW MYREG ; Exclusive OR the value; in WREG with the address; of MYREG

Before InstructionWREG = 0xAF

Address of MYREG †

= 0x37Z, N = x† MYREG is a symbol for adata memory location


; 1010 1111;; 0011 0111; ---- ----; 1001 1000



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Example 3 XORLW HIGH (LU_TABLE) ; Exclusive OR the value; in WREG with the high; byte of the address of; LU_TABLE

Before InstructionWREG = 0xAF


= 0x9375Z, N = x† LU_TABLE is a label for anaddress in program memory

After InstructionWREG = 0x3CZ = 0N = 0

;; 1010 1111;; 1001 0011; ---- ----;;;; 0011 1100



XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f, d, a

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (WREG).XOR. (f) → destination



Description: Exclusive OR the contents of the WREG Register with Register 'f'.



Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Processdata

Write todestination

Example 1 XORWF REG1, 1, 1 ; Exclusive OR the value; in WREG with the value in; REG1

Before Instruction

REG1 = 0xAFWREG = 0xB5Z, N = x

; 1010 1111 (0xAF); 1011 0101 (0xB5); --------- ------

After Instruction

REG1 = 0x1AWREG = 0xB5Z = 0N = 0

; 0001 1010 (0x1A)



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Example 2 XORWF REG1, 0, 1 ; Exclusive OR the value; in WREG with the value in; REG1. Place result in; WREG

Before Instruction

REG1 = 0xAFWREG = 0xB5Z, N = x

; 1010 1111 (0xAF); 1011 0101 (0xB5); --------- ------

After Instruction

REG1 = 0xAFWREG = 0x1AZ = 0N = 0

;; 0001 1010 (0x1A)

Example 3 XORWF INDF0, 1, 1 ; Exclusive OR the value; in WREG with the value; pointed to by the FSR0; (FSR0H:FSR0L) Register

Before InstructionWREG = 0xB5FSR0 = 0x7C2Contents of Address

(FSR0) = 0xAFZ, N = x

After InstructionWREG = 0xB5FSR0 = 0x7C2Contents of Address

(FSR0) = 0x1AZ = 0N = 0

;; 1011 0101;;; 1010 1111;;;;;; 0001 1010;;

Example 4 XORWF REG1, 1, 0 ; Exclusive OR the value; in WREG with the value; at address REG1 in the; access bank. Place; result in access bank

Before InstructionWREG = 0xF8REG1 = 0x01Contents of Address

(REG1) in access bank= 0xAA

Z, N = xAfter Instruction

WREG = 0xF8REG1 = 0x01Contents of Address

(REG1) in access bank= 0x52

Z = 0N = 0

;; 1111 1000; 0000 0001;;; 1010 1010;;;;;;; 0101 0010;;



31.8 Design Tips

Question 1: I have seen references to “Read-Modify-Write” instructions in your datasheet, but I do not know what that is. Can you explain what it is and why Ineed to know this?

Answer 1:

An easy example of a Read-Modify-Write (or R-M-W) instruction is the bit clear instruction BCF.You might think that the processor just clears the bit, which on a port output pin would clear thepin. What actually happens is the whole port (or register) is first read, THEN the bit is cleared,then the new modified value is written back to the port (or register). Actually, any instruction thatdepends on a value currently in the register is going to be a Read-Modify-Write instruction. Thisincludes ADDWF, SUBWF, BCF, BSF, INCF, XORWF, etc... Instructions that do not dependon the current register value, like MOVWF, CLRF, and so on are not R-M-W instructions.

One situation where you would want to consider the affects of a R-M-W instruction is a port thatis continuously changed from input to output and back. For example, say you have TRISB set toall outputs, and write all ones to the PORTB Register, all of the PORTB pins will go high. Now,say you turn pin RB3 into an input, which happens to go low. A BCF PORTB,6 is then executedto drive pin RB6 low. If you then turn RB3 back into an output, it will now drive low, even thoughthe last value you put there was a one. What happened was that the BCF of the other pin (RB6)caused the whole port to be read, including the zero on RB3 when it was an input. Then, bit 6was changed as requested, but since RB3 was read as a zero, zero will also be placed back intothat port latch, overwriting the one that was there before. When the pin is turned back into anoutput, the new value was reflected. Try using the LATx register instead of the PORTx registerfor this read-modify-write operation.

Question 2: When I perform a BCF, other pins get cleared in the port. Why?

Answer 2:

There are a few possibilities, two are:

1. Another case where a R-M-W instruction may seem to change other pin values unexpect-edly can be illustrated as follows: Suppose you make PORTC all outputs and drive thepins low. On each of the port pins is an LED connected to ground, such that a high outputlights it. Across each LED is a 100 µF capacitor. Let's also suppose that the processor isrunning very fast, say 20 MHz. Now if you go down the port setting each pin in order; BSFPORTC,0 then BSF PORTC,1 then BSF PORTC,2 and so on, you may see that only thelast pin was set, and only the last LED actually turns on. This is because the capacitorstake a while to charge. As each pin was set, the pin before it was not charged yet and sowas read as a zero. This zero is written back out to the port latch (R-M-W, remember)which clears the bit you just tried to set the instruction before. This is usually only a con-cern at high speeds and for successive port operations, but it can happen, so take it intoconsideration.

2. If this is on a PIC16C7X device, you may not have configured the I/O pins properly in theADCON1 Register. If a pin is configured for analog input, any read of that pin will read azero, regardless of the voltage on the pin. This is an exception to the normal rule that thepin state is always read. You can still configure an analog pin as an output in the TRISRegister, and drive the pin high or low by writing to it, but you will always read a zero.Therefore, if you execute a Read-Modify-Write instruction (see previous question), all ana-log pins are read as zero, and those not directly modified by the instruction will be writtenback to the port latch as zero. A pin configured as analog is expected to have values thatmay be neither high nor low to a digital pin, or floating. Floating inputs on digital pins area no-no, and can lead to high current draw in the input buffer, so the input buffer is dis-abled.



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31.9 Related Application Notes

This section lists application notes that are related to this section of the manual. These applica-tion notes may not be written specifically for the Enhanced family (that is they may be written forthe Baseline, the Mid-Range, or High-End families), but the concepts are pertinent, and could beused (with modification and possible limitations). The current application notes related to theInstruction Set are:

Title Application Note #

No related Application Notes at this time.

Note: Please visit the Microchip Web site for additional software code examples. Thesecode examples are stand alone examples to assist in the understanding of thePIC18CXXX. The web address for these examples is:

http://www.microchip.com/10/faqs/codeex/



31.10 Revision History

Revision A

This is the initial released revision of the Enhanced MCU Instruction Set description.


39532 Instruction Set - University of Sydney

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