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• Paged Segmentation

Storage Management

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Recap…

In the last class, you have learnt:

Paging concepts and segmentation

Pages

Frames

Segments

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Objective

On completion of this period, you would be able

to know

• Paged Segmentation

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Segmentation with Paging – MULTICS

• The MULTICS system solved problems of external

fragmentation and lengthy search times by paging the

segments

• Paging eliminates external fragmentation

• Segment-table entry contains the base address of a page

table for that segment

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Segmentation with Paging – MULTICS

• In MULTICS logical address = 18-bit segment no. +

16-bit offset

• This scheme creates a 34-bit address space

• Each page in MULTICS consists of 1 K words

• So the segment offset is broken in to 6-bit page no. and

10-bit page offset

• Page no. indexes into the page table to give the frame

no.

• Frame no. is combined with the page offset to form a

physical address

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Segmentation with Paging – MULTICS

• Must have a separate page table for each segment

• The 18-bit segment no. could have up to 2,62,144

segments

• So the 18-bit segment no. is broken into 8-bit page no.

and 10-bit page offset

• The segment table is represented by a page table

consisting of up to 28 entries

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Segmentation with Paging – MULTICS

• The logical address in MULTICS is as follows

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Segment number Offset

S1 S2 d1 d2

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Figure:1

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• In fig1 s1 index into the page table of the segment table

• s2 is the displacement within the page of the segment

table

• d1 is a displacement in to the page table of the desired

segment

• d2 is the displacement into the page containing the word to

be accessed

Segmentation with Paging – MULTICS

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Segmentation with Paging – MULTICS

S1 S2 d1 d2

Logical address

s1

d1

d1

s2

Page table for segment

table Page of segment

table Page table for segment

Page of segment

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MULTICS Address Translation Scheme

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Segmentation with Paging – Intel 386

• As shown in the following slide, the Intel 386 uses

segmentation with paging for memory management with

a two-level paging scheme

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Internal architecture of paged segmentation

Paged Segmentation

 Combination of paging and

segmentation address =

frame at (page table base

for segment)

+ offset into page table

+ offset into memory

 Look at example of Intel

architecture

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Summary

In this class, you have learnt

• Paged Segmentation

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Frequently Asked Questions

• What is Paged Segmentation?

• Explain the Paged segmentation hardware with

a neat diagram ?

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Quiz

1. Page no. indexes into the page table to give the

a) Segmentationb) Frame no. C) None

2. MULTICS must have a separate page table for each a) Page offset b) Hole

c) segment d) None

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Quiz

3. ____________ scheme creates a 34-bit address

space

a) Page number

b) MULTICS

c) Compaction

d) None

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Quiz

4. The _________system solved problems of external fragmentation

a) External fragmentation

b) MULTICS

c) Compaction

d) None

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