36478230 Lecture1 3 CMOS NWELL and TwinTub Process
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Transcript of 36478230 Lecture1 3 CMOS NWELL and TwinTub Process
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27/12/2008VLSI DesignUNIT I : Introduction to IC Technology CMOS Inverter in n-well process
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Out LineCMOS Inverter in n-well processCMOS Inverter in Twin-Tub Process
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CMOS Technologiesn-well: The pMOS transistors are placed in the n-well and the nMOS transistors are created on the substrateP-well: The nMOS transistors are placed in the p-well and the pMOS transistors are created on the substrate
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1.WaferA bare Si wafer is chosenThe type will be n or p depending upon the technology
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2.Oxidation of WaferThe wafer is oxidised at a high temperatureThis must be patterned to define the n-well
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3.PhotoResist depositionThe photoresist is deposited throughout the waferThe PR has to be patterned to allow formation of the well
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4.n-well MaskThe PhotoResist is exposed through the n-well maskThe softened PhotoResist is is removed to expose the oxide
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5.Oxide EtchThe oxide is etched with HF acid where unprotected by PhotoResistThe wafer is now exposed to the n-well area
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6.PhotoResist removalThe remaining PR is removed via piranha etchThe well is ready to be formed
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7.n-well FormationThe diffusion process can make the the n-wellIon implantation can also form the same
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8.Oxide RemovalThe remaining oxide is stripped with HF acidThis leaves the exposed wafer with the n-well formed
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9.Gate FormationThe gates are made up of polysilicon over thinoxCVD is used to grow the poly (heavily doped) layer
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10.Poly PatterningThe wafer is now patterned with PhotoResist and the poly maskFinally this leaves the device gates
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11.Diffusion PatternAgain, a protective oxide is grown and PhotoResist depositedPhotoResist is patterned according to the diffusion mask
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12.Wafer Exposure for DiffusionThe protective oxide is etched awayThe wafer is exposed for S/D formation
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13.n-Diffusion RegionsThe n+ diffusion regions are formedPolysilicon blocks the channel area
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14.Self-Aligned Process
This is a self-aligned processS/D are automatically formed adjacent to the gate
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15.p-DiffusionThe p-diffusion mask is used nextThis completes creation of all active regions
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16.Field OxideThe field oxide is grown to insulate wafer and metalIt is patterned with the contact mask
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17.Metal FormationAl is sputtered over the entire area filling contact cuts tooMetal is patterned with the metal mask
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Inverter Cross-sectionTypically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
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Well and Substrate TapsSubstrate must be tied to GND, n-well to VDD Use heavily doped well and substrate contacts / taps
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Six masks n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
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CMOS Inverter in Twin-Tub Process
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Twin Tub ProcessesTwin-tub CMOS technology provides the basis for separate optimization of the p-type and n-type transistors.
One can optimize independently for threshold voltage, body effect, and the gain associated with n- and p-devices.
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Twin Tub Process: N-well / P-wellFirst place wells to provide properly-doped substrate for n-type, p-type transistors:
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Twin Tub Process: Polysilicon
Pattern polysilicon before diffusion regions:
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Twin Tub Process: N+/ P+ DiffusionAdd diffusions, performing self-masking:
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Start adding metal layers:Twin Tub Process: Contact / Via / Metal
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Twin-well CMOS process cross section
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Twin Tub CMOS Process Cross Section
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---Struggle gives Strength and Dignity....