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  • EE 439/539

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    Basic lithography process flow

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    Defects kill yield and drive up manufacturing cost, so defect inspection is vital in the Fab.

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    Crystal structure: How do atoms arrange themselves to form solids?

    Fundamental concepts and language Unit cells Crystal structures Face-centered cubic Body-centered cubic Hexagonal close-packed Close packed crystal structures Types of solids Single crystal Polycrystalline Amorphous

    Crystal structure: How do atoms arrange themselves to form solids?

    Fundamental concepts and language Unit cells Crystal structures Face-centered cubic Body-centered cubic Hexagonal close-packed Close packed crystal structures Types of solids Single crystal Polycrystalline Amorphous

    Types of Solids

    Crystalline material: atoms self-organize in a periodic array

    Single crystal: atoms are in a repeating or periodic array over the entire extent of the material

    Polycrystalline material: comprised of many small crystals or grains

    Amorphous: lacks a systematic atomic arrangement

    Crystal Properties of Solid

    Three types of solids, classified according to atomic arrangement

    (a) Crystalline (b) Amorphous (c) Polycrystalline

    Crystal grains of a ceramic material

    Crystalline materials: The constituent atoms arranged in a pattern that repeats itself periodically in 3-dimensions.

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    Crystal structure

    To discuss crystalline structures it is useful to consider atoms as being hard spheres with well-defined radii.

    In this hard-sphere model, the shortest distance between two like atoms is one diameter.

    We can also consider crystalline structure as a lattice of points at atom/sphere centers.

    Unit Cell

    The unit cell is the smallest structural unit or building block

    that can describe the crystal structure. Repetition of the

    unit cell generates the entire crystal.

    Example: 2D honeycomb net can be represented by translation of two adjacent atoms that form a

    unit cell for this 2D crystalline structure

    Different choices of unit cells possible, generally choose

    parallelepiped unit cell with highest level of symmetry

    Crystals are characterized by a unit cell which repeatsin the x, y, z directions.

    Face-Centered Cubic (FCC) Crystal Structure (I)

    Atoms are located at each of the corners and on the centers of all the faces of cubic unit cell

    Cu, Al, Ag, Au have this crystal structure

    Face-Centered Cubic Crystal Structure (II)

    The hard spheres or ion cores touch one another across a face diagonal the cube edge length, a= 2R2

    The coordination number, CN = the number of closest neighbors to which an atom is bonded = number of touching atoms, CN = 12

    Number of atoms per unit cell, n = 4. (For an atom that is shared with m adjacent unit cells, we only count a fraction of the atom, 1/m). In FCC unit cell we have: 6 face atoms shared by two cells: 6 x 1/2 = 3 8 corner atoms shared by eight cells: 8 x 1/8 = 1

    Atomic packing factor, APF = fraction of volume occupied by hard spheres = (Sum of atomic volumes)/(Volume of cell) = 0.74 (maximum possible)


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    Body-Centered Cubic Crystal Structure (II)

    The hard spheres touch one another along cube diagonal

    the cube edge length, a= 4R/3

    The coordination number, CN = 8

    Number of atoms per unit cell, n = 2

    Center atom (1) shared by no other cells: 1 x 1 = 1

    8 corner atoms shared by eight cells: 8 x 1/8 = 1

    Atomic packing factor, APF = 0.68

    Corner and center atoms are equivalent

    Hexagonal Close-Packed Crystal Structure (II)

    Unit cell has two lattice parameters a and c. Ideal ratio

    c/a = 1.633

    The coordination number, CN = 12 (same as in FCC)

    Number of atoms per unit cell, n = 6.

    3 mid-plane atoms shared by no other cells: 3 x 1 = 3

    12 hexagonal corner atoms shared by 6 cells: 12 x 1/6 = 2

    2 top/bottom plane center atoms shared by 2 cells: 2 x 1/2 = 1

    Atomic packing factor, APF = 0.74 (same as in FCC)

    All atoms are equivalent

    Semiconductor Lattice Structures

    Diamond and Zincblende Lattices

    Diamond latticeSi, Ge

    Zincblende latticeGaAs, InP, ZnSe

    Diamond lattice can be though of as an FCC structures with an extra atoms placed at a/4+b/4+c/4 from each of the FCC atoms

    The Zincblende lattice consist of a face centered cubic Bravais point lattice which contains four different atoms per lattice point. The distance between the two atoms equals one quarter of the body diagonal of the cube.

    Identification of a plan in a crystal

    Crystal Plans

    Miller Indices (hkl)11/2


    1 (210)

    z intercept at






    x intercept at a/2

    y intercept at bUnit cell


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    Defects in crystal Nothing in Nature is perfect, and crystals are no

    exception. Any real crystal contains defects, and these affect its properties in various ways.

    Defects in diamond alter the color;

    defects in semiconductors (of the right kind) allow them to be used to make devices;

    defects in metals alter their mechanical properties;

    defects affect thermal and electrical conductivity.

    Beneficial (crystal defects) Deep states are added to increase the resistively ( > 106 -cm)

    of semiconductor material used as substrates (semi-insulating material). The best examples are GaAs:Cr and InP:Fe.

    GaP is an efficient emitter of light. The red light is observed if the crystal contains oxygen together with Zn or Cd. The light is green if GaP is doped with nitrogen and the yellow emission from GaP is obtained by Mg-O doping.

    An increase of switching frequency in silicon junction is obtained by added Gold as deep levels.

    Sensitizing Centers have a large capture cross section for minority carrier , and hence magnitude of photoconductivity, is greatly increased.

    Thus deep levels are essential for the designing of devices and for their efficient performance.

    Deep level defects may efficiently reduce the minority carrier-lifetime. This is the main cause of the decrease in the energy conversion efficiency of solar cells.

    Deep levels may increase the leakage current of devices and alsodeteriorate the efficiency of photovoltaics.

    The performance of devices such as light-emitting diodes (LED ) isdegraded when the deep levels produce a parallel non-radiativerecombination path and act as a poison center.

    Deep level can also act as a Donor or acceptor like , Trap, Killercenter and scattering center.

    Thus reduction of deep levels is essential for the designing ofdevices and for their efficient performance.

    Detrimental (crystal defects) Point defects in semiconductors

    A point defect in a crystal is an entity that causes an interruption in the lattice periodicity. This occurs during due to following events:

    An atom is removed from its regular lattice site; the defect is a vacancy.

    An atom is in a site different from a regular lattice (substitutional) lattice site; the defect is an interstitial. An interstitial defect can be of the same species as the atoms of the lattice (it is an intrinsic defect, the self-interstitial) or of a different nature ( it is then an extrinsic defect, an interstitial impurity).

    An impurity occupies a substitutional site.

    Foreign interstitial atoms

    Self- interstitial




    Foreign interstitial atoms

    Self- interstitial




    Point defects play critical role in impurity diffusionand in ion implantation as well during space missions.

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    Dislocations Dislocations are line defects.

    Simplest to visualize is an edge dislocation

    think of an extra half-plane of atoms.

    Affects deformation properties to slide upper block over lower now

    only requires a line of bonds to break at a time, not a whole plane

    process of slip. Explains low yield strength of solids.

    Sources:i by stress due to temperature

    gradientii agglomeration

    Issues: anti-phase domain boundaries (APBs)

    1 m GaAs


    APBs reduce reliability/performancePlanar shunt/diffusion pathssurface roughness

    Zincblende III-V(2 types of atoms)

    Group IV(1 type of atom)


    = As= Ga= Ge or Si

    Electrically active Ga-Ga or As-As bonds

    APDs are a potential problem for any III-V/IV heteroepitaxy !!!

    Crystal Structure Mismatch

    Silicon Wafer Manufacture


    EpitaxialGrowth Oxidation



    Diffusion (Ion Implantation) Metallization

    Fabrication Process Flow for VLSI Devices

    Chip Fabrication Processes

    Silicon Wafer Preparation

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    Czochralski (CZ) Growth Method

    CZ is more common method to grow silicon crystal today because it is capable of producing large diameter crystals, from which large diameter wafer can be cut.

    Lecture # 4

    Modern CZ Crystal Growth

    The raw Si used for crystal growth is purified from SiO2 (sand) through refining, fractional distillation and CVD.

    The raw material contains < 1 ppb impurities except for O ( 1018cm-3) and C ( 1016 cm-3)

    Essentially all Si wafers used for ICs today come from Czochralskigrown crystals. Polysilicon material is melted, held at close to 1415 C, and a single crystal seed is used to start the crystal growth.

    Pull rate, melt temperature and rotation rate are all important control parameters.

    Drawback of the CZ method

    The only significant drawback to the CZ method is that the silicon is contained in liquid form in a crucible during growth and as a result, impurities from the crucible are incorporated.

    in the growing crystal. Oxygen and carbon are the two most significant contaminants.

    These impurities are not always a drawback, however. Oxygen in particular can be very useful in mechanically strengthening the silicon crystal and in providing a means for gettering other unwanted impurities during device fabrication.

    Vpmax= maximum crystal pull rate is inversely proportional to the square root of the crystal radius.

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    Modeling Dopant Behavior During CZ Crystal Growth

    Dopants are added to the melt to provide a controlled

    n or p doping level in the wafers.

    However, the dopantincorporation process is complicated by dopant segregation.

    Ko is the segregation coefficient.CSand CL are the impurity concentration just on the either side of the solid/ liquid interface.

    f= Vs/Vo, a fraction of melt that has solidified

    Doping concentration versus position along the grown CZ crystal for common dopants in silicon.

    Consider three cases: If K1if K~1

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    Curves for growth from the melt showing the doping concentration in a solid as a function of the fraction


    Example-1A ingot of single crystal silicon is pulled from the melt in a CZ process. The Si is boron doped. After the ingot is pulled , it is sliced into the wafers. The wafer taken from the top of the ingot has a boron concentration of 3 x 1015 cm-3. What would you expect for doping concentration of the wafer taken from the position corresponding to 90% of the initial charge solidified?

    Float Zone Growth Technique CZ wafers are contaminated by O2 and C

    from the crucible or graphite heaters.

    This limits the resistivity to ~ 20 cm, while intrinsic Si is 230 kcm.

    Extremely high purity Si wafers are made using float zone growth.

    FZ does not use a crucible or carbon heaters.

    * More expensive.

    * Carrier concentrations down to 10 11atoms/cm 3 have been achieved.

    * High purity needed for power thyristors and rectifiers.

    FZ Growth Considerations Segregation and evaporation of impurities in the melt zone help

    purify the Si further.

    * Recall, if k < 1, then more dopants/impurities in the liquid than in the solid.

    * Thus, the impurities generally stay in the melt zone, and don't solidify in the boule.

    * You can "purify" FZ wafers further by successively passing thecoil along the boule. The impurities then segregate towards the end of the boule.

    Thermal instability in the melt zone can cause microvariations in composition and doping.

    Difficult in making a uniform dopant concentration.

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    Crystal growth: Liquid Encapsulated Czochralski (LEC) technique

    The most common method for preparing GaAs wafer for IC application is the LEC technique.

    The growth of GaAs from the melt is significantly more difficult than the growth of Silicon. The main reason is the difference in the vapor pressure of the two materials.

    At the melting temperature of the GaAs (1238oC), the vapor pressure of gallium is less than 0.001 atm, while the vapor pressure of arsenic is 104 larger.

    Liquid Encapsulated Czochralski (LEC) technique

    GaAS wafers are round and are limited to about 4" diameter because:

    GaAs has lower thermal conductivity than Si (0.07 vs. 0.21 W/cmK).

    GaAs has a lower shear stress, and so heavy boules produce more defects.

    Using LEC, GaAs can be made semi-insulating (100 M cm).

    Typically used for electronic devices

    Disadvantage of LEC technique

    The dislocation density in GaAs is higher than in Si and is of great concern.

    Under the same conditions, GaAs is more susceptible to dislocation formation for two reason:

    First, the bond in GaAs are not as stronger as in Si, so dislocation form more easily. Second, the thermal conductivity of Si is about three-fold that of GaAs. Therefore, it is more difficult to reduce thermal gradients in GaAs crystals. As a result a GaAs boule is not able to dissipate the latent heat of fusion as rapidly as a silicon boule.

    Because of the difference in fundamental properties defect densities in LEC grown GaAs is many order of magnitude larger than CZ grown Si.

    It has also been suggested that while growing replacement of a Ga atom with much larger indium atom creates a strain field that traps dislocations

    Bridgman Growth of GaAs

    About of GaAs market is made this way.

    Lower dislocation density than LEC and is commonly used to fabricate optoelectronic devices (lasers).

    Wafers are D shaped and are small --> typically 1" - 2" in diameter.

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    Future Trends in Technologies Silicon will be the dominant material used for ICs for as far into the future as

    we can reliably see. There will be increasing demand for larger diameter wafers since manufacturing

    economics favor larger wafers and the resulting larger numbers of chips they can carry.

    It is also easy to predict that as device dimensions continue to shrink, in-creasing demands will be made on wafer suppliers to reduce impurity levels in the starting wafers or to tightly control these levels as in the case of oxygen.

    The recently introduced MCZ should help in controlling wafer properties. One of the change that may impact starting wafer in the future is the current

    interest in Silicon On Insulator (SOI), which result a epitaxial layer. The advantages of such a structure come about because the devices

    are built in a thin silicon film on an insulator (SiO2 in this case). This can reduce parasitic capacitances and as a result, speed up circuits.

    This process is know as SIMOX for separation by implanted oxygen BESOI for Bonded and etch back technology

    Clean Room Clean Room

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    Typical a person emit 5-10 million particlePer minute.Most modern IC plantsUse robots for wafer Handling.


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    Standard RCA cleaning procedureGettering

    Gettering is a favorable mechanism observed in the presence of oxygen at concentration near 1017 cm-3.

    When, prior to a device processing a silicon wafer is heated to ~1000oC in N2 atmosphere, most of the oxygen near the surface of the wafer isremoved by the atmosphere. Deep in the bulk of crystal , however, oxygen remains at high concentration and precipitates as complexes and acts as a sink that attracts impurities such as heavy metals.

    Gettring can be also achieved by intentionally damage the back of the wafer and then subjecting it to high temperature. The damage region act as sink for impurities.

    In GaAs replacement of gallium atom with a much larger indium atom creates a strain field that traps the dislocations, effectively getteringthem from any active layer grown on top of the wafer.

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    Intrinsic gettering

    Generally, particlesOn the order of the Technology minimumFeatures size or Large will causeDefect.

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    A light sensitive photoresist is spun onto the wafer forming a thin layer on the surface. The resist is then selectively exposed by shining light through a mask which contains the pattern information for the particular being fabricated. The resist is then developed which completes the pattern transfer from the mask to the wafer.

    Lithography comes from two Greek words, lithos which means stone and graphein which means write. writing a pattern on stone

    Lithography Lithography is the most complicated, expensive, and critical

    process of modern IC manufacturing.

    Lithography transforms complex circuit diagrams into pattern which are define on the wafer in a succession of exposure and processing steps to form a number of superimposed layers of insulator, conductor, and semiconductors materials.

    Typically 8-25 lithography steps and several hundred processing steps between exposure are required to fabricate a packed IC.

    The minimum feature size i. e., the minimum line width or line to line separation that can be printed on the surface, control the number of circuits that can be placed on the chip and has a direct impact on circuit speed. The evolution of IC is thereforeclosely linked to the evolution of lithographic tools.

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    reviewBasic lithography process flow-chapter-5

    Ten Basic Steps of


    1. Surface Preparation2. Photoresist Application3. Soft Bake4. Align & Expose*

    5. Develop6. Hard Bake7. Inspection8. Etch9. Resist Strip10. Final Inspection

    * Some processes may include a Post-exposure Bake

    Introduction to the Lithography Process Lithography Overview

    While the lithography concept is very simple, the actual implementation is very complex, because of the following demands placed on this process:

    Resolution - demand for smaller device structures

    Exposure field - chip size and need to expose at least one full chip (8 wafer)

    Placement accuracy -alignment with respect to the existing pattern

    Throughput -manufacturing cost

    Reduction of defects density - yield loss

    0.7X in linear dimension every 3 years. Placement accuracy 1/3 of feature size. 35% of total wafer manufacturing costs forlithography. Note the ???. This represents the single biggestuncertainty about the future of the roadmap.

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    Wafer Exposure Systems

    Contact printing is capable of high resolution but has unacceptable defect densities. Inexpensive, diffraction effects are minimize. Proximity printing cannot easily print features below a few m (except for x-ray systems). Poor resolution due to diffraction effects, required 1 X mask. Projection printing provides high resolution and low defect densities and \dominates today. Typical projection systems use reduction optics (2X - 5X), step and repeat or step and scan mechanical systems, print 50 wafers/hour and cost $5 - 10M.

    electronic interface computer

    Stepper E-Beam Lithography

    Wafer Exposure Systems Photomask A mask for optical lithography consists of a

    transparent plate called blank, covered with a patterned film of opaque material.

    The blank is made of soda lime, borosilicate glass, or fused quartz. The advantage of the quartz is that it is transparent to deep UV (365nm) and has a very low thermal expansion coefficient.

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    Three ways to improve resolution Wmin (also R is used in the text)

    We will derive this expression and analyze all the different means of reducing Wmin(alsoR)

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    An approach to improve resolution

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    Pattern Generation using CAD tools

    In a typical CAD system pattern is designed with a light pen on a cathode ray tube. The output of the CAD system is usually in the form of a binary data.

    The data are first translated into machine language and then transmitted to an optical, electron beam, or laser system and finally design shapes on the mask.

    A laser pattern generation system

    Projection Systems ( Fraunhofer Diffraction)

    These are the dominant systems in use today.

    Performance is usually described in terms of resolution depth of focus field of view modulation transfer function alignment accuracy throughput




    dfR ===

    Where n has been included for generality and is the index of refraction of the material between the object and the lens and R is the minimum feature size.

    Two small adjacent featureson a mask

    How close togethercan they be and still be resolved in theimage plan?

    = K1NA


    NA is the ability ofLens to gather light.

    The formula suggestsThat decreasing the and /or increasing the NA are ways to printa smaller image size.

    Depth of the focus (DOF) Aside from the difficulty of large

    lenses, there is also a significant draw back to using higher numerical aperture (NA), of a lens. If is the axis path length difference at the limit of the focus, then the path length difference for a ray from the edge of the entrance aperture is simply cos. The Raleigh criteria for depth of the focus is simply that these two lengths not differ by more than /4 i. e.,


















    k2 is usually experimentally determined.

    (is a measure of how much of the diffracted light the lens accepts and image)

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    Photolithography-DOF The defocus tolerance (DOF)

    Much bigger issue in miniaturization science than in ICs

    A small aperture was used to ensure the foreground stones were as sharp as the ones in the distance.

    What you need here is a use a telephoto lens at its widest aperture.


    This depth of focus is on the same order as the resist layer thickness itself.

    Modulation Transfer Function (MTF)

    MTF is a measure of the optical contrast in the aerial image by the exposure system. The higher the MTF the better the optical contrast. MTF of an image can be defined as

    MTF increases with decreasing wavelength.

    For large features size MTF is unity. As the features size decreases diffraction effects cause the MTF degrade to finally reached zero when the features are so closely spaced that there is no remaining contrast in the image.





    Partially dark

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    Spatial Coherence

    A useful definition of the spatial coherence of practical light sources for lithography is simply

    S= light source diameter condensed lens diameter

    Practical light sources are not point sources. Therefore, the light striking the mask will not be plane waves.

    Typically, S ~ 0.5 to 0.7 in modern systems.

    Summary of wafer printing systems

    In the contact printing system , a very high resolution image is produced i. e., minimum diffraction effect.

    In a proximity printing system, the resolution degrade because of near field Fresnel diffraction effects.

    In the projection printing system , diffraction effects are minimized by placing a lens between mask and the wafer. And focus the aperture on the wafer.

    It is clear from the figure that the resolution of the proximity system is inferior to both of the other systems. This is why projection systems are used in manufacturing today.

    Discuss implications of following calculation for the technologist that mustmanufacture transistors with 0.5 m features.

    R RExample


    Photoresist Composition

    The most commonly used positive resist consist of diazonaphtoquinone (DQ), which is the photoactive compound (PAC), and novolac (N), a matrix material called resin. Upon absorption of UV light, the PAC undergoes a structural transformation which is followed by reaction with water to form a base soluble carboxylic acid, which is readily soluble in basic developer (KOH, NAOH, TMAH etc.)

    The base resin is novolaca long chain polymerconsisting of hydrocarbon rings with 2 methyl groupsand 1 OH group attached.

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    Basic Properties of Resists: Contrast Curves

    Two basic parameters are used to describe resist properties, contrast and the critical modulation transfer function or CMTF.

    Contrast is a measure of the ability of a resist to distinguish between light and dark portion of the mask defined as ,


    10 of DD=The higher the contrast, the sharper the line edge.

    Resist with high contrastCan actually sharpen up a pooraerial image.


    Find the parameter for the i Positive photoresist Df=90mJ/cm2

    and Do=45 mJ/cm2

    ii Negative photoresist Df=7mJ/cm2



    10 of DD=

    Critical modulation transfer function (CMTF)

    By analogy to the MTF (dark versus light intensities in the arialimage produced by the exposure system) defined earlier for optical systems, the CMTF for resists is defined as

    In terms of the contrast, can be written as,

    In general CMTF < MTF is required for the resist to resolve the aerial image.

    There are often a number of additional issues that arise in exposing resist.












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    A 0.6 mm thick layer of a particular photoresist has D0=40mJ/cm2 and D100 =85mj/cm2. (a) Calculate the resist contrast (b) Calculate CMTF If resist thickness is cut in half, D100 reduced to 70mJ/cm2 while D0 is Unchanged . What is the highest contrast possible in this resist without changing theResist processing?

    Resolution enhancement techniques: Mask engineering or wavefront

    engineering Sharp features are lost because higher frequencies are lost due

    to diffraction. These effects are calculable and can be compensated for.

    The resolution of an optical system can be improved by increasing the numerical aperture and reducing the wavelength.

    Increasing the numerical aperture and reducing the wavelength, however, decrease the depth of the focus. Further reduction in the wavelength requires the development of new optical systems and resist compositions.

    It is known that in the sub 0.5m range, a perfect image on the mask can, from diffraction effect, result in a distorted pattern in the resist.

    OPC mask attempt to reverse the situation by having a distorted image on the mask that is design to, produce a perfect image on the resist. A computer is used to analyze exposure process conditions.

    However, the use of OPC are so difficult that they are unlikely to be implemented on a large scale in the near future.

    Resolution enhancement techniques: Mask engineering

    (1) Optical proximity corrections (OPC)

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    Optical Proximity Correction (OPC) can be used to compensate somewhat for diffraction effects.

    Sharp features are lost because higher spatial frequencies are lost due to diffraction. These effects can be calculated and can be compensated for. This improves the resolution by decreasing k1.

    Photolithography- OPCResolution enhancement techniques:

    (2) Optical Phase Shifting

    Diffraction problem could be more pronounced as two mask patterns get closer together

    OPS uses phase shifting to sharpen printed images.

    These techniques can allow existing exposure tools to be used in manufacturing at least one more technology generation.

    Unresolved pattern

    When the angle of illumination and the angle of diffractionare well matched, the amount of light diffracted can be enhanced and the contrast of the image improved.

    (3) Off-axis Illumination technique

    Photolithography-NA At the same time that exposure

    wavelengths have been reduced, improvements in lens design has led to improvements in the NA of exposure systems lens, see figure . In the mid eighties an NA value of approximately 0.4 was typical, today 248nm exposure systems are available with an NA greater than 0.8. The physical limit to NA for exposure systems using air as a medium between the lens and the wafer is 1, the practical limit is somewhere around 0.9, with recent reports suggesting that an NA as high as 0.93 may be possible for ArF systems in the future .

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    The third element in the Rayleigh equation is k1. k1 is a complex factor of several variables in the photolithography process such as the quality of the photoresist and the use of resolution enhancement techniques such as phase shift masks, off-axis illumination (OAI) and optical proximity correction (OPC). While exposure wavelengths have been falling and NA rising, k1 has been falling as well, see figure . The practical lower limit for k1 is thought to be about 0.25.

    Photolithography- k1 From the discussion to this point, the resolution limit for

    193nm exposure systems may be calculated using the Rayleigh equation with, l = 193nm, NA = 0.93 and k1 = 0.25 or

    From the above a highly optimized ArF exposure system has an absolute maximum resolution of 52nm, sufficient for 65nm linewidths forecast in 2005, but not capable of meeting the 45nm linewidths forecast in 2007.

    Photolithography-Immersion Litho

    NA is determined by the acceptance angle of the lens and the index of refraction of the medium surrounding the lens. The physical limit for an air based system is clear, but what if a medium with a higher index of refraction is substituted for air? Microscopy has for years used oil between the lens and the sample being viewed for resolution enhancement and it is somewhat surprising that the semiconductor industry has taken this long to seriously consider the merits of replacing air with an alternative.

    Photolithography-Immersion litho

    Photolithography-Immersion Litho

    The medium between the lens and the wafer being exposed needs tohave an index of refraction >1, have low optical absorption at 193nm, be compatible with photoresist and the lens material, be uniform and non-contaminating. Surprisingly, ultrapure water may meet all of these requirements. Water has an index of refraction n = 1.47, absorption of

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    Next Generation lithographic methods

    Why is optical lithography so widely used and what makes it such a promising method?

    It has high throughput, good resolution, low cost and ease in operation. However, due to deep submicron IC process requirements, optical

    lithography has limitation that have not yet been solved. Therefore, it is required to find alternatives to optical lithography. The

    possible promising techniques are: Electron beam lithography Extreme Ultraviolet Lithography X-ray lithography Ion beam lithography

    Schematic of an electron beam

    lithography machine.

    Advantages:Generation of submicronResist geometriesGreater depth of focusDirect patterning on a Semiconductor withoutUsing a mask.Currently EBL is the Technology of choice forMask generation due to Its ability to accurately define small features.

    Disadvantage:Low throughput

    Next Generation Lithography: E-Beam

    oDiffraction is not a limitation on resolution ( < 1 for 10-50 keV electrons)oResolution depends on electron scattering and beam optics the size of the beam, can reach ~ 5 nmoTwo modes of operation:

    oDirect writing with narrow beam oElectron projection lithography using a mask :EPL

    oIssues:oThroughput of direct writing is very low : research tool or low pattern density manufacturingoProjection stepper (EPL) is in development stage only (primarily by Nikon).oMask making is the biggest challenge for the projection methodoBack-scattering and second electron result in proximity effect reduce resolution with dense patterns there is also the proximity effectoOperates in high vacuum (10-6 10-10 torr) slow and expensive

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    The advantages of electron lithography are: (1) Generation of micron and submicron resist geometries (2) Highly automated and precisely controlled operation (3) Greater depth of focus (4) Direct patterning without a mask

    Next Generation Lithography: E-Beam

    The biggest disadvantage of electron lithography is its low throughput (approximately 5 wafers / hour at less than 0.1 resolution). Therefore, electron lithography is primarily used in the production of photomasksand in situations that require small number of custom circuits.

    Issue associated with EBL: Proximity effect

    In EBL the resolution is not limited by diffraction

    In EBL backscatteringcauses the electron beam to broaden and expose a large volume of resist then expected.

    The proximity effect places a limit on the minimum spacing between pattern feature.

    SCALPEL (SCattering with Angular Limitation Projection Electron-beam Lithography)

    EPL is e-baem with a mask for high-throughput The aspect of SCALPEL which differentiates it

    from previous attempts at projection electron-beam lithography is the mask. This consists of a low atomic number membrane covered with a layer of a high atomic number material: the pattern is delineated in the latter. While the mask is almost completely electron-transparent at the energies used (100 keV), contrast is generated by utilizing the difference in electron scattering characteristics between the membrane and patterned materials. The membrane scatters electrons weakly and to small angles, while the pattern layer scatters them strongly and to high angles.

    An aperture in the back-focal (pupil) plane of the projection optics blocks the strongly scattered electrons, forming a high contrast aerial image at the wafer plane

    Uses very short 13.4 nm light

    All reflective optics (at this wavelength all materials absorb!)

    Uses reduction optics (4 X) Step and scan printing Optical tricks seen before all

    apply: off axis illumination (OAI), phase shift masks and OPC

    Vacuum operation Laser plasma source Very expensive system

    Next Generation Lithography : EUV

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    Challenges:EUV is strongly absorbed In all materials.Lithography process must be performed in vacuumMask blank must also be multilayer coated to minimizeIts reflection.

    An extreme ultraviolet (EUV) lithography system.

    Schematic representation of a proximity x-ray lithography system.


    Problems:Masks are the most Difficult and criticalElement of an XRL systemlacking of photoresist1:1 printingHigh energy x-ray destroy conventional optics

    Advantages:Low diffractionShorter exposure timeScattering is minimumX rays pass through spots

    Although all non optical lithography techniques have 100 nm or better resolution , each process has its own limitations:Proximity effect in electron beam lithographyMask blank production difficulties in EUV lithographyMask fabrication complexity in X-ray lithographyRandom space charge effect in ion beam lithography

    Thermal Oxidation-Chapter 6Basic Concepts

    SiO2 and the Si/SiO2 interface are the principal reasons for silicons dominance in the IC industry. SiO2 : Easily selectively etched using lithography. Masks most common impurities (B, P, As, Sb). Excellent insulator ( > > 1016 cm, Eg > 9eV). High breakdown field (10 7 Vcm -1 ) Excellent junction passivation. Stable bulk electrical properties. Stable and reproducible interface with Si.

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    Uses of SiO2 in Silicon Technology Silicon Oxidation System

    Oxidation systems are the simplest types of semiconductor processingEquipment. However, the effect to continue decreasing the size of VLSI (MOS devices are

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    Physical measurements techniques(destructive)

    Etching (HF for SiO2 layer), AFM, STM, SEM, TEM(resolution below 10nm).

    All of these techniques required sample preparation and as a result are not well suited to in process measurements on a manufacturing line. They also provide information on film thickness.

    SEM image

    TEM image

    Example In an experimental structure in the following figure, a

    phosphorus N+ region is formed by ion implantation using a 50-nm Sio2 mask. A metal electrode is then formed as shown and a CV measurement is made in the region outside the N+ region. The measurement gives C = Cox for all values of applied voltage as shown. Explain what might have gone wrong in this experiment. That is explain why no surface inversion is observed in the CV measurement.

    Linear Parabolic Model (Deal Grove model)

    The basic model for oxidation was developed in 1965 by Deal and Grove. It has been assumed that an oxide of some

    thickness xi is already present on the Si surface. It has also been assume that three steps are necessary for oxidation on the silicon surface although only two of them are important.

    F1 F2 F3

    Si+O2SiO2 Si+2H2OSiO2+2H2

    Deal-Grove relation Under steady state conditions these three flows must balance, F1 = F2 = F3. In

    order to find a growth rate we need Henrys law , which says that concentration of an absorbed species at the surface of a solid is proportional to the partial pressure of the species in the gas just above the solid:

    CO=HPS = HkTCS (7) so combining equations (1-7) we can write as

    Where h=hG/HkT The growth rate can be determined by following equation

    Where N1 number of molecule of oxygen per unit volume of SiO2

    By using boundary (at time =0, xi=x0)- condition the solution of above differential equation is written as


    DAwhere 112







    )(02 +=+ tBAxxo













    DHPB G=B

    Axx ii +=2

    The parameters A and B are proportional to diffusitivity and follow an Arrenhious function. the shift in time to account for initial oxide thickness.


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    The Linear and Parabolic rate coefficients(two limiting forms of Deal Grove model)

    Case I: For very short oxidation time (thin oxides layer), the rate equation reduced to the linear form

    Case II: when t>>, the oxide is sufficiently thick, the rate equation reduced to the simple parabolic expression,

    B/A and B are often termed the linear and parabolic rate coefficients respectively because of the xo and x2o terms in which they appear. Physically, they represent the contribution of fluxes F3 (interface reaction) and F2 (oxidant diffusion), respectively. SiO2 growth on a bare Si wafer usually starts out with a linear xx versus x, which become parabolic as the oxide thickens.

    In fact, B and B/A are normally determine experimentally by extracting them from growth rate. The reason for taking this approach is simply that we usually do not know all the parameters in Grove-Deal model equations. Ks (interface reaction rate constant) is particular contains a lot of hidden physics associate with the interface reaction. What we do, however, is compare experimental values of B and B/A with the model equations. To test the reasonableness of the liner parabolic model.


    )( 0202 ++=++=+ t



    BxtBAxx oo O


    xBxo ++=+ )()(



    Analysis of the rate constants (B and B/A)

    Experimentally, it has been found that both B and B/A are well describe by Arrheniousexpressions of the form

    B=C1exp(-E1/kT) B/A= C2exp(-E2/kT) Where E 1 and E2 are the activation energies associated with the physical process that B

    and B/A represent; C1 and C2 are the preexponential constant. The physical mechanism responsible for E1 might be the oxidant diffusion through the

    Sio2. The physical origin of E2 is likely connected with the interface reaction rate constant Ks.

    Ks really represent the number of process occurring at the interface.


    9 BAxx ii +=



    2 +=+ tBAxxo

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    A p-type Si wafer with a resistivity of 10cm is placed in a wet oxygen systemto grow a field oxide of 0.45145m at a 1050C. Determine the time require to Grow the oxide.

    Problems in Deal Grove model: Initial Oxidation Stage

    A major problem with the Deal Grove model was recognized when it was first proposed - it does not correctly model thin O2 growth kinetics (0-30 nm).

    Experimentally dry O2 oxides grow much faster for 200 than Deal Grove predicts.

    MANY suggestions have been made in the literature about why. None have been widely accepted.

    Since modern technologies emphasize this range of oxide thickness for MOSFETs and capacitors, intense work has been done to model the initial rapid stage of oxidation.According to the deal grove model the oxidation rate should apporch at constant value i. e.



    tLim =


    Instead, the oxidation rate increasedby a factor of 4 or more.

    + )( tABxo

    Effect of stress on Oxidation Kinetics

    Stress is created by two-dimensional growth of oxide and the resulting volume expansion of the oxidize region.

    As the oxide grow the newly formed oxide pushes out the old oxide which rearranges itself through viscous flow.

    Stress occurs typically on curved surfaces, as illustrated for the inside and outside corners of a trench in Si.

    2D SiO2 Growth Kinetics

    Several physical mechanisms are important in explaining these results: Crystal orientation 2D oxidant diffusion Stress due to volume expansion To model the stress effects, Kao et. al. suggested modifying the Deal Grove parameters.

    These models have been implemented in modernprocess simulators and allow them to predict shapesand stress levels for VLSI structures.

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    Local Oxidation of Silicon (LOCOS)

    The ability to selectively oxidize the silicon surface has become very important in high density bipolar and MOS processes.

    The technique utilize for localized oxidation of silicon are generally refereed to as LOCOS processes. LOCOS is widely used to isolate region in Si, called active area, , where devices are constructed.

    In the figure the role of pad oxide is to relieve the stress transmitted to silicon by the nitride at high temperature. Typical LOCOS thicknesses are in the range of 250-800nm.

    The penetration of the oxide underneath the nitride results in a birds beakstructure, which loss the geometry so minimization of the birds beakphenomenon is control in VLSI structure, an important goal in VLSI process design.

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    Chapter 7: Dopant Diffusion High temperature diffusion has historically been one

    of the most important processing steps used in fabrication of monolithic integrated circuits (IC).

    Today, diffusion is used in the formation of deep layers exceeding few tenths of micron in depth. Therefore we must study diffusion process in order to understand its limitation and various problems associated with redistribution of impurities.

    In this chapter we will discuss and explore theoretical and practical aspects of the diffusion process.

    Diffusion: Basic Concepts Diffusion is the redistribution of atoms from

    regions of high concentration of mobile species to regions of low concentration.

    It occurs at all temperatures, but the diffusivity has an exponential dependence on T.

    Diffusivity, a property that describe the ease with which they move through the medium.

    The driving force of diffusion is the concentration gradient.

    Dopant Solid Solubility

    Dopants are soluble in bulk silicon up to a maximum value before they precipitate into another phase.

    Discrepancy in dopant concentration: an example

    Dopants may have an electrical solubility that isdifferent than the solid solubility.

    Two electrons forma dangling bond

    And do not contribute free electrons to the crystal

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    Ficks first law diffusion equation (cont.)

    Ficks first law is mathematically described by the equation,

    Proportionality constant is the diffusivity D in cm 2 sec -1 . D is related to atomic hops over an energy barrier (formation and migration of mobile species) and is exponentially activated. D is isotropic in the silicon lattice.

    Negative sign indicates that the flow is down the concentration gradient.


    = ),( xtxCDJ

    = ),(

    Analytic Solutions of Ficks Laws: Limited Source:

    Consider a fixed dose Q, introduced as a delta function at the origin.

    The solution that satisfies Ficks second law is

    Important consequences:1. Dose Q remains constant2. Peak concentration

    decreases as 1/ t3. Diffusion distance from

    origin increases as 2 Dt

    Introduced a spike of dopant in the middle of Lightly doped region.

    The factor 2Dt is often termed as the Diffusion length (how far the dopant has diffused?).

    Analytic Solutions of Ficks Laws: Limitted Source Near A Surface

    This solution is also called drive in diffusion. In this case initial amount of impurity QT is introduced into the wafer subject the boundary condition that QT is fixed.

    Analytic Solutions of Ficks Laws: constant Source Near A Surface

    This condition is correspond to putting a heavily doped epitaxiallayer on a lightly doped wafer.

    The solution which satisfies Ficks law is given by ,

    Important consequences of Error function solution:

    Symmetry about mid-point allows solution for constant surface concentration to be derived.

    Dose beyond x=0 continues to increase with annealing time.

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    Intrinsic diffusion coefficientsIntrinsic dopant diffusion coefficients

    are found to be of the form,

    Where is the activation energy of the neutral vacancy and Do is the measure of the frequency with which an atom attempts to make a jump over the barrier (1013-1014Hz).

    The exponential term which represent the probability that an atom will have an energy equal to or in access of the activation energy.


    Note the "slow" and "fast" diffusers. Solubility is also an issue in choosing a dopant for a particular application.

    3.2 Atomic Scale Diffusion: Fairs vacancy model

    Many effects that are very important experimentally, cannot be explained by the macroscopic models discussed so far. Thus we need to look deeper at atomic scale effects.

    In the vacancy model, vacancy can be neutral (Vo), positively charged by donating an electron (V+), double positively charged by donating two electrons (V++), negatively charged by accepting an electron (V-), double negatively charged by accepting two electrons (V=). However, the probability for high level charged is very low. Due to these probabilities, the most general expression for the diffusion coefficient in the vacancy model is given by,

    ........... 22












    ++= +

    For substrate with excess free Electron (n-type), positive charge term can be neglected and for substratewith excess free holes(p-type) the negaticharge terms can be neglected.

    Concentration Dependent Diffusivity

    ........... 22












    ++= +

    The dash line show the erfc profiles. The solid lines are numerical simulation which agree with experimental results

    At high doping concentrations, the diffusivityappears to increase. Fick's equation must then be solved numerically since D constant.

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    ........... 22












    ++= +


    o oaeDD /=

    The surface of a silicon wafer has a region that is uniformly doped with boron at the concentration of 1018 cm-3. This layer is 20 angstroms thick (1 angstrom = 10-4 micrometer = 10-8 cm). The entire wafer, including this region, is uniformly doped with arsenic at a concentration of 1015cm-3. The surface of the wafer is sealed and it is heated at 1000 degrees Celsius for 30 minutes. Assume intrinsic diffusion.

    a) Find the concentration of boron at the surface after the anneal. b) Find the junction depth (boron concentration equal to arsenic concentration) after the

    anneal. Solution: 3.6a) This is a drive-in diffusion

















    At the surface of the wafer, x=0 31610*8.2),0( == cm

    DtQtC T




    TJ 15.0ln*4 =


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    Correction to simple theory: Electric field effect

    When the doping is higher than ni at the diffusion temperature, -field effects become important.

    The origin of the field comes from the higher mobility of the electrons and holes compared to dopant atoms.

    xChDJ += )1(

    h is the field enhancement term. When C>>nih2

    A silicon wafer was doped in a 1000oC predeposition diffusion with phosphorus to its solid solubility limit. The process time was 20 min. After the predeposition, the surface of the silicon was sealed and 1100oC drive in was done. Find the drive in time necessary to obtained a junction depth of 4.0 micron. Assume a substrate concentration of 1017cm-3. What is the surface concentration after the drive in?

    (ref table 3.2)


    (predeposition flux)


    Ref fig 3.7

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    Diffusion vs ion implantationIon implantation became the dominant doping method by the mid 1970sand Continues to be so today.

    The new emerging method for dopant diffusion is rapid thermal processing

    Comparison of (a) diffusion and (b) ion-implantation techniques for the selective introduction of dopants into the

    semiconductor substrate.

    Chapter-7: Diffusion


    Five problems in thermal diffusion process (chapter -7)

    Lateral diffusion Ultra thin junction Poor doping control Surface contamination interference Dislocation generation

    Ion Implantation drawbacks

    There are also some significant disadvantages:

    Damage to crystal Anomalous transient enhanced

    diffusion (TED) upon annealing the damage

    Charging of insulating layers Channeling


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    Example : Mass Resolution

    += sincos121





    Implant Profiles

    Ion implantation is a random process.

    High energy ions (1-1000keV) bombard the substrate and lose energy through nuclear collisions and electronic drag forces.


    Range distribution

    The average depth below the surface an ion penetrate is called the mean projected rangeRP. This depth is typically shorter than the actual distance the ion travels.

    Some ion stop at a depth smaller than RP, and other at a depth larger than RP. The distribution about RP can be approximated by a Gaussian with a standard deviation, orstraggle, RP can be estimated by,

    Where Mi and Mt are the masses for incident and target ion

    The implanted ion also scatter laterally around the impact point, which can also approximated by Gaussian distribution with transverse straggle, RT.

    + titi

    pp MMMM


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    Mathematical model for ion implantation

    Profiles can often be described by a Gaussian

    distribution, with a projected range and standard deviation. (200KeV implants shown in the Fig.)

    = p


    p RRx

    RxN 2





    Where RP is the project range and RP is the standard deviation of the projectedrange and is dose.The total number of ion implanted (dose) can be also written as

    This provide a useful relationship betweenThe dose and the peak concentration of the Implant.

    ppCR= 2CP is the peak concentration.


    Fig. 6.20el

    Range and implanted struggle (RP)

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    A 30-KeV implant of B11is done into a bare siliconThe dose is 1012cm-2(a) What is the depth of peakof implanted profile?(b) What is the concentrationAt this depth? what is the concentrationat depth of 3000Ao?

    (d) The measured concentrationis found to be an order of magnitudelarger than the value predicted in part

    although the profile agrees with answers (a) and (b). Give a possible

    explanation, assuming that the measured value is correct.


    Lateral Spread of Implanted Ions When a mask is used to implant

    selective regions of the wafer, there is also lateral scattering perpendicular to the path of the incident beam that causes a transverse spread, RT, of implanted ion from the mask edge.

    As the dimension of the modern MOS devices shrink, RT. becomes very important.

    Deviation from the Gaussian Theory (Skewness) When light ions such as boron,

    impact atoms of the silicon target, they experience a relatively large amount of backward scattering and fill in the distribution on the front side of the peak.

    Heavy atoms such as antimony, experience a large amount of forward scattering and tend to fill in the profile on the substrate side of the peak.

    The different skewnress can be visualized by thinking of forward momentum.

    A number of model has been proposed to explain this behavior. The most common one is known as Pearson Type IV.

    Implants in Real Silicon - Channeling

    At least until it is damaged by the implant, Si is a crystalline material.

    Channeling can produce unexpectedly deep


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    Minimizing channeling. (a) Implantation through an amorphous oxide layer.

    (b) Misorientation of the beam direction to all crystal axes. (c) Pre-damage on the crystal surfaces.

    Modeling of range statistics: Energy loss mechanism

    The total energy loss during an ion trajectory is given by the sum of nuclear and electronic losses.

    The stopping power of the target is the loss of energy per unit distance dE/dx, define as,

    Where E is the ion energy Sn the nuclear stopping power Se the electronic stopping power N, the density of the atom in the Target material. R is the ion range.

    Nuclear Stopping If the ion and the target atoms

    were bare nuclei, the scattering potential would be given by simple Coulomb potential. Because of electron which surround the target nucleus, the full effect of the positive core potential is screened from the incoming ion and is given by modified Thomas-Fermi model of the atom,

    Where a is some screening distance.

    The energy loss of the incident ion per unitLength Sn depends on the ion energy. The nuclear energy loss is small at veryhigh energies, because fast particle have

    Less interaction time with the scattering nucleus.Thus the nuclear energy loss tends to dominant to wards the end of the range when ion has lost much of its energyand where nuclear collisions produced most

    Of the damage.

    Where m1, Z1 refer to the ion and m2, Z2=substrate atom mass and atomic number

    Electron Stopping Drag force caused by charged

    ion in "sea" of electrons (non-local electronic stopping). These collisions are inelastic and result in small energy losses in which the electron are excited or ejected from their shells and then dissipate their energy through thermal vibration of the target.

    Since electron stopping depends directly on the ion velocity, we can write

    C and k are parameters depend on ion, the substrate.

    Local electron interaction

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    Density and distribution of displaced atoms

    An implanted ion can increase the number of recoil atoms only ifit possesses an energy greater than 2Ed (why?), where Ed is the minimum energy required to break four covalent bonds anddislodge a lattice atom is called threshold energy or displacement (for Si, Ed~15eV). When the energy of the incident ion or secondary knocked on atom reach Ed, they can be considered stopped, because if they do damage to transfer all their energy to a lattice atom, they can cause a single displacement but remain at rest in the lattice position themselves.

    Thus the number of displaced atoms created by an energetic particle can be estimated by

    N=En/2Ed ,where En is the energy lost in nuclear collisions.

    Example How many displaced lattice

    atoms are created by a single incident 30 keV arsenic atom?


    N=30,000/2 X 15=1000 displaced atoms

    Thus , each incident arsenic ion creates a trail or cascade of 1000 displaced atoms.

    It is to be noted that for a heavy ion like arsenic, this energy is mainly dissipated due to nuclear collisions. How about lighter ion (i.e. boron)?

    Damage annealing

    Goals: Remove primary damage created by

    the implant and activate the dopants.

    Restore silicon lattice to its perfect crystalline state.

    Restore the electron and hole mobility.

    Do this without appreciable dopantredistribution.

    Bulk and surface recombination take place on a short time scale.

    The origin of the interstitial type defects is from the extra dopantatom introduced into the lattice. This gives rise +1 model.

    Monte Carlo simulation of the recombinationof I and V damage generated by an implant and following annealing at 800oC.

    Origin of {311} clusters defects after annealing

    {311} clusters are formed by capturing a row of interstitials dimersthat lie on the {311} plan and grow by extending in the 110 directions (annealing above 400oC).

    After a 5-second anneal at 900oC, there may be very high concentration (~1011 cm-2) of these {311} defects.

    {311} defects anneal out in sec - min at upon further annealing but eject I TED.

    Stable dislocation loops can form when the damage is greater (amorphizing implant).

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    Transient Enhanced Diffusion (TED)

    TED occurs when an attempt is made to anneal implant damage and restore the lattice to its crystalline perfection. It consist of a burst of diffusion many thousand of time faster than what is normally absorb for similar anneal when no implant damage is present

    The basic model for TED assumes that all the implant damage recombines rapidly, leaving only 1 interstitial generated per dopant atom when the dopant atom occupies substitutional site (the +1 model) [Giles].

    THIN FILM DEPOSITION -Introduction

    Many films, made of many different materials aredeposited during a standard CMOS process. These layers include silicon dioxide, silicon nitride, poly silicon and metal.

    In this set of notes we describe the requirements, methods and equipment used to deposit these thin films.

    Requirements or desirable traits for deposition:

    1. Desired composition, low contaminates, goodelectrical and mechanical properties.

    2. Uniform thickness across wafer, and wafer-to wafer.

    3. Good step coverage (conformal coverage).

    4. Good filling of spaces.

    5. Planarized films .

    Issue related to thin filmand their deposition

    Quality of the deposited filmUniform thickness across a wafer

    Chance of high resistivityMechanical cracking

    Filling contact holewith a metal

    Filling between metallines with an oxide

    Incomplete filling leading to a voidIn dielectric between the lines.

    A void in a metal layer can lead toHigh sheet resistance and in adielectric can result in creaking problem.

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    Aspect ratio

    An important parameter that can effect filling and bottom coverage is the aspect ratio of a feature, defined as,

    whAR =

    A deep narrow contact holeWould have a large aspect ratioAnd would be harder to fill.

    Historical Development and Basic Concepts

    Two main types of deposition methods have been developed and are used in CMOS technology:

    Chemical Vapor Deposition (CVD)- APCVD, LPCVD, PECVD, HDPCVD

    Physical Vapor Deposition (PVD)- evaporation, sputter deposition

    Atmospheric Pressure Chemical Vapor Deposition ( APCVD)

    Steps involved in a CVD process:

    1. Transport of reactants to the deposition region.

    2. Transport of reactants from the main gas stream through the boundary layer to the wafer surface.

    3. Adsorption of reactants on the wafer surface.

    4. Surface reactions, including: chemical decomposition or reaction, surface migration to attachment sites (kinks and ledges); site incorporation; and other surface reactions (emission and redeposition for example).

    5. Desorption or reemission of by-products.

    6. Transport of by-products through the boundary layer.

    7. Transport of by-products away from the deposition region.

    Kinetics of CVD thin film deposition (cont.)

    In steady state F=F1=F2

    The growth rate (growth velocity) is now given by,

    where N is the number of atoms incorporated perunit volume in the film (5 x 1022 cm-3 for the case ofepitaxial Si deposition) and Y is the mole fraction(partial pressure/total pressure) of the incorporatingspecies , can be written as

    Y=CG/CT=PG/PtotalWhere CT is the concentration of all the gas molecules in the

    gas phase (i.e. SiCl4, H2)

    Note the similarity of this analysis to the Deal Groveoxidation model (Chapter 6).

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    Limiting cases of growth velocity1. If kS

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    Possible methods to reduce autodopinga) Back side seal with a film of polysilicon, silicon dioxide, or silicon nitride to

    prevent evaporation from the substrate.

    b) Extended 'prebake' at high temperature to reduce the surface concentration of the heavily doped region by depleting the exposed region from impurities.

    c) Use of dopants with lower vapor pressure, such as Sb instead As. (The lower solid solubility limit of Sb in silicon, however, limits its maximum concentration to about 2x1019cm -3).

    d) Deposition of an undoped cap-film followed by the deposition of the desired layer (two-step deposition).

    e) Reduced pressure deposition, increasing the dopant mean-free path and hence the probability that the species escape from the boundary before being adsorbed at the surface of the crystal (Fig.).

    Low Pressure Chemical Vapor Deposition( LPCVD)

    Atmospheric pressure systems have major drawbacks

    If operated at high T, a horizontal configuration must be used (few wafers at a time).

    If operated at low T, the deposition rate goes down

    and throughput is again low.

    LPCVD system Advantages

    Lower chemical reaction temperature Good step coverage and uniformity Vertical loading of wafer-high

    throughput Less dependence on gas flow dynamics Can be performed in standard tube


    Low pressure extending the surface reaction regime to higher temperature (review)

    Since hG is much larger at the lower pressure, mass transport through the boundary layerbecomes much less important compared to the surface reaction.

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    Plasma Enhanced CVD ( PECVD)

    Non-thermal energy to enhance processes at lower temperatures.

    Plasma consists of electrons, ionized molecules, neutral molecules, neutral and ionized fragments of broken-up molecules, excited molecules and free radicals.

    Free radicals are electrically neutral species that have incomplete bonding and are extremely reactive. (e.g. SiO, SiH3, F)

    The net result from the fragmentation, the free radicals, and the ion bombardment is that the surface processes and deposition occur at much lower temperatures than in non-plasma systems (APCVD, LPCVD).

    By supplying additional energy from the plasma to the reactantsgases, the reaction needed for deposition can occur at temperature much lower than those needed when only thermal energy is provided.

    High Density Plasma ( HDP)CVD

    Remote high density plasma with independent RF substrate bias.

    Allows simultaneous deposition and sputtering for better planarization and void-freefilms (later).

    Mostly used for SiO2deposition.

    Physical Vapor Deposition ( PVD)

    PVD uses mainly physical processes to produce reactant

    species in the gas phase and to deposit films.

    In evaporation, source material is heated in high vacuum chamber. (P

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    Sputter Deposition

    Uses plasma to sputter target, dislodging atoms which then deposit on wafers to form film.

    Higher pressures than evaporation - 1-100 mtorr.

    Better at depositing alloys and compounds than evaporation.

    Typical sputtering energy range from 0.5KeV- 5 KeV.

    Plasma structure and voltage distribution in DC sputter system

    The plasma contains ~ equal numbers of positive argon ions and electrons as well as neutral argon atoms.

    Most of voltage drop of the system (due to applied DC

    voltage, Vc) occurs over cathode sheath.

    Ar+ ions are accelerated across cathode sheath to the

    negatively charged cathode, striking that electrode

    (the target) and sputtering off atoms (e.g. Al).

    These travel through plasma and deposit on wafers

    sitting on anode.

    Important process in Sputter deposition

    A minimum energy on the order of 10-20eV, is needed to sputter an atom.

    Sputtering targets are generally large and provide awide range of arrival angles in contrast to a pointsource.

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    asymmetric depositions Asymmetric deposition

    means that thicker deposition occurs on one side of a feature (a step, for example) than the other




    How can we avoid asymmetric deposition?

    Is there another way to reduce any asymmetry ?

    9.13. How does the ability to fill the bottom of a narrow trench using sputterdeposition change as the target is moved further away from the wafer?Neglect any gas phase collision effects.


    The further away the target, the narrower the arrival angle distribution, similar tomaking the target smaller. So n is greater and better filling of the bottom of anarrow trench is achieved.

    RF Sputter Deposition For DC sputtering, target electrode

    is conducting. To sputter dielectric materials use

    RF power source.

    Due to slower mobility of ions vs. electrons, the plasma biases positively with respect to both electrodes. (DC current must be zero.) continuous sputtering.

    When the electrode areas are not equal, the field must be higher at the smaller electrode (higher current

    density), to maintain overall current continuity.

    Thus by making the target electrode smaller, sputtering occurs "only" on the target.

    Wafer electrode can also be connected to chamber walls, further increasing V1/V2.

    Ionized Sputter Deposition or HDP Sputtering

    In some systems the depositing atoms themselves are ionized. An RF coil around the plasma induces collisions in the plasma creating the ions.

    This provides a narrow distribution of arrival angles which may be useful when filling or coating the bottom of deep contact hole.

    Little deposition at the bottom of the hole due to shadowing effect.

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    . Calculate the mean free path of a particle in the gas phase of a deposition systemand estimate the number of collisions it experiences in traveling from thesource to the substrate in each of the cases below. Assume that in each casethe molecular collisional diameter is 0.4 nm, the source-to-substrate distanceis 5 cm, and that the number of collisions is approximately equal to thesource-to-substrate distance divided by the mean free path.

    a. An evaporation system in which the pressure is 10-5 torr and the

    temperature is 25C. b. A sputter deposition system in which the pressure is 3 mtorr and the

    temperature is 25C. c. An LPCVD system in which the pressure is 1 torr and the temperature is

    600C. d. An APCVD system in which the pressure is 1 atm and the temperature is



    The mean free path of a gas particle is (Eqn. 9.26) = kT2d2P where k =

    1.36x10-22 cm3 atm K-1, T is the temperature in K, d is the collision diameter of themolecule in cm (approximately 4x10-8 cm for most molecules of interest), and P isthe pressure in atm. The # collisions is approximately equal to the source-to-substrate distance divided by the mean free path in each case. Plugging in thenumbers gives:

    (in cm) = kT2d2 P

    = 1.36x1022 cm3 atm K1 T(K)

    2 4x108 cm( )2 P(torr)760torr / atm = 1.45x105 T(K)


    a. 433 cm, 1.2x10-2 collisions; b. 1.44 cm, 3.5 collisions; c. 0.013 cm, 392 collisions;

    d. 1.7x10-5 cm, 3.0x105 collisions

    Summary of the key ideas In this chapter we have examined how thin films are deposited

    as part of the fabrication of IC. Important issues in thin film deposition include physical and

    chemical properties of the films, step converge and filling of the holes or trenches.

    In the simple model for CVD presented, the deposition process is seen to be limited by surface reaction or by mass transfer.

    At low pressure the mass transfer is not a limiting step, and the surface reaction become rate limiting.

    In PVD arrival angle distribution of the source material at the wafer surface is important.

    Shadowing by topographical features can be very important in PVD method.

    Concurrent sputtering and redeposition of the material along with the direct deposition of ionized species can lead to good gap or hole filling of relatively high aspect ration features.

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    ETCHING - Chapter 10Introduction

    Etching of thin films and sometimes the silicon substrate are very common process steps.

    Usually selectivity, and directionalityare the first order issues.

    Selectivity comes from chemistry; directionality usually comes from physical processes.

    Modern etching techniques try to optimize both.

    Directionality is a measure of the relative etch rates in different directions ,usually vertical versus lateral.

    Selectivity (S=r1/r2) means that etch rate of the layer to be etched should be fast compared to the etch rate of mask and substrate.

    Simulation tools are beginning to play an important role in etching just as they are in deposition.

    General etch requirements:1. Obtain desired profile (sloped or vertical)2. Minimal undercutting or bias3. Selectivity to other exposed films and resist4. Uniform and reproducible5. Minimal damage to surface and circuit6. Clean, economical, and safe

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    The undercut can be described in terms of Anisotropy, which is given by

    A = 1 - RL/RV, where RL and Rv are the lateral and vertical etch rates.What is value of A for isotropic etching ?


    Isotropic etching implies undercutting. This is often expressed in terms of the etch bias b.

    Because of their isotropic nature, wet chemical etches are rarely used in mainstream IC manufacturing today.

    Selectivity The selectivity, S of an etch process between two materials, 1 and 2, is simply the

    ratio of their etch rates, r, in the enchant , or

    Material 1 is usually the film being etched, and material 2 is either the masking material or material below the film.



    rrS =

    Common problems in wet etch processes

    Illustration of etch bias and over etch.10 - 20% over etches are common.

    A common problem in wet etch processes is undetected resist scumming. This occur when some of the exposed photoresist is not removed in thedevelop process because of incomplete exposures and insufficient Developing of the pattern .

    During etching the by products can form bubbles that can prevent the movement of fresh enchant to the surface. The problem is morepronounced near pattern edges.

    Mask erosion can be an issue for both isotropic and anisotropic etching profiles.\

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    Ion Enhanced Etching

    Figure shows etch rate of silicon as XeF2 gas (not plasma) and Ar+ ions are introduced to the silicon surface.

    Only when both are present does appreciable etching

    occur. Etch profiles can be very

    anisotopic, and selectivitycan be good.

    Many different mechanisms proposed for this synergisticetching between physical and chemical

    mechanisms proposed forsynergistic etching

    Inhibitor could be either direct byproduct of etch process, or indirect byproduct (such as polymer formation from C in gas or from photoresist).

    Whatever the exact mechanism (multiple mechanisms may occur at same time):

    the two components act in series. get anisotropic etching and little undercutting because of directed ion flux. get selectivity due to chemical component. many applications in etching today.

    Etching by radical is negligible

    Summary of plasma system and mechanism

    Summery of trends of different etch system

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    Backend technology: fabrication of interconnects and the dielectrics that electrically and physically separate them.

    More metal interconnect levels increases circuit

    functionality and speed. Local interconnects

    (polysilicon, silicides, TiN) versus global interconnects (usually Al).

    Early structures were very simple by today's standards.

    Issues in VLSI Metallization

    Speed: switching speed, RC delay Intensity: electromigration (I), electric breakdown (V) Stability: contact interface, stable I-V characteristics Voltage drop: IR drop reduces voltage on transistor Area: connection wires have to be narrow as device

    density increases

    Speed limitations: next generation technology trends

    The speed limitations of interconnects can be estimated fairly simply.

    R=LW/H C = Kox o WL / xox+ Ko xo H L/ Ls Where Kox is the dielectric constsant. The tolat RC delay associated with global

    interconnects is:

    To keep the analysis simple we assume that xox, H, as well as Ls and W, are equal to minimum feature size thus the above equation can be written in terms of the area A of the chip

    2min )(


    AK ooxL =

    The goal is to decrease L, or at least to keep it from increasing too much as some of the dimension change.

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    2min )(


    AK ooxL =

    Recent analysis by Bohr based on Intel's technology agree with the qualitative predictions of this simple analysis

    Why Aluminum? Low resistivity Al at room temperature (2-3cm). It adheres (hold fast or stick by) well to Si and SiO2. It makes good electric Ohmic contact to heavily

    doped Si It react with SiO2 even at low T, forming a thin layer

    of Al2O3 at the interface, which act as a glue layer to bind the Al to the SiO2.

    In case of Al-to-Si contact, the Al reduce any native oxide on top of Si, which could prevent ohmic contact.

    Its presence assist the annealing out of interface traps at the Si-SiO2 interface., presumably by converting H2O to free H, which passivate the traps.

    Spiking problem

    Because Si has a significant solubility in Al, e.g. ~1% at 450oC, heat treatment result in dissolution of Si, which tends to proceed more slowly along (111) than (110) or (100) planes.

    This creates voids in the crystal into which Al precipitates and form conductive spikes (0.2-1m) that can cause high leakage or shorts in shallow junctions.

    Methods used to reduce spikingOne solution to the Al spiking

    problem is to use Al films that already have Si in them (Al-Si alloy). Therefore, the solubility requirement is already fulfilled.

    In this way spiking problem, reduced but another arises.

    Widely used, but Si can precipitate when cooling down, leaving Si nodules.

    Better solution: use barrier layer(s). Ti or TiSi2 forgood contact and adhesion, TiN for barrier

    TiSi2/TiN is not the only choice, various barrier option are available.TiSi2/TiN is not the only choice, various barrier option are available.

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    Interconnects and Vias

    Al has been the dominant material for interconnects.

    9 - low resistivity9 - adheres well to Si and SiO29 - can reduce other oxides9 - can be etched and deposited using

    reasonable techniques Problems:X relatively low melting point and

    soft.X - need a higher melting point

    material for gate electrode and local interconnect polysilicon.

    - hillocks and voids easily formed in Al. Still Al is dominant for global interconnects!

    Hillocks,voids and Electromigration Hillocks and voids form because

    of stress and diffusion in Al films.

    Heating places Al under compression hillocks.

    Cooling back down can place Al under tension voids.

    Adding few % Cu stabilizes grain boundaries and

    minimizes hillock formation.Coefficient of thermal expansion ofSi=2.6 x 10-6 oC-1Coefficient of thermal expansion ofAl: 23 x 10-6 oC-1

    A related problem with Al interconnects iselectromigration. High current density (0.1-0.5 MA/cm2) causes movement of Al atoms in direction of electron flow. Adding Cu (0.5-4 weight %) can also inhibit electromigration.

    Next development

    Adding Cu and Si to the Alincreases sheet resistivity of the interconnect by as much as 35%, but this was the necessary trade-off in order to prevent the failure of the circuits due to electromigration, hilllocks and void formation.

    Next development was use of other materials with lower resistivity as local interconnects, like TiN and silicides (TiSi2, WSi2, NiSi2).

    Silicides used to 1. strap polysilicon, 2. strap junctions, 3. as a local interconnect.

    Silicide material can be used to reduce all the above mentioned problems.Silicide offer:9 low electric resistivity9Stable at high temperature9Easy to plasma eatch9Provide good contact to other material9Do not exhibit much electrmigration

    Planarization Reducing the step heights and achieving more planer technology

    through processing technique is called planarization. The degree of planarization (DOP) is define as,

    xistep=the initial step heightxfstep=the final step height

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    RC delay due to interconnects: Need of multilayer

    The design of multilayer system is aimed at reducing lead resistanceand capacitance without compromising yield and reliability.

    Interconnect and via structures made up of multilayers have been developed for barrier and adhesion reason. It is believed that overall capacitance (line to line or line to substrate) can be decreased by increasing the number of interconnect layers.

    The time constant of various interconnect material can be estimated by simple lumped parameter model:


    oxmet tt


    Memory makers found that long wire lines made from poly silicon with a silicide could decrease the access time of the device. Assume that the line is 1 cm long, the oxide is 1m thick, the poly and silicide are each 0.5mm thick, and the resistivites of the two films are 10-3 and 10-4 cm, respectively. Use the simple lumped RC model to determine the delay associated with each of the two lines.

    Isolation materials: dielectrics Dielectrics electrically and physically

    separate interconnects from each other and from activeregions.

    Two types:- First level dielectric (before Al

    deposition)- Intermetal dielectric (IMD) (after Al


    First level dielectric is usually SiO2 doped with P or B or both (2-8 wt. %) to enhance reflow properties.

    PSG: phosphosilicate glass, reflows at 950-1100C

    BPSG: borophosphosilicate glass, reflows at 800C.

    After 800oC reflow step

    Requirements for VLSI dielectric layers:

    Good electric isolation (low dielctric constant) High break down field strength Low leakage (high resistivity) Provide good adhesion to Si, metals, and silicide. Low intrinsic stress. Thermal stability ( up to 950oC for first level and up

    to 500oC for intermetal dielectrics). Impurities free. Low defects densities.

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    Device isolation: MOS transistor isolation How close can be a transistor be placed? When two properly biased MOS transistors are placed near each other,

    they are isolated by reverse biased source-substrate and drain-substrate junctions, as shown in the figure.

    However, to maintain this isolation , the depletion layers surrounding the various source-drain diodes must not merge, and this requirement limits the minimum spacing between the devices. Usually the spacing between adjacent transistor must be greater than twice the maximum depletion layer width, which can be estimated by

    Wd=2Kso(VA+Vbi)/qNB Vbi=0.56+(kT/q In(NB/ni)

    Self isolated

    In early technology >2m spacing does not represent a problem but for advanced submicron features sizes, this form of isolation is not satisfactory.

    Wd=2Kso(VA+Vbi)/qNBVbi=0.56+(kT/q In(NB/ni)

    Shallow trench isolation (STI) In STI the depletion layers are effectively cutoff and

    separated by the oxide. The minimum space between the drain diffusions is now

    set by minimum width of the STI region and can ideally approach a minimum feature size in the technology.


    Deep trench isolation process

    Typical dimensions are 0.18 to 1 m width and 2 to 5 m in depthTrenches with width 0.25m and depth of 10m have been demonstrated.