354 33 Powerpoint-slides CH3

N. Senthil Kumar,M. Saravanan & S. Jeevananthan Oxford University Press 2013

Oxford University Press 2013

Oxford University Press 2013Instruction Set and Execution in 8085


Every microprocessor has its own instruction set. Based on the design of the ALU and the decoding unit, the microprocessor manufacturers generally list out the instruction set for the every microprocessor manufactured. The instruction set consists of both the assembly language mnemonics and the corresponding machine code. MICROPROCESSOR INSTRUCTIONS Oxford University Press 2013


The purpose of an instruction set is to facilitate the development of efficient programs by users.The instruction set is based on the architecture of the processor. So, to understand the instruction set of a processor, it is necessary to understand the basic architecture of the microprocessor and the user accessible registers in it. MICROPROCESSOR INSTRUCTIONS Oxford University Press 2013


An instruction is a binary bit pattern that can be decoded inside a microprocessor to perform a specific function. The assembly language mnemonics are the codes for these binary patterns so that the user can easily understand the function performed by these instructions. The entire group of instructions is called the instruction set, and this determines the functionalities the microprocessor can perform.INSTRUCTION SET Oxford University Press 2013


Intel 8085 processor has its own set of instructions listed both in mnemonics and machine code, also called as object code. As 8085 is an 8-bit processor, the machine codes for the instructions are also 8-bits wide.INSTRUCTION SET Oxford University Press 2013


The microprocessor instruction can be classified based on many parameters such as the functionality, length and operand addressing.Instructions can be classified into five categories based on the functionality provided by the instructions. a) Data Transfer (copy) operations,b) Arithmetic operations,c) Logical operations,d) Branching operationse) Machine-control operations

Classification of Instructions Oxford University Press 2013


Based on the length of the instructions, the instruction set can be classified into three or more types. a) One-byte instructions, b) Two-byte instructions andc) Three-byte instructions etc.Classification of Instruction set Oxford University Press 2013


Based on the way the operand is addressed in an instruction, the instruction set can be classified into many types. Following is the list of classification of 8085 instructions based on addressing modes. a) Immediate addressing instructionsb) Direct addressing instructionsc) Indirect addressing instructions d) Implied addressing instructions.

Classification of Instruction set Oxford University Press 2013


INSTRUCTION CLASSIFICATION BASED ON FUNCTIONALITY



This group of instructions copy data from a location called a source register to another location called a destination register. The contents of the source register are not modified.

Data Transfer Operations Oxford University Press 2013


Data Transfer Operations Oxford University Press 2013

MnemonicOperandAddressing modeNumber of bytesT statesMOVReg destination, Reg sourceRegister direct14MOVReg destination,MMemory Indirect17MOVM,Reg sourceMemory Indirect17

MVIReg, byteImmediate27MVIM, byteImmediate210

LXIB, DbleImmediate310LXID, DbleImmediate310LXIH, DbleImmediate310LXISP, DbleImmediate310

LDAadrMemory direct313STAadrMemory direct313

LDAXBMemory Indirect17LDAXDMemory Indirect17STAXBMemory Indirect17STAXDMemory Indirect17

LHLDadrMemory direct316SHLDadrMemory direct316


Arithmetic operations include addition, subtraction, increment, and decrement. As 8085 has accumulator oriented ALU, one of the data for the arithmetic instructions should be stored in the accumulator and the result is also stored in the accumulator. Arithmetic and Logical operation cannot e executed without the accumulator

Arithmetic Operations Oxford University Press 2013


The addition instructions of the 8085 add the contents of a register or memory location with the contents of the accumulator. The result is stored in the accumulator. The Intel 8085 instruction set supports two types of addition instructionswith and without addition of the carry flag content to the least significant bit of the numbers. The instruction set also supports 16-bit addition, i.e., the content of the HL register pair can be added to that of another register pair and the result stored in the HL register pair.Addition (ADD) Oxford University Press 2013


The instruction set of the 8085 supports two types of subtractionwith borrow and without borrow. Like addition, the subtraction operation also uses the accumulator as reference, i.e., it subtracts the content of a register or memory location from that of the accumulator and stores the result in the accumulator.

Subtraction (SUB) Oxford University Press 2013


The 8-bit contents of a register or a memory location can be incremented or decrement by 1 INR, DCR. These operations can be used to increment or decrement the contents of any register, register pair, or memory location. Unlike the arithmetic and logical operations, the increment and decrement operations need not be based upon the accumulator.Increment/Decrement Oxford University Press 2013


Logical instructions are also accumulator-oriented, i.e., they require one of the operands to be placed in the accumulator. The other operand can be any register or memory location. The result is stored in the accumulator. The operations that use two operands are logical AND, OR, and EXOR. The operation that uses a single operand (i.e., the accumulator) is the logical complement or NOT operation. The instruction set of the 8085 supports rotation of the data stored in accumulator. Logical Operations Oxford University Press 2013


The data can be rotated left or right, through the carry or without the carry. The most important 8085 instruction is the compare instruction. This instruction is used to compare register or memory content with the accumulator content. The result of comparison such as equal to, greater than, or less than is reflected in the flag register bits.Logical Operations contd.. Oxford University Press 2013


Branching instructions are important for programming a microprocessor. These instructions can transfer control of execution from one memory location to another, either conditionally or unconditionally. Branching can take place in the following two ways: a) Execution control cannot return to the point of branching. Example: Jump instructions b) Execution control can return to the point of branching, which is stored by the 8085. Example: Subroutine call instructionsBranching Operations Oxford University Press 2013


These instructions can be used to control the execution of other instructions. They include halting the operation of the microprocessor, interrupting program execution, etc. Machine Control Operations Oxford University Press 2013


Each instruction of 8085 has two parts: One is task to be performed, called the operation code (opcode)Second is the data to be operated on, called the operand. The operand (or data) can be specified in various ways. It may include 8-bit (or 16-bit) data, an internal register, a memory location, or an address. In some instructions, the operand is implicit.

INSTRUCTION CLASSIFICATION BASED ON LENGTH



The 8085 instruction set is classified into the following three groups according to word size: a) One-word or 1-byte instructions b) Two-word or 2-byte instructions c) Three-word or 3-byte instructions Assembly language instructions should be converted into machine code for storage and execution by the processor. So the length of the machine language code instructions determines the length of the program.This in turn determines the amount of memory required for the program. INSTRUCTION CLASSIFICATION BASED ON LENGTH contd.. Oxford University Press 2013


Instructions that require only one byte in machine language are called one-byte instructions. These instructions just have the machine code or opcode alone to represent the operation to be performed. The common examples are the instructions that have their operands within the processor itself. Even though the instruction ADD M adds the content of a memory location to that of the accumulator, its machine code requires only one byte.

One-Byte Instructions Oxford University Press 2013


Example - One-Byte Instructions Oxford University Press 2013


Two-Byte InstructionsIn a two-byte instruction, the first byte specifies the operation code and the second byte specifies the operand. Oxford University Press 2013

OpcodeOperandMachine code / Opcode/ Hex codeByte descriptionMVIA, 7FH3E 7FFirst ByteSecond ByteADI0FHC6 OFFirst ByteSecond Byte

IN40HDB 40First ByteSecond Byte


Two-Byte Instructions contd..Assume that the data byte is 32H. The assembly language instruction is written as The instruction would require two memory locations to be stored in consecutive memory locations. MVI r, data ; r

ADI data A

Instructions that require three bytes in machine code are called three-byte instructions. In 8085 machine language, the first byte of the three-byte instructions is the opcode which specifies the operation to be performed. The next two bytes refer to the 16-bit operand, which is either a 16-bit number or the address of a memory location.Three-Byte Instructions Oxford University Press 2013


Three-Byte Instructions Examples Oxford University Press 2013

OpcodeOperandHex CodeByte descriptionJMP2085HC38520First byteSecond ByteThird ByteLDA8850H3A5088First byteSecond ByteThird ByteLXIH, 0520H212005First byteSecond ByteThird Byte


This instruction would require three memory locations in memory. Three byte instructions - opcode + data byte + data byte Examples: LXI rp, 16-bit data where rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data bytes are 16-bit data to be stored in L and H in sequence. LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate addressing.Three-Byte Instructions contd.. Oxford University Press 2013


LDA addr A

Every instruction in a program has to operate on data. The process of specifying the data to be operated on by the instruction is called addressing.Efficient software development for the microprocessor requires complete familiarity with the addressing mode employed for each instruction. For example, the instructions MOV B, A and MVI A, 82H are used to copy data from a source to a destination.

ADDRESSING MODES IN INSTRUCTION Oxford University Press 2013


In these instructions, the source can be a register or an 8-bit number (00H to FFH); the destination is a register. The source and destination are operands. The various formats for specifying operands are called addressing modes.ADDRESSING MODES IN INSTRUCTION contd.. Oxford University Press 2013


The 8085 has the following 5 different types of addressing.a) Immediate Addressingb) Direct Addressingc) Register Addressingd) Indirect Addressinge) Implied Addressing

Types of Addressing Modes Oxford University Press 2013


Immediate addressing transfers the operand given in the instruction-a byte or a word into the destination register or memory location. Operand is part of the instruction itself.

Format of Immediate AddressingInstructionsImmediate Addressing Oxford University Press 2013

OpcodeOperand


MVI A, 9AH (a) The operand is part of the instruction. (b) The operand is stored in the register mentioned in the instruction. ADI 05H (a) Add 05H to the contents of the accumulator. (b) 05H is the operand. Immediate addressing has no memory reference to fetch data.It executes faster, but has limited data range. Example - Immediate Addressing Oxford University Press 2013


Memory Direct addressing moves a byte or word between a memory location and a register. The memory location address is given in the instruction. The instruction set does not support a memory to memory transfer.

Memory Direct Addressing Oxford University Press 2013


Format of memory Direct Addressing Oxford University Press 2013


LDA 850FH This instruction is used to load the contents of the memory location 850Fh into the accumulator. STA 9001H a) This instruction is used to store the contents of the accumulator to the memory address 9001H. b) In these instructions the memory address of the operand is given in the instruction.

Example - Memory Direct Addressing Oxford University Press 2013


Direct addressing is also used for data transfer between processor and output / input devices. For example, a) IN instruction is used to receive data from the input port and store it into the accumulator. b) OUT instruction is used to send the data from the accumulator to the output port.e.g., IN 00H and OUT 01H

Memory Direct Addressing contd.. Oxford University Press 2013


Register direct addressing transfers a copy of a byte or word from the source register to the destination register. Operand is in register named in the instruction. It features very fast execution, very limited register space and requires good assembly programming. Mostly the operand is within in the processor itself and so the execution is faster. Register Direct Addressing Oxford University Press 2013


Format of Register Direct Addressing Oxford University Press 2013


MOV Rd, RsMOV B, C ; Copy the contents of C register to B register.ADD BAdd contents of register mentioned B register content to A, accumulator

Example - Register Direct Addressing Oxford University Press 2013


Indirect addressing transfers a byte or word between a register and a memory location. The memory location address is stored in a register and that register is specified in the instruction. Effective Address is calculated by the processor using contents of the register specified in the instruction. This type of addressing employs several accessestwo accesses to retrieve the 16-bit address and a further access (or accesses) to retrieve the data which is to be loaded in the register. Indirect Addressing Oxford University Press 2013


Format of Indirect Addressing Oxford University Press 2013


MOV A, M a) Here, the data is in the memory location pointed to by the contents of the HL pair. b) The data is moved to the accumulator Example - Indirect Addressing Oxford University Press 2013


In implied addressing mode, the instruction itself specifies the data to be operated. For example CMA complement the content of the accumulator. No specific data is mentioned in the instruction. The instruction does not need any specific operand

Implied or Implicit Addressing Oxford University Press 2013


The 8085 microprocessor instruction set has 74 operation codes and 246 instructions set. It is compatible with the predecessor 8080A instruction set with two additional instructions SIM and RIM related to serial I/O. The complete instruction set is also listed in Appendix 1 with additional information such as number of T states required for execution and the flags affected.

INSTRUCTION SET OF 8085 Oxford University Press 2013


The assembly language programs are written for performing the specific function and are converted into the machine language code and then stored in the memory of the microprocessor based system. The conversion of assembly language program into machine language code is called as Assembling and the application that performs this task is called assembler. Format of Assembly language instructions and programs Oxford University Press 2013


This conversion or assembling can be done manually by the programmers also. So, in order to facilitate the process of assembling, the assembly language programs are written in a specific format as given below.

Format of Assembly language instructions and programs contd.. Oxford University Press 2013


Format of Assembly language instructions and programs contd..In general, the actual assembly language mnemonics with the operands are written first. The address where the instructions are stored is given a dummy name and that name is called as label.The purpose of this label is to give the proper branch address in the instructions.The Labels are separated from the mnemonics with colon. Oxford University Press 2013


The comments column is essential for any program so that the programmer can easily understand the logic of the program later. Without the comments, it becomes difficult for any person to understand any assembly language program. The comments are separated from the mnemonics with a semicolon.Format of Assembly language instructions and programs contd.. Oxford University Press 2013


The first two columns are corresponding to the physical memory address and the actual machine code. These two columns are filled up later after completing the assembly language programming. These columns will actually have binary numbers but for the sake of easy understanding, hexadecimal numbers are used.Format of Assembly language instructions and programs contd.. Oxford University Press 2013


For manual assembling, these two columns are filled by the programmer.An assembler can generate these columns automatically. An example of the assembly language program format is given below.Format of Assembly language instructions and programs contd.. Oxford University Press 2013


Format of Assembly language instructions and programs contd.. Oxford University Press 2013

Memory addressMachine code / opcodeLabel Mnemonics with operandscomments80003E START:MVI A,5FHload data in the accumulator80015F8002Address of the next memory location


The following notations are used in the description of the instruction.a) R = 8-bit register within 8085 (A, B, C, D, E, H and L) b) Rs = Register source c) Rd = Register destination(A, B, C, D, E, H and L)d) Rp = register pair (BC, DE, HL and SP)e) P= Port address 8-bit binary number or 2 hex digitsf) 8-bit = 8-bit data or 2 hex digitsg) 16-bit = 16bit data/ address or 4 hex digitsh) ( ) = contents of

Notation description Oxford University Press 2013


Data transfer instructions are used for data transfer between two registers in the microprocessor or between a peripheral device and microprocessor. MVI instruction is used for storing any 8-bit data to a microprocessor register.LXI instruction is used for storing 16-bit data to a register pair.MOV instruction is used for data transfer between registers in direct addressing.Data Transfer Instructions Oxford University Press 2013


MOV can be used for data transfer between a memory location and a register in indirect addressing mode. If the instruction has M in the operand field, then the memory location pointed by HL pair is considered for data transfer.LDA and STA are using memory direct addressing mode and use 16-bit memory address as operand.

Data Transfer Instructions contd.. Oxford University Press 2013


LDAX and STAX are using indirect addressing mode for data transfer. The operand given in the instruction is one of the register pairs BC or DE. Register pair HL is not used with LDAX, because we have the alternate MOV A,M.LHLD and SHLD are the instructions used to transfer 16-bit data between HL register pair and the two consecutive memory locations. For example, executing SHLD 9000H instruction will store the contents of L register and 9000H and the contents of H register in 9001H.



PUSH and POP instructions are used for data transfer between a register pair and stack. The stack is a set of memory locations configured as Last In and First Out LIFO or First In Last Out FILO array. The top of the stack locations is pointed by a special register Stack Pointer within the microprocessor. PUSH instruction will store the register pair given in to the instruction to the two memory locations of stack. Similarly POP instruction will copy the last two bytes stored in the stack to the register pair mentioned in the instruction. Data Transfer Instructions contd.. Oxford University Press 2013


Care must be taken in using these instructions as the stack is configured as LIFO array. Another instruction to store data to the stack is XTHL which actually exchanges the two top memory locations of stack and the HL register pair.Stack Pointe can be initialized using LXI instruction or SPHL instruction SPHL instruction will copy the contents of H and L register pair to the Stack Pointer.



IN and out instructions are using 8-bit port addresses as the operand.IN instruction is used to get data from the input port and the data obtained is stored in the accumulator. OUT instruction is to issue data to an output port from the accumulator.XCHG instruction is used to exchange the content of the HL and DE register pairs.Data Transfer Instructions contd.. Oxford University Press 2013


DATA TRANSFER INSTRUCTIONS - Summary Oxford University Press 2013

MnemonicsTasks performed on execution Addressing modeLength of the InstructionExampleMVI R, 8-bitMove immediate 8-bitImmediateTwo bytesMVI B,3FHLXI Rp, 16-bitLoad register pair immediateImmediateThree bytesLXI B,5AF3H, RsCopy from source to destinationDirect One byteMOV A,BLDA 16-bitLoad accumulator data from the memoryDirectThree bytesLDA 905FHLHLD 16-bitLoad H and L registers directly from two consecutive memory locationsDirectThree bytesLHLD 900AHSTA 16-bitStore accumulator direct to memory locationDirectThree bytesSTA 9050HSHLD 16-bitStore H and L registers direct to two consecutive memory locationsDirectThree bytesSHLD 809FHPUSH RpPush register pair onto stackDirectOne bytePUSH BPOP RpPop top 2 memory locations of stack to register pairDirectOne bytePOP H


DATA TRANSFER INSTRUCTIONS Summary contd.. Oxford University Press 2013

OUT 8-bitOutput data in accumulator to port with 8-bit addressDirectTwo bytesOUT 40HIN 8-bitInput data to accumulator from a port with 8-bit addressDirectTwo bytesIN 30H, MCopy the contents of the memory location pointed by HL register pair to the registerIndirectOne byteMOV B,MMOV M,RsCopy the contents of register to the memory location pointed by HL register pairIndirectOne byteMOV A,MLDAX RpLoad accumulator indirect from memory location pointed by register pairIndirectOne byteLDAX BSTAX RpStore accumulator indirect to memory location pointed by register pairIndirectOne byteSTAX DXCHGExchange H and L with D and E register pairsImplicitOne byteXCHGSPHLCopy H and L registers to the stack pointerImplicitOne byteSPHLXTHLExchange H and L with top of stackImplicitOne byteXTHL


Arithmetic instructions supported by 8085 are Add, Subtraction and its variants. For the arithmetic operations, one of the data must be stored in the accumulator and the other data is given or addressed in the instruction. Add with carry instructions are used for multi-byte addition and used in the addition of higher order bytes.

Arithmetic Instructions Oxford University Press 2013


Subtract with borrow instructions are used in the subtraction of higher order bytes in the multi-byte subtraction.The increment and decrement instructions can be operated not only on accumulator, but also on the other registers including a memory location.The contents of a register pair can be incremented or decremented using INX and DCX instructions.

Arithmetic Instructions contd.. Oxford University Press 2013


DAA is the instruction that supports BCD addition in 8085.The addition of BCD data is done using add instructions only. DAA instruction is used to convert the result of binary addition of the BCD numbers into BCD number. This instruction can not be used to directly convert binary numbers into the BCD numbers.Arithmetic Instructions contd.. Oxford University Press 2013


ARITHMETIC INSTRUCTIONS - Summary Oxford University Press 2013

MnemonicsTasks performed on execution Addressing modeLength of the InstructionExampleADI 8-bitAdd immediate to accumulatorImmediateTwo bytesADI 30HACI 8-bitAdd immediate to accumulator with carryImmediateTwo bytesACI 4FHSUI 8-bitSubtract immediate from accumulatorImmediateTwo bytesSUI 2AHSBI 8-bitSubtract immediate from accumulator with borrowImmediateTwo bytesSBI 5CHADD RAdd register content to accumulatorDirectOne byteADD CADC RAdd register content to accumulator with carryDirectOne byteADC ESUB RSubtract register content from accumulatorDirectOne byteSUB BSBB RSubtract register content and borrow from accumulatorDirectOne byteSBB CDAD RpAdd register pair to H and L registersDirectOne byteDAD BINR RIncrement register by 1DirectOne byteINR BINX RpIncrement register pair by 1DirectOne byteINX BDCR R Decrement register by 1DirectOne byteDCR EDCX RpDecrement register pair by 1DirectOne byteDCX DADD MAdd memory content pointed by HL register pair to accumulatorIndirectOne byteADD CADC MAdd memory content pointed by HL register pair to accumulatorIndirectOne byteADC ESUB MSubtract memory content pointed by HL register pair from accumulatorIndirectOne byteSUB BSBB MSubtract memory content pointed by HL pair and borrow from accumulatorIndirectOne byteSBB CINR MIncrement a memory content pointed by HL register pair onceIndirectOne byteINR MDCR MIncrement a memory content pointed by HL register pair onceIndirectOne byteINR MDAADecimal adjust accumulatorImplicitOne byteDAA


Logical instructions supported by 8085 are AND, OR, EXOR and NOT. For the logical operations, one of the data must be stored in the accumulator and the other data is given or addressed in the instruction. The logical operations can be done with accumulator by any immediate data or a register or indirectly addressed memory location content.

Logical Instructions Oxford University Press 2013


Two types rotate instructions are available in 8085. One set - RLC and RRC will just rotate the accumulator contents within itself. RLC instruction will shift the accumulator content left once and in the process the most significant bit of the accumulator will become the least significant bit.

Logical Instructions contd.. Oxford University Press 2013


The other type of rotate instructions RAL and RAR will rotate the accumulator content along with the carry flag included.RAL instruction will shift the accumulator content left once and in the process, the most significant bit will be shifted to carry flag and the carry flag content will be shifted into the least significant bit of the accumulator.

Logical Instructions contd.. Oxford University Press 2013


Logical Instructions - Summary Oxford University Press 2013

MnemonicsTasks performed on execution Addressing modeLength of the InstructionExampleANI 8-bitLogical AND immediate with accumulatorImmediateTwo bytesANI 0FHXRI 8-bitExclusive OR immediate with accumulatorImmediateTwo bytesXRI 01HORI 8-bitLogical OR immediate with accumulatorImmediateTwo bytesORI 80HANA RLogical AND register or memory with accumulatorDirectOne byteANA CXRA RExclusive OR register or memory with accumulatorDirectOne byteXRA DORA RLogical OR register or memory with accumulatorDirectOne byteORA EANA MLogical AND memory pointed by HL register pair with accumulatorIndirectOne byteANA MXRA MLogical XOR memory pointed by HL register pair with accumulatorIndirectOne byteXRA MORA MLogical OR memory pointed by HL register pair with accumulatorIndirectOne byteORA MRLC Rotate accumulator leftImplicitOne byteRLCRRCRotate accumulator rightImplicitOne byteRRCRALRotate accumulator left through carryImplicitOne byteRALRARRotate accumulator right through carryImplicitOne byteRARCPI 8-bitCompare immediate with accumulatorImmediateTwo bytesCPI FFHCMP RCompare register or memory with accumulatorDirectOne byteCMP BCMP MCompare memory pointed by HL register pair with accumulatorIndirectOne byteCMP MCMAComplement accumulatorImplicitOne byteCMACMCComplement carryImplicitOne byteCMCSTCSet carryImplicitOne byteSTC


Branching instructions are used to transfer the execution of microprocessor to a different address.The branching instructions are of two types jump instructions and subroutine instructions. The jump instructions just transfer the execution from one part of the program to another location in the program. The subroutine instructions in a main program can transfer execution to a new location and the execution can return to the main program. Return instructions are used for this purpose.

Branching Instructions Oxford University Press 2013


The branching can take place unconditionally or conditionally based on the flag conditionsPCHL instruction is a special instruction used to branch to the address stored in the HL register pair.RST n is the restart instruction supported by 8085.Upon execution of the RST n instruction, the program execution will be transferred to the address given by n*8. For example, RST 4 instruction will transfer the execution to the address 0020H which is hexadecimal equivalent of 32 decimal.

Branching Instructions contd.. Oxford University Press 2013


In machine code or opcode, the16 bit or 4 hex digit jump address in the branching instructions are given such that the lower byte of the address follows the higher order byte. For example JMP 8030H is coded as C3 30 80. The opcode for JMP i.e. C3 is stored first, followed by 30 and then by 80 for the physical jump address of 8030H.

Branching Instructions contd.. Oxford University Press 2013


Branching Instructions - summary Oxford University Press 2013

MnemonicsTasks performed on execution Addressing modeLength of the InstructionExampleJMP 16-bitJump unconditionallyImmediateThree bytesJMP 9500JC 16-bitJump if carry is setImmediateThree bytesJC 9500JNC 16-bitJump on no carryImmediateThree bytesJNC 9500JP 16-bitJump on positiveImmediateThree bytesJP 9500JM 16-bitJump on minusImmediateThree bytesJM 9500JZ 16-bitJump on zeroImmediateThree bytesJZ 9500JNZ16-bitJump on no zeroImmediateThree bytesJNZ 9500JPE 16-bitJump on parity evenImmediateThree bytesJPE 9500JPO 16-bitJump on parity oddImmediateThree bytesJPO 9500CALL 16-bitCall unconditionallyImmediateThree bytesCALL 9500CC 16-bitCall on carryImmediateThree bytesCC 9500CNC 16-bitCall on no carryImmediateThree bytesCNC 9500CP 16-bitCall on positiveImmediateThree bytesCP 9500CM 16-bitCall on minusImmediateThree bytesCM 9500CZ 16-bitCall on zeroImmediateThree bytesCZ 9500CNZ 16-bitCall on no zeroImmediateThree bytesCNZ 9500CPE 16-bitCall on parity evenImmediateThree bytesCPE 9500CPO 16-bitCall on parity oddImmediateThree bytesCPO 9500RET Return unconditionallyImplicitOne byteRET RC Return on carryImplicitOne byteRC RNC Return on no carryImplicitOne byteRNC RP Return on positiveImplicitOne byteRP RM Return on minusImplicitOne byteRM RZ Return on zeroImplicitOne byteRZ RNZ Return on no zeroImplicitOne byteRNZ RPE Return on parity evenImplicitOne byteRPE RPO Return on parity oddImplicitOne byteRPO PCHLCopy HL contents to the program ImplicitOne bytePCHLRST 0/1/2/3/4/5/6/7RestartImplicitOne byteRST 5


Machine control Instructions are used control the microprocessor execution and functionNOP means no operation. When this instruction is executed, nothing is done and no change the contents of registers of the microprocessor. The program counter alone is incremented to fetch and execute the next instruction.

Machine Control Instructions Oxford University Press 2013


HLT instruction is used to halt the entire program execution of the microprocessor. The microprocessor operation is completely suspended when HLT instruction is executed.Only way to recover the microprocessor to normal functioning is applying hardware reset signal.

Machine Control Instructions contd.. Oxford University Press 2013


DI and EI instructions are used to disable and enable interrupts. Normally, the interrupts are disabled whenever the interrupts are sensed by the microprocessor. To enable interrupts again, the EI instruction has to be executed.



RIM and SIM instructions are used for Reading Interrupt Mask and Setting Interrupt Mask. The SIM instruction is used to send the serial data on SOD line of microprocessor RIM instruction is to receive the serial data on the SID input of the processor.



MACHINE CONTROL INSTRUCTIONS - Summary Oxford University Press 2013

MnemonicsTasks performed on execution Addressing modeLength of the InstructionNOPNo operationImplicitOne byteHLTHalt the microprocessor executionImplicitOne byteDIDisable interruptsImplicitOne byteEIEnable interruptsImplicitOne byteRIM Read interrupt maskImplicitOne byteSIMSet interrupt maskImplicitOne byte


The 8085 microprocessor is designed to fetch the instruction pointed by the program counter and then decode and execute the instruction within the processor. If necessary, further operand fetch will take place before completing the execution. Each instruction has two parts:The operation code, known as opcode and another part - operand.INSTRUCTION EXECUTION AND TIMING DIAGRAM WITH MACHINE CYCLES AND T STATES Oxford University Press 2013


The opcode is a command such as ADD, and the operand is an object to be operated on, such as a byte or the contents of a register.To complete the execution, 8085 needs to perform various operations such as opcode fetch, operand fetch, Memory Read / Write or I/O Read / Write.TIMING DIAGRAM Oxford University Press 2013


The microprocessor external communication function can be divided into three categories:a) Memory read/writeb) I/O read and writec) Interrupt Request Acknowledge

External Communication Function Oxford University Press 2013



Instruction Cycle Defined as the time taken by the processor to complete execution of an instruction. Instruction cycle consists of 1 to 6 machine cycles.Machine Cycle: The time required to complete one operation of accessing memory or an I/O device. The machine cycle consists of 3 to 6 T-states.T state The time corresponding to one clock period. The T state forms the basic unit to calculate the execution of instructions and programs in a processor.Definitions



The 8085 microprocessor has 5 (Five) basic machine cycles. They area) Opcode fetch cycle (4T)b) Memory read cycle (3 T)c) Memory write cycle (3 T)d) I/O read cycle (3 T)e) I/O write cycle (3 T)

Different Machine Cycles



Each instruction of the 8085 processor consists of one to five machine cycles. An instruction execution will have compulsorily, the opcode fetch cycle. Then depending upon the instruction, an instruction cycle will have one or two or three other cycles in the list. When the 8085 processor executes an instruction, it will need to access external memory and I/O devices, in other words need many machine cycles in a specific order.Machine Cycles - Description



Clock Signal Shape



The timing diagram of an instruction ate obtained by drawing the binary levels on the various signals of 8085. It is drawn with respect to the clock input of the microprocessor. It explains the execution of the instruction with the basic machine cycles of that instruction, one by one in the order of execution.Timing Diagram



Opcode fetch machine cycle



At T1, the high order 8 address bits are placed on the address lines A8 A15 and the low order bits are placed on AD7AD0. The ALE signal goes high to indicate that AD0 AD8 are carrying an address. At exactly the same time, the IO/M signal goes low to indicate a memory access operation.Opcode fetch machine cycle



At the beginning of the T2 cycle, the low order 8 address bits are removed from AD7 AD0 and the controller sends the Read (RD) signal to the memory. The RD signal remains low (active) for two clock periods to allow for slow devices. During T2, memory places the data from the memory location on the lines AD7 AD0.




During T3 the RD signal is Disabled (goes high). This turns off the output Tri-state buffers in the memory. That makes the AD7 AD0 lines go to high impedance mode.During T4, the opcode is decoded by the processor and necessary action or control is initiated for the execution of the instruction fetched.




Memory Read Machine Cycle



The memory read machine cycle is exactly the same as the opcode fetch except:a) It only has 3 T-statesb) The S0 signal is set to 0. c) The memory read machine cycle is executed by the processor to read a data byte from memory.d) The processor takes 3T states to execute this cycle.e) The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle.Memory Read Machine Cycle



Memory Write Machine Cycle



The memory write machine cycle is executed by the processor to write a data byte in a memory location. The processor takes 3T states to execute this machine cycle. Now, the active low WR signal is made to low indicating a write operation to the memory chips.

Memory Write Machine Cycle



I/O Read Cycle of 8085



The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral, which is I/O, mapped in the system.8085 uses 8-bit port address. So, the port address is placed in lower order address bus. At the same time, the port address is also placed in the higher order address bus. The IN instruction uses this machine cycle during the execution.I/O Read Cycle



I/O Write Cycle of 8085



The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a peripheral, which is I/O, mapped in the system.The processor takes 3T states to execute this machine cycle.

Introduction - I/O Write Cycle


The AD7 AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information.The high order bits of the address remain on the bus for three clock periods.The low order bits remain for only one clock period and they would be lost if they are not saved externally. The low order bits of the address disappear when they are needed most.

DEMULTIPLEXING AD7-AD0 Oxford University Press 2013


To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7 AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.

DEMULTIPLEXING AD7-AD0 Oxford University Press 2013


DEMULTIPLEXING AD7-AD0Given that ALE operates as a pulse during T1, we will be able to latch the address.Then when ALE goes low, the address is saved and the AD7 AD0 lines can be used for their purpose as the bi-directional data lines.



The microprocessor operation related to data manipulation can be summarized in four functions:Copying dataPerforming arithmetic operationsPerforming logical operationsTesting for a given condition and altering the program sequence.An instruction has two parts: opcode (operation to be performed) and operand (data to be operated on). The method of specifying an operand (directly or indirectly, etc.) is called the addressing mode.Summary Oxford University Press 2013


The instruction set is classified in three groups according to the world size: 1, 2, and 3 byte instructions.The instructions are executed in steps of machine cycles and each machine cycle requires many T states.

Summary contd.. Oxford University Press 2013


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