33arm Selector Guide

SPRING2007

www.arrownac.com/arm

ARM Solutions c

ARROW ARM SOLUTIONS GUIDE

Arrow Electronics ARM Solutions1-866-910-3650 www.arrownac.com/arm

Table of Contents

ARM SUPPORT

4 Arrow Services and Solutions

ARM CORES

8 ARM7TDMI

10 ARM920T

12 ARM926EJ-S

14 ARM966E-S

16 ARM1136J(F)-S

18 ARM Cortex-A8

20 ARM Cortex-M3

22 ARM CortexR4(F)

24 Intel XScale®

ARM SUPPLIERS

34 Freescalei.MX31

36 Intel®

Intel® Network Processors and Intel® I/O Processors

40 NXPLPC210x | LPC23xx and LPC24xx | LPC2478

46 STMicroelectronicsSTR7 and STR9 Families | STR730F | STR710F | STR750F |STR910F

54 Texas InstrumentsDaVinci™

TOOLS

58 IARIAR Embedded Workbench Version 4.41 for ARM

60 KeilThe Keil RealView Microcontroller Development Kit

62 ARMRealView Tools by ARM

It’s a fact. Arrow Electronics is the only distributor and approved trainingcenter for ARM tools in North America.Which means we can solve your ARM-powered design challenges efficiently and completely. Our broad line card features more than a dozenmajor silicon suppliers offering ARMtechnology and our innovative servicescan help you at every point in your design cycle. Whether you need support for ARM software developmentor architecture, you can rely on Arrow to deliver up-to-date and accurate technical information from well-versedindustry experts. Arrow’s vast line card,services, and unparalleled expertise deliver comprehensive ARM solutionsthat get you to market faster.

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Arrow Electronics ARM Solutions

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Arrow solves your ARM challenges through outstanding technical support, training, and seminars designed to address yourspecific ARM requirements. We’re here to help you navigate at every point in the design cycle.

Engineering Expertise—the Right Team for the Job c

Arrow’s Field Applications Engineers (FAEs) provide expertsupport for all your design requirements, no matter where youare located. Our FAEs undergo monthly ARM training andconstantly deliver the latest technical overviews of ARMtechnologies, so you can rest assured the information youreceive is accurate, up-to-date, and relevant.

The Industry’s Only ARM Training Center c

Arrow is the “go-to source” for ARM training. It’s the onlyapproved ARM training center in North America and theonly distributor for ARM tools. You can turn to us for relevanttechnical information conveyed by seasonedtrainers because our team draws from theworld’s largest and most experienced poolof ARM technology experts. Our field trainers provide multi-day classes that dive deep into ARM architectures and surrounding development tools. Theseclasses can be conducted at any Arrowbranch or customer location and give you access to quality technical training available only from Arrow and ARM. To register or for more information, go towww.arrownac.com/arm.

ARM Seminar Series for High-EndApplications

ARM technology is widely used in high-performance applicationsthat require the most from a processor yet need to maintain alow power profile. This seminar series is aimed at applicationsthat utilize media, complex user interfaces, and computational-intensive applications on large data segments. The higher endof the industrial, medical, transportation, and other commercialmarkets is addressed, providing you with valuable, effectivesolutions. For more information, visit www.arrownac.com/atsf.

EmbeddedDeveloper.com c

Finding the right ARM solution has never been easier. With EmbeddedDeveloper.com, you can search ARM devices by core type, peripheral sets, price, and many other specifications. Compare and contrast device functions,download specifications and datasheets, and even go to the Arrow shoppingcart and buy the bestdevelopment tool solution on-line.

ARM Support from Concept through Production

For information on Arrow’s ARM training and seminars, visit www.arrownac.com/arm or call 1-866-910-3650.

FIND. COMPARE. BUY.

Arrow Technical Solutions Forum (ATSF): c

ARM Seminar Series for Cost-Sensitive ApplicationsThis seminar series offered by Arrow addresses embeddedcustomers’ demand for ARM technology and supports youremerging requirements.ARM offers some of thebest solutions for balanc-ing the needs for high per-formance, high integration, low power, and small die sizes (low cost). This ARM technology seminar series provides valuable solutions that get you to market faster. Visitwww.arrownac.com/atsf for more information.

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Arrow Consulting Engineering Services c

The Arrow Consulting Engineering Services (ACES) programputs you in touch with pre-screened, qualified, and certified third-party solutions and design services companies so you can save time, effort, and resources. The superior core competencies of our partners allow them to provide complete outsourceddesigns—while allowing you to focus on your core competency.

Arrowdevtools.com c

Find the best reference designs and evaluation tool solutionswith arrowdevtools.com—an on-line development tool selectionand purchasingprocess that gives youaccess to a vast rangeof development tools.This proprietaryparametric search engine allows you to narrow your tool searchquickly and intuitively to the unique tool you need to keep yourdevelopment on track. Browse and compare different solutionsand then conveniently and confidently purchase your tool forimmediate delivery from arrowdevtools.com on-line or throughArrow’s sales team. Arrowdevtools.com offers everything youneed to move your project rapidly to completion.

TestdriveSM c

Arrow’s Testdrive tool evaluation program helps you save timeand money on your designs. The program allows you to try toolsbefore you buy them, free of charge for 21 days. You can test avast selection of toolsfrom all the major semiconductor supplierswithout impacting yourbudget. Additionally,Arrow’s Field Applications Engineers are familiar with the toolsoffered through Testdrive and can work through any issues thatmay arise, saving you precious resources and giving you accessto some of the industry’s leading expertise.

Supply Chain Solutions c

For decades, Arrow has successfully managed one of the mostcomplex supply chains in the world, allowing us to offerunmatched insight and expertise. Our services, which includecollaborative material planning tools, vendor managed inventoryprograms, performance analysis services, materials managementprograms, and electronic communication services, can supportyour needs throughout a product’s entire lifecycle—from thetechnical discovery stage to design and prototype development,and through production and product end of life.

Custom Logic Solutions c

Arrow’s Custom Logic Solutions group has partnered withindustry leaders to meet your custom logic needs with theright combination of vendor technology, design services, andintellectual property.Solutions range fromsmall FPGAs tostructured ASICs, tohighly complex standard cell ASICs. More than 130 localengineers and over 20 factory Custom Logic Solutionsengineers, as well as integrated staff from Arrow’s network ofdesign services partners, provide comprehensive design servicesthat help you get to market quickly with the right product at thelowest possible risk and cost. Custom Logic Solutions alsoextends engineering support into the IP space, enabling youto piece together complex SOCs (Systems On A Chip) withouthaving to be “experts at everything.”

Global Programming Services c

More and more companies are relying on programmabledevices to improve performance, simplify design, reduce chipcount, and ease manufacturing. To help you keep up withconstant advances in technology, Arrow has developed GlobalProgramming Services to support procurement and the actualprogramming of your devices. Our services can give you greaterlevels of scheduling flexibility, reduce internal coordination andtracking, and avoid cost on capital equipment and staffing, toget you to market faster.

Access to comprehensive ARM offerings and leading suppliers is complemented by Arrow services that go far beyondgetting you the components you need. Our engineering services, on-line development tool selection process, complimentarydevelopment tool evaluation program, supply chain solutions, and custom logic solutions ensure the success of your designfrom concept to production.

Innovative Arrow Services

For information on Arrow’s Innovative Services, visit www.arrownac.com/arm or call 1-866-910-3650.

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ARM 32-Bit RISC Core with 16-Bit System Costs

The ARM7TDMI core is the industry’s most widely used 32-bit embedded RISC microprocessor. The ARM7TDMI-S is asynthesizable version of the ARM7TDMI. Optimized for cost- and power-sensitive applications, the ARM7TDMI solutionprovides the low power consumption, small size, and high performance needed in portable, embedded applications.

The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macrocell optimized to provide the bestcombination of performance, power, and area characteristics. The ARM7TDMI core enables system designers to buildembedded devices requiring small size, low power, and high performance.

The ARM7 family also includes the ARM7TDMI processor, the ARM7TDMI-S processor, the ARM720T processor, and theARM7EJ-S processor, each of which has been developed to address different market requirements.

RISC Advantages c

The ARM architecture is based on the Reduced Instruction SetComputer (RISC) principles. The RISC instruction set andrelated decode mechanism are much simpler than those of theComplex Instruction Set Computer (CISC) designs. Thissimplicity has the following advantages:

• A high instruction throughput

• An excellent real-time interrupt response

• A small, cost-effective, processor macrocell

The Instruction Pipeline c

• The instruction pipeline

• Memory access

• Memory interface

• EmbeddedICE

The Instruction Pipeline c

The ARM7TDMI core uses a pipeline to increase the speed ofthe flow of instructions to the processor. This allows severaloperations to take place simultaneously.

A three-stage pipeline is used, so instructions are executed inthree stages:

• Fetch (the instruction is fetched from memory)

• Decode (decoding of registers used in the instruction)

• Execute (register/s read from register bank; shift and ALU operations; write register/s back to register bank)

During normal operation, while one instruction is being executed,its successor is being decoded and a third instruction is beingfetched from memory.

ARM7TDMI and ARM7TDMI-S

Memory Access c

The ARM7TDMI core has a Von Neumann architecture with asingle 32-bit data bus carrying both instructions and data. Onlyload, store, and swap instructions can access data from memory.This simplifies the internal logic of the processor memory inter-face using less die area.

Memory Interface c

The ARM7TDMI processor memory interface has been designedto allow performance potential to be realized while minimizing theuse of memory. Speed-critical control signals are pipelined toallow system control functions to be implemented in standardlow-power logic. These control signals facilitate the exploitationof fast-burst access modes supported by many on-chip andoff-chip memory technologies.

AR

M7

TD

MI-

SHigh-performance

multiplier

ETM Interface

Bus Interface Unit

Control logic

EmbeddedICE-RT logic

32-bit ALU

Thumb decoder

Coprocessor�Interface

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EmbeddedICE-RT Logic c

The EmbeddedICE-RT logic provides integrated on-chip debugsupport for the ARM7TDMI core. You use the EmbeddedICE-RTlogic to program the conditions under which a breakpoint orwatchpoint can occur.

The EmbeddedICE-RT logic contains a Debug CommunicationsChannel (DCC), which is used to pass information between thetarget and the host debugger. The EmbeddedICE-RT logic iscontrolled through the Joint Test Action Group (JTAG) testaccess port.

On execution, 16-bit Thumb instructions are transparentlydecompressed to full 32-bit ARM instructions in real timewithout performance loss.

Performance Characteristics c

0.18 µm 0.13 µm 0.090 µm

Speed Optimized Speed Optimized Speed Optimized

Frequency* (MHz) 115 133 236

Area (mm2 ) 0.59 0.26 0.18

Power** (mW/MHz) 0.21 0.06 –

*Worst-case conditions—0.18 µm process—1.62V, 125°C, slow silicon; 0.13 µm process—1.08V, 125°C, slow silicon; 90 nm process—0.9V, 125°C, slow silicon **Typical-case conditions—0.18 µm process—1.8V, 25°C, typical silicon; 0.13 µm process—1.2V, 25°C, typical silicon; 90 nm process—1V, 25°C, typical silicon

Applications c

• Industrial• Automotive• Personal audio (MP3, WMA, and AAC players)

Features c

• 32-/16-bit RISC architecture (ARM v4T) • 32-bit ARM instruction set for maximum performance

and flexibility • 16-bit Thumb instruction set for increased code density • Unified bus interface; 32-bit data bus carries both

instructions and data • Three-stage pipeline • 32-bit ALU • Very small die size and low power consumption • Fully static operation • Coprocessor interface • Extensive debug facilities:

– EmbeddedICE-RT real-time debug unit – JTAG interface unit– Interface for direct connection to Embedded Trace

Macrocell (ETM)

Benefits c

• Generic layout can be ported to specific process technologies

• ARM and Thumb instruction sets can be mixed with minimal overhead to support application requirements forspeed and code density

• Small die size reduces overall SoC area, cost, and power consumption

• EmbeddedICE-RT and optional ETM units enable extensive, real-time debug facilities

Architecture c

The ARM7TDMI processor has two instruction sets:

• The 32-bit ARM instruction set• The 16-bit Thumb® instruction set

Having both 32-bit ARM instructions and 16-bit Thumbinstructions gives the ARM7TDMI processor two advantages:instruction compression and higher performance over typical16-bit architectures.

Microprocessor architectures traditionally have the samewidth for instructions and data. In comparison with 16-bitarchitectures, 32-bit architectures exhibit higher performancewhen manipulating 32-bit data and can access a large addressspace much more efficiently.

Typically, 16-bit architectures have higher code density than32-bit architectures, but they have approximately half theperformance.

The Thumb instructions implement a 16-bit instruction set on a32-bit architecture to provide:

• Higher performance than a 16-bit architecture• Higher code density than a 32-bit architecture

The Thumb instruction set is a subset of the most commonlyused 32-bit ARM instructions. Thumb instructions are each 16 bits long and have a corresponding 32-bit ARM instruction.This has the same effect on the processor model. Thumb instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and Thumb states.

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High-Performance and Low-Power Platform OS

The ARM9TDMI processor core is a Harvard architecture device implemented using a five-stage pipeline consisting offetch, decode, execute, memory, and write stages. It can be provided as a standalone core that can be embedded into more complex devices. The standalone core has a simple bus interface that allows you to design your own caches andmemory systems around it.

The ARM920T processor is a member of the ARM9TDMI family of general-purpose microprocessors, which includes:

• ARM9TDMI (core)

• ARM940T (core plus cache and protection unit)

• ARM920T (core plus cache and MMU)

ARM920T Application Support Features c

The ARM9TDMI family of microprocessors supports both the32-bit ARM and 16-bit Thumb® instruction sets, allowing you to trade off between high performance and high code density.

The ARM920T processor is a Harvard cache architectureprocessor that is targeted at multi-programmer applicationswhere full memory management, high performance, and lowpower are all-important. The separate instruction and datacaches in this design are 16 KB each in size, with an eight-wordline length. The ARM920T processor implements an enhancedARM architecture v4 MMU to provide translation and accesspermission checks for instruction and data addresses.

The ARM920T processor supports the ARM debug architectureand includes logic to assist in both hardware and softwaredebug. The ARM920T processor also includes support forcoprocessors, exporting the instruction and data buses alongwith simple handshaking signals.

The ARM920T’s interface to the rest of the system is overunified address and data buses. This interface enablesimplementation of an Advanced Microcontroller Bus Architecture(AMBA), an Advanced System Bus (ASB), or an AdvancedHigh-performance Bus (AHB) scheme either as a fully compliantAMBA bus master, or as a slave for production test. TheARM920T processor also has a Tracking ICE mode, whichallows an approach similar to a conventional ICE mode ofoperation.

The ARM920T processor supports the addition of an Embedded Trace Macrocell (ETM) for real-time tracing of instructions and data.

ARM920T

AR

M9

20

TARM9TDMI

core

Write buffer

ETM Interface

Control Logic and Bus Interface Unit

MMU

16KInstruction

cache

16KData

cache

MMU

AMBA AHB InterfaceCoprocessor

Interface

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Applications c

• Automotive infotainment

• Industrial connectivity

• Medical handheld

• Platform OS-based devices

• Next-generation smart phones, communicators, and PDA’s

• 3G baseband and applications processor

• Digital still camera

• Audio and video decoding

• Set-top box

Features c

• 32-/16-bit RISC architecture (ARMv4T)

• 32-bit ARM instruction set for maximum performance and flexibility

• 16-bit Thumb instruction set for increased code density

• MMU which supports operating systems including Symbian OS, Windows CE, Linux, and Palm OS

• Instruction and data caches: ARM920T = 16K/16K, ARM922T = 8K/8K

• Industry-standard AMBA bus interface

• ETM interface for real-time trace capability with ETM9

Benefits c

• Runs all major OS’s and existing middleware

• Single development toolkit for reduced development costs and shorter development cycle time

• Multiple sourcing from industry-leading silicon vendors

• Code-compatible upward migration path to ARM10E family

• Excellent debug support for SoC designers

• Instruction set can be extended by the use of coprocessors


0.18 µM 0.13 µM

Speed Optimized Speed Optimized

Frequency* (MHz) 190-200 230-250

Area with cache (mm2) 11.80 4.70

Cache size 16K/16K 16K/16K

Power with cache** (mW/MHz) 0.80 0.25

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon**Typical-case conditions—0.18 µm process–1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon

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ARM926EJ-S Jazelle-Enhanced Macrocell Processor

The ARM926EJ-S™ fully synthesizable processor features a Jazelle-enhanced 32-bit RISC CPU, flexible size instruction and data caches, Tightly Coupled Memory (TCM) interfaces, and a Memory Management Unit (MMU). It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for multi-layer AHB-based systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single-cycle MAC operations. The instruction set includes 16-bit fixed-point DSP instructions toenhance performance of many signal processing algorithms and applications as well as supports Thumb® and Java byte-code execution.

The ARM926EJ-S processor is a member of the ARM9 family ofgeneral-purpose microprocessors. The processor is targeted atmulti-tasking applications where full memory management, highperformance, small die size, and low power are all important.

The processor supports the 32-bit ARM and 16-bit Thumbinstruction sets, enabling the user to trade off between high per-formance and high code density. The ARM926EJ-S processorincludes features for efficient execution of Java byte codes, pro-viding Java performance similar to JIT, but without the associatedcode overhead.

The ARM926EJ-S processor supports the ARM debug architec-ture and includes logic to assist in both hardware and softwaredebug. The processor has a Harvard cached architecture andprovides a complete high-performance processor subsystem,including:

The ARM926EJ-S processor provides support for externalcoprocessors, enabling the addition of other floating-point orother application-specific hardware acceleration. The processorimplements ARM architecture version 5TEJ.

The ARM926EJ-S processor is a synthesizable macrocell. Thismeans that you can optimize the macrocell for a particular targetlibrary, and you can configure the memory system to suit yourtarget application. You can individually configure the cache sizesto be any power of two between 4 KB and 128 KB.

ARM926EJ-S

The tightly coupled instruction and data memories are instantiated externally to the ARM926EJ-S macrocell, providingyou with the flexibility to optimize the memory subsystem for performance, power, and particular RAM type. The TCM interfaces enable non-zero wait-state memory to be attached, as well as provide a mechanism for supporting DMA.

AR

M9

26

EJ

-S

ARM9EJ-Score

Write buffer

ETM9 Interface


MMU

Instructioncache

MMU

Datacache

DataTCM interface

InstructionTCM interface

AMBA AHB interfaceCoprocessor Interface Instruction Data

• An ARM9EJ-S integer core

• An MMU

• Separate instruction and data AMBA AHB bus interfaces

• Separate instruction and data TCM interfaces

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Applications c

• Automotive infotainment

• Audio and video decoding

• Platform OS-based devices

• Next-generation smart phones, communicators, and PDAs

• 3G baseband and applications processor

• Digital still camera

Features c

• 32/16-bit RISC architecture (ARMv5TEJ)



• DSP instruction extensions and single-cycle MAC

• ARM Jazelle technology

• MMU which supports operating systems including Symbian OS, Windows CE, and Linux

• Flexible instruction and data cache sizes

• Instruction and data TCM interfaces with wait-state support

• EmbeddedICE-RT logic for real-time debug

• Industry-standard AMBA bus AHB interfaces


• Optional MOVE coprocessor delivers video encoding performance

Benefits c

• Runs all major OS’s and existing middleware

• Single-chip MCU, DSP, and Java solution

• Support for leading Java run-times

• High-efficiency Java bytecode execution

• Ultra-low Java power consumption

• Java JIT compiler performance without the disadvantages

• Jazelle support code has no increase in VM size

• Simple single-processor software structure, no need for software partitioning across MCUs

• Single development toolkit for reduced development costs and shorter development cycle time


• Code-compatible upward migration path through to the latest cortex family of processors

• Process portable synthesizable design



• ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry-standard views and models


0.18 µM 0.13 µM 90 nm

Speed Optimized Speed Optimized A rea Optimized Speed Optimized A rea Optimized

Standard cells SAGE-X SAGE-HS SAGE-X Advantage-HS Metro

Memories HSHD HSHD HSHD Advantage Metro

Frequency* (MHz) 200 276 238 500 250

Area with cache (mm2) 6.5 2.78 2.39 1.55 0.85

Area without cache (mm2) 3 1.61 1.45 1.05 0.50

Cache size 8K/8K 8K/8K 8K/8K 8K/8K 8K/8K

Power with cache** (mW/MHz) – – 0.48 0.29 0.14

Power without cache** (mW/MHz) – – 0.36 0.24 0.11

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon **Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon

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Embedded Core with Flexible Memory System and DSP Instruction Set Extensions

The ARM966E-S processor is targeted at a wide range of embedded applications where high performance, low systemcost, small die size, and low power are all important. The ARM966E-S macrocell is a fully synthesizable 32-bit RISCprocessor aimed specifically at embedded hard real-time applications. The core implements the ARMv5TE instruction set and features an enhanced 16 x 32-bit multiplier capable of single-cycle MAC operations, and 16-bit fixed point DSPinstructions to accelerate signal processing algorithms and applications.

The ARM966E-S processor has separate, directly connectedinstruction and data Tightly Coupled Memory (TCM), which have flexible sizes and run at the processor clock speed. TheARM966E-S processor supports ARM’s real-time tracetechnology with the optional ETM9 Embedded Trace Macrocell.The ARM966E-S features a simple memory map providing anarea and power-efficient solution for applications that do notrequire complex memory management support. The coreincludes an AMBA AHB™ interface and a coprocessor interface for connection to application acceleration hardwaresuch as the VFP9-S floating-point coprocessor.

The ARM966E-S processor provides a high-performanceprocessor subsystem that includes the ARM9E-S RISC integerCPU core featuring:

• ARMv5TE 32-bit instruction set with improved ARM/Thumb code inter-working and enhanced multiplier designed for improved DSP performance

• ARM debug architecture with additional support for real-time debug; this enables critical exception handlers to execute while debugging the system

• Support for external TCM; a TCM interface is provided for each of the external instruction and data memory blocks; the TCM interfaces of the ARM966E-S processor enable high-speed operation without incurring the performance and power penalties of accessing the system bus, while having a lower area overhead than a cached memory system; the size of both the Instruction and Data TCM blocks are implementor-specific to enabletailoring of the hardware to the embedded application

• A simple fixed memory map for the local TCM, ideal for real-time embedded control applications

ARM966E-S

• An AMBA AHB bus interface

• Support for external coprocessors enabling floating-point or other application-specific hardware acceleration to be added

• Support for the use of a scan test methodology for the standard-cell logic and Built-In-Self-Test (BIST) for the TCM

Providing this complete high-frequency subsystem frees the SoCdesigner to concentrate on design issues unique to their system;the synthesizable nature of the device eases integration intoASIC technologies.

AR

M9

66

E-S

ARM9E core

Write buffer

ETM Interface


DataTCM interface

InstructionTCM interface

AMBA AHB interfaceCoprocessor Interface

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Applications c

• Automotive control: Powertrain with VFP9-S coprocessor

• Industrial control

• Mass storage devices: hard disc drives and DVD drives

• Networking systems

• Wireless devices

• Digital still cameras

Features c

• 32-/16-bit RISC architecture (ARMv5TE)



• Tightly Coupled Memories (TCMs)

• EmbeddedICE-RT logic for real-time debug

• Floating point capability with VFP9-S coprocessor


• ARM-Synopsys Reference Methodology compliant deliverables

• Optional MOVE coprocessor delivers video encoding performance

Benefits c

• Single-chip MCU and DSP solution

• Deterministic performance from TCM memories

• Simple single-processor software structure; no need for software partitioning across MCUs and eliminates multi-MCU debugging

• Single development toolkit: reduced development costs and shorter development cycle time

• Optimized for hard real-time applications


• Code-compatible upward migration path to ARM10E family



• ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry-standard views and models

Core area, frequency range, and power consumption aredependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisan standard-cell libraries and RAMs.

The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order toachieve a target area density.


0.18 µM 0.13 µM 90 nm

Speed Optimized Speed Optimized Speed Optimized A rea Optimized

Standard cells NA NA Advantage-HS Metro

Frequency* (MHz) 200 250 500 250

Area (mm2) 2 1 0.70 0.35

Power** (mW/MHz) 0.70 0.25 0.15 0.07

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon**Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon

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A High-Performance, Low-Power Processor with DSP and Media Extensions

The award-winning ARM1136J-S™ and ARM1136JF-S™ processors deliver up to 660 Dhrystone 2.1 MIPS in a 0.13 µmprocess. Both processors feature the ARM v6 instruction set with media extensions, ARM Jazelle® technology for efficientembedded Java execution, ARM Thumb® code compression, and an optional floating-point coprocessor. Media processingextensions offer up to 1.9x the acceleration of media-processing tasks such as MPEG4 encode.

Instruction and data cache sizes are configurable, and optional Tightly Coupled Memories (TCMs) can be added to accelerate interrupt handling and data processing. These processors feature AMBA® 2.0 AHB™ interfaces compatible with a wide range of system IP and peripherals. The ARM1136JF-S processor also features an integrated floating-pointcoprocessor, which makes it particularly suitable for embedded 3D-graphics applications.

The ARM1136JF-S processor incorporates an integer unit thatimplements the ARM architecture v6. It supports the ARM andThumb instruction sets, Jazelle technology to enable direct execution of Java bytecodes, and a range of SIMD DSPinstructions that operate on 16-bit or 8-bit data values in 32-bit registers.

The ARM1136JF-S processor is a high-performance, low-power,ARM cached processor macrocell that provides full virtual mem-ory capabilities.

Features c

• An integer unit with integral EmbeddedICE-RT logic

• An eight-stage pipeline

• Branch prediction with return stack

• Low-interrupt latency

• External coprocessor interface and coprocessors 14 and 15

• Instruction and Data Memory Management Units (MMUs),managed using MicroTLB structures backed by a unified Main TLB

• Instruction and data caches, including a non-blocking data cache with Hit-Under-Miss (HUM)

• The caches are virtually indexed and physically addressed, and have a 64-bit interface to both caches

• Level-one TCM that can be used as a local RAM with DMA, or as SmartCache

• High-speed Advanced Microprocessor Bus Architecture (AMBA) level two

• Vector Floating-Point (VFP) coprocessor support

In addition to the ARM1136J-S, ARM introduced a version thatincludes a VFP coprocessor. This is designated as theARM1136JF-S.

ARM1136J(F)-S

Core c

The ARM1136JF-S processor is built around the ARM11 core in an ARMv6 implementation that runs the 32-bit ARM, 16-bitThumb, and 8-bit Jazelle instruction sets. The processor containsEmbeddedICE-RT logic and a JTAG debug interface to enablehardware debuggers to communicate with the processor.

Registers c

The ARM1136JF-S core contains:

• 31 general-purpose 32-bit registers

• Seven dedicated 32-bit registers

AR

M1

13

6J

F-S

ARM1136J-Score

VFP

Memory Management

TCRAM

DataCache

InstructionCache

TCRAM

InstructionInterface

DataInterface

DebugInterface

CoprocessorController

DMA Peripheral Port

AR

M11

36J

(F)-

S

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Memory System c

The core provides a level-one memory system with the following features:

• Separate instruction and data caches

• Separate instruction and data RAMs

• 64-bit datapaths throughout the memory system

• Complete memory management

• 32-bit dedicated peripheral interface

Applications c

• Automotive infotainment: in-car entertainment, DVD players, and navigation equipment

• Networking: control processors in network infrastructure, switch, and router products

• Consumer: digital TVs, set-top boxes, game consoles, and handheld digital media players

Core area, frequency range, and power consumption aredependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisan standard-cell libraries and RAMs.

The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order toachieve a target area density.

The cache sizes are specified as InstructionCache/DataCache.The area without cache numbers quoted exclude RAM area, but include all logic including memory management, cache control, and debug. The area with cache numbers quotedincludes the core, the specified instruction and data caches, and all necessary RAMs.


90 nm

Speed Optimized A rea Optimized

Standard cells Advantage-HS Metro

Memories Advantage Metro

Frequency* (MHz) 620 320

Area with cache (mm2) 2.50 1.55

Area without cache (mm2) 1.80 0.90

Cache size 16K/16K 16K/16K

Power** with cache (mW/MHz) 0.45 0.24

Power** without cache (mW/MHz) 0.37 0.18

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon **Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon

Thumb Instruction Set c

Thumb is an extension to the ARM architecture. It contains asubset of the most commonly used 32-bit ARM instructions thathas been encoded into 16-bit wide opcodes, to reduce memoryrequirements.

DSP Instructions c

The ARM DSP instruction set extensions provide the following:

• 16-bit data operations

• Saturating arithmetic

• MAC operations

Multiply instructions are processed using a single-cycle 32x16implementation. There are 32x32, 32x16, and 16x16 multiplyinstructions (MAC).

Media Extensions c

The ARMv6 instruction set provides media instructions to com-plement the DSP instructions. The media instructions are dividedinto the following main groups:

• Additional multiplication instructions for handling 16-bit and 32-bit data, including dual-multiplication instructions that operate on both 16-bit halves of the source registers; this group includes an instruction that improvesthe performance and size of code for multi-word unsigned multiplications

• Instructions to perform Single Instruction Multiple Data (SIMD) operations on pairs of 16-bit values held in a single register, or on quadruplets of 8-bit values held in a single register; the main operations supplied are addition and subtraction, selection, pack, and saturation

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Processors for Complex OS and User Applications

The ARM Cortex™-A8 processor is the first applications processor based on the ARMv7 architecture and is the highest performance, most power-efficient processor ever developed by ARM. With the ability to scale in speed from 600 MHz togreater than 1 GHz, the ARM Cortex-A8 processor can meet the requirements for power-optimized mobile devices needingoperation in less than 300 mW and performance-optimized consumer applications requiring 2000 Dhrystone MIPS.

The ARM Cortex-A8 processor is ARM’s first superscalar processor featuring technology for enhanced code density andperformance, NEON™ technology for multimedia and signal processing, and Jazelle® RCT (Runtime Compilation Target)technology for efficient support of ahead-of-time and just-in-time compilation of Java and other bytecode languages.

The exceptional speed and power efficiency of the Cortex-A8processor is enabled by new ARM Artisan® Advantage-CElibraries supporting and implementing advanced leakage control.

The processor is supported by a wide range of ARM technologies for rapid system design including:

• The RealView® DEVELOP family of software development tools

• The RealView CREATE family of ESL tools and models • CoreSight™ debug and trace technology as well

as software library support through the OpenMAX multimedia processing standard

• AMBA® 3 AXI high-performance SoC interconnect

Architectural Features c

The ARM Cortex-A8 processor’s sophisticated pipeline architecture is based on dual, symmetric, in-order issue,13-stage pipeline with advanced dynamic branch predictionachieving 2.0 DMIPS/MHz.

• The in-order, dual-issue, superscalar microprocessor core includes:– 13-stage main integer pipeline – 10-stage NEON media pipeline – Dedicated Level 2 (L2) cache with programmable

wait states – Global-history-based branch prediction

• The processor works in conjunction with a power-optimized load store pipeline to deliver 2.0 DMIPS/MHz for power-sensitive applications

ARM Cortex-A8

• The ARM Cortex-A8 is ARMv7 architecture-compliant and includes:– Thumb®-2 technology for greater performance, energy

efficiency, and code density – NEON signal processing extensions to accelerate

media codecs such as H.264 and MP3 – Jazelle RCT Java-acceleration technology to optimize

Just In Time (JIT) and Dynamic Adaptive Compilation (DAC), and to reduce memory footprint by up to three times

– TrustZone technology for secure transactions and Digital Rights Management (DRM)

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Instruction and Data DMA arbitration

IFetch IDecode IExecute Load store

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| 19


• Integrated L2 Cache:– Built using standard compiled RAMs – Configurable size from 64K-2 MB – Programmable delay

• Optimized Level 1 (L1) Cache:– Performance- and power-optimized– Combines minimal access latency with hash way

determination to maximize performance and minimize power consumption

• Dynamic Branch Prediction:– Enabled by branch target and global-history buffers– Achieves 95% accuracy across industry benchmarks– Replay mechanism minimizes miss-predict penalty

• Memory System:– Single-cycle load-use penalty for access to

the L1 cache– Hash array in the L1 cache limits activation of the

memories to when they are likely to be needed– Direct interface between the integrated, configurable

L2 cache and the NEON media unit for data streaming– Banked L2 cache design that enables only one bank

at a time– Support for multiple outstanding transactions to the

Level 3 (L3) memory to fully utilize the CPU


65 nm

Speed Optimized

Frequency* (MHz) 600-800

Area with cache (mm2) < 4

Area without cache (mm2) < 3

Power with cache** (mW/MHz) < 0.5

*Core area, frequency range, and power consumption are dependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisanstandard-cell libraries and RAMs. Area is for core only (excluding NEON, Trace technology, and L2 cache). Frequency and power are for mobile applications. Frequency for consumer applications = 1 GHz. The speed-optimized implementations refer to the library choices and synthesisflow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density. **The 65 nm (LP) dynamic power measured is at 1.2V nominal and, hence, is higher than the 65 nm (GP) dynamic power, which is at 1.0V. However, the 65 nm (LP) leakage is significantly lower and this is the major consideration for mobile or battery-operated devices that need to conserve power in standby mode.

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Processors Optimized for Cost-Sensitive and Deeply-Embedded Applications

The ARM CortexTM-M3 processor has been developed to provide a high-performance, low-cost platform that meets theneeds of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstandingcomputational performance and exceptional system response to interrupts.

The ARM Cortex-M3 32-bit RISC processor executes purely Thumb®-2 instructions, delivering the high performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.

In addition to minimizing its memory requirement, the ARMCortex-M3 processor is also the smallest 32-bit core designedby ARM at just 33k gates for the central processing core(CM3Core) and 60k gates total, including many close systemperipherals. This design reduces silicon area requirements evenfurther, enabling the smallest of packages or the manufacturingof devices on low-cost processes, such as 0.35 µM and 0.25 µM.

The ARM Cortex-M3 processor also reduces the number of pinsrequired for debug from five to one, by implementing a newdebug interface technology—Single Wire Debug—that canreplace the current multi-pin JTAG port.

Outstanding Performance c

In addition to unparalleled performance, power consumption,and memory utilization, the ARM Cortex-M3 processor alsoachieves exceptional interrupt handling. By implementing theregister manipulations required for handling an interrupt inhardware, this core achieves minimal clock overhead on enteringinterrupts, and switches between pending or higher priority inter-rupts in only six cycles. The design, which comes with 32 interrupt channels as standard, can be configured to between 1 and over 240 channels.

The ARM Cortex-M3 processor also includes an optionalMemory Protection Unit (MPU) to provide a privileged modeof operation for complex applications.

ARM Cortex-M3

Enabling Technology c

The ARM Cortex-M3 processor has been designed “fromthe ground up” to provide optimal performance and powerconsumption within a minimal memory system. To achieve this,the core executes only the Thumb-2 instruction set, whichdelivers an unparalleled combination of ARM instruction setperformance with industry-leading code density. The design,which is based on a three-stage pipeline Harvard architecture,also maximizes memory utilization through the support ofunaligned date storage, and single-cycle atomic bit manipulation.

The exceptional performance of the ARM Cortex-M3 processoris achieved through a highly revised architecture that alsoimplements many new technologies in this type of core, suchas hardware divide and single-cycle multiply.

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| 21


Benefits c

The ARM Cortex-M3 processor offers significant benefits to system and software developers.

• Lower cost devices through smaller processing core, system, and memories

• Ultra-low power consumption and integrated sleep modes

• Outstanding processing performance for challenging applications

• Fast interrupt handling for critical control applications

• Platform security with optional integrated memory protection unit

• Enhanced system debug for faster development

• No assembler code requirement to ease system development

• Wide application envelope encompassing ultra-low-cost microcontrollers and high-performance SoC

Core area, frequency range, and power consumption aredependent on process, libraries, and optimizations. Thenumbers quoted above are illustrative of synthesized coresusing general-purpose TSMC process technologies and ARMArtisan® standard-cell libraries and RAMs. Area numbers includethe CM3Core, the Nested Vectored Interrupt Controller (NVIC),and Bus Matrix, but not the optional components including theMemory Protection Unit, Embedded Trace Macrocell, BreakpointUnit, Data Watchpoint Unit, and Trace Port Interface Unit.

The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made inorder to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order toachieve a target area density.


0.18 µM 0.13 µM

Speed Optimized A rea Optimized Speed Optimized A rea Optimized

Standard cells SAGE-X Metro SAGE-X Metro

Frequency* (MHz) 100 50 135 50

Area (mm2) 0.86 0.70 0.39 0.30

Power** (mW/MHz) 0.19 0.14 0.12 0.09

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon**Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon

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Embedded Processors for Real-Time Applications

The ARM Cortex™-R4 processor is the first deeply embedded processor to be based on the ARMv7 architecture and is targeted at very high-volume, deeply embedded applications such as hard-disk drives, inkjet printers, and automotivesafety systems.

The ARM Cortex-R4 processor provides key savings in cost and power consumption for system developers, offeringsubstantially higher performance than any other processor with similar die size. Along with the ARM1156T2-S and ARMCortex-M3 processors, the ARM Cortex-R4 processor completes comprehensive coverage for the diverse needs of theembedded microprocessor market. Furthermore, the ARM Cortex-R4 processor supports substantial synthesis timeconfigurability that enables designers to match the processor precisely to the application requirements.

In addition to the ARM Cortex-R4, ARM has introduced theARM Cortex-R4F, which contains a Floating Point Unit (FPU).The ARM Cortex-R4F processor’s FPU performs floating-pointcalculations that allow a greater dynamic range and accuracythan fixed-point calculations. The FPU is backward compatiblewith earlier ARM FPUs (VFP9/10/11), and is optimized for thesingle-precision processing most commonly used in automotiveand control applications. The FPU is particularly useful insophisticated control applications, where algorithms are oftenmodeled in an environment such as Simulink or ASCET-SD,and code is auto-generated using tools such as Real TimeWorkshop Embedded Coder, ASCET-SE, or dSPACE Targetlink.

The ARM Cortex-R4 processor is capable of running at clockspeeds of up to 400 MHz on typical 90 nm processes, and thefocus throughout the design is on efficiency and configurability.

Technical Innovations c

• Thumb®-2 technology; an innovation that has enabled partners to combine the minimal memory footprint of 16-bit Thumb code with the high performance of 32-bit ARM code

• AMBA 3 AXI protocol; a set of major enhancements to AMBA for high-performance on-chip interconnect, the ARM Cortex-R4 processor integrates a 64-bit master portas well as a 64-bit DMA port for direct access to the Tightly Coupled Memories (TCM)

• A selective superscalar eight-stage pipeline that provides more than 1.6 DMIPS/MHz in an efficient low gate count implementation

• Non-Maskable Interrupts (NMI); many real-time applications demand this and the ARM Cortex-R4 supports a configurable NMI pin

ARM Cortex-R4(F)

• CoreSight™ technology; a framework for complete system debug and trace; this includes the ETM-R4 embedded trace macrocell and many other CoreSight components

• A significantly improved local memory architecture for TCM and DMA; TCM can now be unified into a single logical address space and can run as fast as cache memory

• Enhancements over the ARMv6 architecture include improvements in interrupt handling and the memory protection scheme; new instructions for managing interrupts reduce the critical early-interrupt handler code,and the worst-case interrupt latency is vastly improved toonly 20 clock cycles

• Performance monitoring support; very useful for refining and tuning a system through advanced profiling of the system performance

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andInterface

InstructionCache

DataCache

AXI Master Interface AXI Slave Interface

DebugInterface VIC Port ETM Interface

FPU

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| 23


Core area, frequency range, and power consumption aredependent on process, libraries, and optimizations. Thenumbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARMArtisan standard cell libraries and RAMs.

The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made inorder to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order toachieve a target area density.

The cache sizes are specified as InstructionCache/DataCache.The area without cache numbers quoted exclude RAM area, but include all logic including memory management, cache control, and debug. The area with cache numbers quotedincludes the core, the specified instruction and data caches and all necessary RAMs.


0.13 µM 90 nm

Area Optimized Speed Optimized A rea Optimized

Standard cells SAGE-HS Advantage-HS Metro

Memories HS Advantage Metro

Frequency* (MHz) 300 500 210

Area with cache (mm2) 3.35 2.50 1.50

Area without cache (mm2) 1.99 1.66 0.80

Cache size 16K/16K 16K/16K 16K/16K

Power** with cache (mW/MHz) – 0.41 0.22

Power** without cache (mW/MHz) – 0.33 0.16

*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon**Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon

• Architected support for parity in the caches and parity or ECC in the TCMs; soft errors are an increasing concern inembedded systems and either parity or ECC is now essential in many systems

• A very efficient branch prediction and prefetch unit provide a branch accuracy of more than 90% for typical C code

• The overall aim of the ARM Cortex-R4 processor is to provide around 40% more efficiency than the ARM9 family whilst increasing the maximum clock speed, supporting the use of low-power, dense RAMs for cache and TCMs, and delivering an efficient Thumb-2 engine

Architectural Features c

The ARM Cortex-R4 processor’s sophisticated pipeline architecture is based on low-cost dual-issue pipeline, eightstages with advanced dynamic branch prediction achieving 1.6 DMIPS/MHz; the ARM Cortex-R4 processor is fully ARMv7 architecture-compliant and includes:

• Thumb-2 technology for greater performance, energy efficiency, and code density

• Hardware divide instructions for control applications

• Optimized level-one caches and TCM

• Synthesis optional cache controllers (with optional cacheparity) and TCM ports for flexibility

• Full wait and error support on TCM interfaces

• Flexible configuration at synthesis time of major level-one features

• A Memory Protection Unit (MPU) can be removed or an eight- or 12-region one selected

• Either one, two, or three TCM ports can be included

• A number of breakpoints and watchpoints can be selected

• Dynamic Branch Prediction- Enabled by branch target, global-history buffers,

and a function called return stack- Achieves 90% accuracy across industry benchmarks

• Single-cycle load-use penalty for access to the L1 cache and TCM

• A single 64-bit AXI master port for easy integration into the SoC interconnect

• An AXI slave port to allow direct access to TCMs by DMAcontrollers and other processors in the system

• Vectored Interrupt Controller (VIC) port for fast connection to interrupt management peripherals

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Designed to Enable High Performance, Low Power Consumption, and Systems Integration

The Intel XScale® core is based on an ARM processor family second-generation core and consists of innovative custom circuits, a proprietary design, and proprietary process techniques. This unique core enables processors in the Intel XScale® family to operate on very low current while in run and low-power modes.

Designed to enable high performance, low power consumption, and systems integration, the Intel XScale® core empowers OEMs to develop smaller, more cost-effective, handheld devices with longer battery life, while providing the performance to run MIPS-intensive multimedia applications such as audio encode/decode, video compression, and speech.

The Intel XScale® microarchitecture extends to set-top boxes, networking, intelligent I/O, and remote-access servers. This unique processor engine design affords a substantial leadership position in the handheld device market segment where high performance, low power, and integration-per-cost-effectiveness are all critical factors.

The Intel XScale® core targets the portable information devicesegment, which consists of feature-rich handheld devices suchas (but not limited to) the following:

• Vertical application devices

• Palm-size devices

• Smart phones/3G+ multimedia phones

• PC companions

The processor is also packaged in a “smaller footprint, lowercost” version focused on handheld and portable applications,and a “higher performance” version for the PC companion andvertical application device segments. In addition to handheldsegments, the Intel XScale® core also provides a market entry to tethered applications such as screen phones, low-end set-top boxes, web terminals, and other Internet appliances.

Features and Benefits of Intel XScale®

Microarchitecture c

• Superpipelined RISC technology achieves high speed and ultra-low power with a seven-stage integer/eight-stage memory superpipelined core

• Dynamic voltage management obtains the right blend of performance and power with dynamic voltage and frequency scaling “on the fly”

• Media processing technology achieves efficient media processing with a multiply-accumulate coprocessor that performs two simultaneous 16-bit SIMD multiplies with 40-bit accumulation

Intel XScale®

• Power management unit saves power with idle, sleep, and quick wake-up modes

• 128-entry branch target buffer maintains pipeline capacity with statistically correct branch choices

• 32 KB instruction cache achieves high performance and low power consumption levels by keeping a local copy ofimportant instructions

• 2 KB data cache avoids “thrashing” of the data cache forfrequently changing data streams

• 32-entry instruction memory management unit enables logical-to-physical address translation, access permissions, and instruction-cache attributes

• Four entry fill and pend buffers obtain core efficiency by allowing non-blocking and “hit-under-miss” operation with data caches

• Performance monitoring unit analyzes hit rates with two 32-bit event counters and one 32-bit cycle counter

• Debug unit debugs programs with hardware breakpoints and a 256-entry trace-history buffer (for flow change messages)

• 32-bit coprocessor interface achieves a high-performance interface between the core and coprocessors

• 64-bit core memory bus with simultaneous 32-bit input path and 32-bit output path obtains up to 4.8 GBytes/sec@ 600 MHz bandwidth for internal accesses

• Eight-entry write buffer provides continuous core execution while data is written to memory

• The Thumb instruction set supported selects the 16-bit Thumb instruction set from the current program status register

| 25


ARM Architecture Compatibility c

The Intel XScale® microarchitecture implements the integerinstruction set architecture specified in ARM Version 5TE. “T” refers to the Thumb instruction set, and “E” refers to the DSP-enhanced instruction set.

ARM Version 5 introduces a few more architecture features overVersion 4, specifically the addition of tiny pages (1 Kbyte), a newinstruction (CLZ) that counts the leading zeroes in a data value,enhanced ARM-Thumb transfer instructions, and a modificationof the system-control coprocessor, CP15.

ARM DSP-Enhanced Instruction Set c

The Intel XScale® microarchitecture implements the ARM DSP-enhanced instruction set, which is a set of instructions that boosts the performance of signal-processing applications.New multiply instructions operate on 16-bit data values, and new saturation instructions are available as well (see below).

• SMLAxy instruction is a 16x16+32 with a 32-bit result

• SMLAWy instruction is a 32x16+32 with a 32-bit result

• SMLALxy instruction is a 16x16+64 with a 64-bit result

• SMULxy instruction is a 16x16 with a 32-bit result

• SMULWy instruction is a 32x16 with a 32-bit result

• QADD adds two registers and saturates the result if an overflow has occurred

• QDADD doubles and saturates one of the input registers and then adds and saturates the result

• QSUB subtracts two registers and saturates the result if an overflow has occurred

• QDSUB doubles and saturates one of the input registers and then subtracts and saturates the result

Extensions to ARM Architecture c

The Intel XScale® microarchitecture includes a few extensions tothe ARM Version 5 architecture to meet the needs of variousmarkets and design requirements. The following is a list of theextensions that are discussed in the next subsections.

• A DSP coprocessor (CP0) has been added that contains a 40-bit accumulator and eight new instructions

• New page attributes were added to the page table descriptors; the C- and B-page attribute encoding was extended by one additional bit to allow for more encodings: write-allocate and mini-data cache; an attribute specifying ECC for 1 MB regions was also added

• Additional functionality has been added to coprocessor 15; coprocessor 14 also added

• Enhancements were made to the event architecture, instruction cache, and data-cache parity

DSP Coprocessor 0 (CP0) c

The Intel XScale® microarchitecture adds a DSP coprocessor to the architecture for increasing the performance and the precision of audio-processing algorithms. This coprocessor contains a 40-bit accumulator and eight new instructions.

The 40-bit accumulator is referenced by several new instructionsthat were added to the architecture; MIA, MIAPH, and MIAxy are multiply/accumulate instructions that reference the 40-bitaccumulator instead of a register-specified accumulator. MARand MRA read and write the 40-bit accumulator.

Access to CP0 is always allowed in all processor modes whenbit 0 of the coprocessor access register is set. Any access toCP0 when this bit is clear will cause an undefined exception.Note that only privileged software can set this bit in thecoprocessor access register. Two new instruction formats were added for coprocessor 0: multiply with internal accumulate format, and internal accumulate access format.

Branch Prediction c

The Intel XScale® microarchitecture implements dynamic branch prediction for the ARM instructions B and BL, and for the Thumb instruction, B. Any instruction that specifies the PC as the destination is predicted as “not taken.” For example,an LDR or an MOV that loads or moves directly to the PC will be predicted “not taken” and incur a branch-latency penalty.

These instructions (ARM B, ARM BL, and Thumb B) enter intothe branch target buffer when they are “taken” for the first time.(A “taken” branch refers to when they are evaluated to be true.)Once in the branch target buffer, the Intel XScale®

microarchitecture dynamically predicts the outcome of theseinstructions based on previous outcomes. A penalty of “zero” for correct prediction means that the Intel XScale®

microarchitecture can execute the next instruction in the program flow in the cycle following the branch.

Power Management c

The Intel XScale® microarchitecture defines three low-powermodes: idle, drowsy, and sleep. All state information is lost onentering sleep mode. The only way to exit sleep mode is throughthe reset sequence. State is retained in idle and drowsy modes.Both idle and drowsy modes are exited by interrupt, even if theinterrupt is masked. A single coprocessor 14 register write isused to enter any low-power mode.


1-866-910-3650

i.MX31 Multimedia Applications ProcessorsCore: ARM1136JF-S™

i.MX31 Block Diagram

The popular i.MX31 and i.MX31L multimedia applications processors are developedwith Freescale’s Smart Speed Technology to drive high performance applications atvery low power for extended battery life. The entire portfolio of i.MX processors offersa range of performance and price levels, on chip integration, and broad connectivityoptions. i.MX processors also have one of the best power-to-performance ratios ofany processor in their class. They are becoming the applications processors of choicefor portable media players, smartphones, automotive infotainment systems, V2IPphones, video surveillance systems, and many other devices. Freescale providesboard support packages (BSPs) to simplify and support development on leadingoperating systems and RTOSes. Freescale is a Gold-level Microsoft Windows

Embedded Partner and offers BSPs for the three most recent Windows CE releases (4.2, 5.0, 6.0) Windows Mobile 5.0 and the new Windows Mobile 6. The i.MX portfolio continues to grow, and new processors will be shipping inproduction this year.

34 |

Features c

• CPU complex with L2 cache, vector floating point co-processor, and Smart Speed switch

• Smart power management including support for multiple low powermodes, dynamic voltage frequency scaling, and dynamic process temperature compensation

• External memory interface with support for multiple types of memory

• Smart multimedia with support for hardware accelerated MPEG4 encode, as well as pre & post processing

• Display port with ability to support a variety of popular display devices and up to two displays simultaneously

• Sensor port which provides connection to either one or two image sensors

• System connectivity, including USB high speed OTG, CSPIs, I2C, PCMCIA, ATA, UARTs

• 2D/3D graphics acceleration (only available on i.MX31) • Board support packages for the major operating systems

Benefits c

• High performance with 32-bit DDR and L2 cache• Long battery life for mobile applications• Ability to boot from NAND flash• MPEG4 playback at 30 fps VGA resolution• Interactive console-like gaming experience with OpenGL-ES based

graphics acceleration• On chip LCDC eliminates the need for timing chips when using

certain displays• Capture, process, and display of moving and still objects• High level of integration simplifies overall board design and

lowers BOM cost


For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650. To research and compare and contrast ARM solutions, visit www.embedded-developer.com.

i.MX31 Application Development Systemi.MX31 Lite Kit

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i.MX31 Multimedia Applications Processors | Freescale Semiconductor

Family Comparative Features c

Part Temp °C Package Core Max Timer Timer Serial Interface USB PeripheralsNumber Type Variant ID Frequency Channels Bits Description

MCIMX31VKN5B 0 to +70 MAPBGA 457 ARM1136JF-S 532 2 32 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port, 2D/3D graphics accelerator

MCIMX31LVKN5B 0 to +70 MAPBGA 457 ARM1136JF-S 532 2 32 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port

MCIMX31CVKN5C -40 to +85 MAPBGA 457 ARM1136JF-S 532 2 32 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port, 2D/3D graphics accelerator

MCIMX31LCVKN5C -40 to +85 MAPBGA 457 ARM1136JF-S 532 2 32 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port

Development Tools Matrix c

Tool Name Description Part Number

i.MX31 ADS Complete hardware development system with power management board and included features such as LCD, camera, and board support packages MCIMX31ADSE

i.MX31 Lite Kit Low-cost development kit for basic evaluation and application development; peripheral accessories and software available separately MCIMX31LITEKIT


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Intel® Network Processors and Intel® I/O ProcessorsCore: Intel XScale® Technology

Intel ® IXP46X Product Line Block Diagram

Intel XScale® Technology is available in two families: The Intel® network processors familyand the Intel® I/O processors family of devices. With a single architecture and integrateddesign, the Intel® IXP4XX product line of network processors delivers scalable performance,reduced power, and lower cost in packages optimized for residential and small/mediumenterprise network applications, as well as communications-based embedded applications.Many storage, networking, and embedded applications require fast I/O throughput for optimal performance. Intel® I/O processors (IOP) allow applications to transfer data faster,reduce communication bottlenecks, and improve overall system performance.

NPE B1 MII or

Quad SMII

Bridge

InterruptController

Timers

Memory Port Interface

Cryptography UnitEAI, SHA

I2C SSP Intel XScale® Core266/400/533/667 MHz32 KB Data Cache32 KB Instruction Cache2 KB Mini-Data Cache

DDR1-266Controller

MII/SMII

Bridge

66.66 MHz Advanced Peripheral Bus

UTOPIA-2/MII/SMII

MII/Quad SMII

PMU(AHB)

IEEE 1588

133.32 MHz Advanced High-Performance Bus

NPE CMII/SMII

AES, DESSHA-1/-256/

-384/-512, MO5

NPEAMII/SMII

UTOPIA, AAL,HSS, HDLC

133.32 MHz Advanced High-Performance Bus

Queue Flag Bus

HW RNG

Queue Manager8KB SRAM

32-bit +ECC

Bus Interface Unit

USBHost 2.0**

PCI Controller

Expansion BusController

UART921KBaud

UART921KBaud

GPIOController

USBDevice v1.1

16G

PIO

32-bit

32-bit+P

arity

HS

S-0

HS

S-1

**USB 2.0 Host supports low-speed (1.5 Mb/s) and full-speed (12 Mb/s) modes.

36 |

Features c

• Intel XScale® Microarchitecture running at up to 667 MHz• Intel® network processors: Peripherals - USB, up to 3 10/100

Ethernet MACs, PCI, DDR, Expansion Bus, UARTs, I2C, SSP• Intel® network processors: Advanced Serial Interfaces including

a high speed serial port for connecting to T1/E1 or SLICs/CODECs; UTOPIA-2 Support;

• Intel® network processors: Integrated support for cryptography, time synchronization and ECC memory

• Intel® I/O processors: Integrated Designs• Intel® I/O processors: I/O Processing Performance• Comprehensive Set of Development Tools

Benefits c

• Intel’s groundbreaking new microarchitecture provides very high processor performance with extremely low power consumption; Intel XScale® technology provides the platform for the most advanced designs in storage, infrastructure and embedded communications

• Provides reduced overall system cost as well as ease of connectivity to industry standard peripherals/devices

• Support for voice applications and connection to industry standard WAN interface

• Improves performance and reliability• I/O processors are available in single- or dual-chip configurations

this provides developers with pre-validated component sets, simplified board designs, and board-space cost savings

• Offloads I/O processing functions, such as I/O interrupt processingand parity calculations from a host processor; I/O processors are also excellent general-purpose processors for high-bandwidth applications that require integrated processors with low power consumption and high-speed peripherals

• Faster time-to-market and support for multiple tool-chains and operating systems on the Intel XScale® microarchitecture



The IQ81342MC board features a 1.2GHZ two core Intel®

IOP342 I/O processors processor. This board has dual UARTs,Dual Gbit Ethernet and a x8 PCI Express slot and a 64-bit PCI-X

slot for expansion, and fits in a standard flex-ATX chassis.

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Intel® Network Processors and Intel® I/O Processors | Intel®


Part Tota l Temp °C Package Core Max A/D A/D Timer Timer Serial Interface GPIO Ethernet USB PeripheralsNumber RAM Type Variant ID Frequency Bits Channels Channels Bits Description

IXP43X eternal up to 1 GB -0 to +70 PBGA XScale 667 0 – 4 32 High Speed UART, SSP/SSI, I2C 16 2 x 10/100 2x2.0 HS Host DDR I/II, 32-bit 33 MHz PCI, 16-bit Expansion Bus, UTOPIA 2,DES/3DES/AES/SHA 1/SHA256/384/512, IEEE 1588

IXP42X eternal up to 256 MB -40 to +85 PBGA XScale 533 0 – 4 32 2 High Speed UARTs 16 2 x 10/100 1x1.1 Device SDRAM, 32-bit 33 MHz PCI, 16-bit Expansion Bus, SHA-1/MD5/ES/DES,/AES

80219 eternal up to 1 GB 0 to +55 FCBGA5 XScale 800 0 0 3 32 2xI2C 8 – – PCI, DDR

IOP331/2 eternal up to 2 GB 0 to +95 FCBGA5 XScale 800 0 – 3 32 2xUARTs, 3xI2C 8 – – PCI-X/PCIe, DDRII, 266 MHz 64-bit internal bus

IOP333 eternal up to 2 GB 0 to +95 FCBGA5 XScale 800 0 – 3 32 2xUARTs, 3xI2C 16 – – PCI-X/PCIe, DDRII, 333 MHz 64-bit internal bus

IOP348 eternal up to 2 GB 0 to +95 FCBGA5 XScale 1200 0 0 3 32 2xUARTs, 3xI2C 16 – – PCI, PCIe, SAS/SATAII, DDII

IOP341/2 eternal up to 2 GB 0 to +95 FCBGA5 XScale 1200 0 – 3 32 2xUARTs, 3xI2C 16 – – PCI-X/PCIe, 1 or two XScale processor cores, DDRII, 400 MHz128-bit internal bus

IXP46X eternal up to 1 GB -40 to +85 PBGA XScale 667 0 – 4 32 2 High Speed UARTs 16 3 x 10/100 1.1 Device, 2.0 DDR I, 32-bit 33 MHz PCI, 32-bit Expansion Bus, FS HostSSP/SSI, I2C UTOPIA 2, DES/3DES/AES/SHA1/ SHA256/384/512, IEEE 1588



Intel® IXDP465 Development Platform Intel® IXDP465 Development Platform, optional T1/E1, Voice, and Ethernet Modules; includes 4 PCI expansion slots, 3 Ethernet ports, USB host and device, 2 UARTS KIXDP465AD

Intel® IXDP425 / IXCDP1100 Development Platform Intel® IXDP425 / IXCDP1100 Development Platform, Network processor base card with the Intel® IXP425 network processor at 533 MHz, Two Intel® LXT972A LAN PHY expansion cards, KIXDP425BDOne ADSL PHY expansion card, One voltage regulator expansion card, Two High-Speed Serial (HSS) ports, Two UART (DB-9) connectors, One USB connector, Four PCI bus connectors

Intel® KIXRP435 Development Platform Intel® KIXRP435 Development Platform Includes 10/100 802.11a/g WLAN, 3x10/100 Ethernet, 2 Wideband FXS + 1 FXO, 2xUSB 2.0, UART, IR, RCA, Audio, Component Video, S-Video KIXRP435 - Hamoa

Intel® IQ80332 Software Development Features Intel® 82545EM Gigabit Ethernet Controller, Primary PCI- PCI Express* supports up to x8 lane, Secondary PCI is PCI-X, two UARTs, Two 7-segment hex LED displays in a dPCI IQ80332and Processor Evaluation Kit Express form factor

Intel® IQ80219 Development Kit Intel® IQ80219 Development Kit featuring a primary PCI-X interface 133 MHz/64-bit or PCI 66 MHz/64-bit, Two Intel® 31244 Serial ATA I/O controllers, Intel® BW31154 PCI 133 MHz IQ80219.DOMtransparent bridge,256MB DDR SDRAM with ECC, one PCI-X 64-bit/100 MHz expansion slot

Intel® EP80219 Development Intel® EP80219 Development Kit features a 10/100 Ethernet controller, one GD31244 SATA controller, a serial port, and a mini-PCI connector for expansion, RTC, Power control, EP80219and Temp Sensor

Intel, the Intel logo, and Intel XScale are trademarks or registered trademarks of Intel Corporation or itssubsidiaries in the United States and other countries. *Other names and brands may be claimed as theproperty of others.


1-866-910-3650

LPC210x 70 MHz, 32-bit microcontroller withARM7TDMI-SCore: ARM7TDMI-S

LPC210x Block Diagram

These powerful yet cost-effective microcontrollers have up to 32 KB of zero wait-state Flash and up to 8 KB of SRAM. Each has a 10-bit A/D converter with eight channels and multiple serial interfaces.

The lowest-priced part, the LPC2101, starts at only USD $1.47 each for 10 Kpcs,making it an attractive alternative to lower performing 8- or 16-bit MCUs. Blending

high performance (63 Dhrystone MIPs) with low power consumption in a tiny 7 mm x 7 mm LQFP48 package makes thepart ideal for almost any application.

These cost-effective processors are stuffed with a variety of peripherals, including 10-bit ADCs, 4 timers, and multiple I2C, SPI, and UART interfaces. The series also features several new power-saving modes and fast general-purpose I/O,allowing more flexibility for designers. The code and peripherals are fully compatible with all of the other members of the NXP LPC2000 family, which has nearly 40 members and continues to grow.

40 |

Features c

• 70-MHz, 32-bit ARM7 Core Architecture with AHB/APB interfaces• Up to 32 KB of zero wait-state Flash• Fast 70 MHz performance at 63 Dhrystone MIPs• Tiny 7mm x 7mm LQFP packaging• Stuffed with low-power features and advanced peripherals• Incredibly low pricing starting at $1.47

Benefits c

• Ideal upgrade for any application using lower performance 8- or 16-bit MCUs

• Ideal for almost any application• Design flexibility



MCB2103 Keil Evaluation Board

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NXP Family of Microcontrollers | NXP



MCB2103 evaluation board from Keil The evaluation board connects to your PC using the serial port (for flash download with the NXP LPC2000 FLASH Utility) or the JTAG interface; it can be powered from a USB connector MCB2103(50mA typical) or from a 5V to 9V DC power supply; debugging is supported via the JTAG interface using the Keil ULINK USB-JTAG adapter and the _Vision IDE and Debugger


Part Tota l Tota l Temp. °C Package Core Max A/D A/D Timer Timer Serial Interface GPIO Ethernet USB PeripheralsNumber Flash RAM Type Variant ID Frequency Bits Channels Channels Bits Description

LPC2101 8 2 -40 to +85 LQFP48 ARM7TDMI-S 70 10 8 7 32 2xUART, SPI, SSP 32 – – –




1-866-910-3650

LPC23xx and LPC24xx 72 MHz, 32-bitmicrocontrollers with ARM7TDMI-S coreCore: ARM7TDMI-S

The LPC23xx and LPC24xx use a high-performance 32-bit ARM7 core that operatesat up to 72 MHz. Each device has 512 KB of on-chip Flash. The LPC23xx offers up to 58 KB of SRAM, while the LPC24xx offers up to 98 KB of SRAM. Both deviceshave two AHB buses, so high-bandwidth peripherals like Ethernet and USB can runsimultaneously, without impacting the main application. The LPC24xx is also the onlyARM7 MCU with two-port USB capability; it has one USB device, and one USB

Host or OTG. This unique ability enables new advances for multiple communications applications by supporting com-pound (Host + device) USB functionality, such as a USB mini-hub.

42 |

Features c

• On-chip RC-oscillator 4 Mhz trimmed to 1%• Four 32-bit general purpose timers• PWM block supporting 3-Phase Motor Control• Watchdog timer from multiple clock source options• 10-bit A/D converter and 10-bit D/A converter• Low-power Real Time Clock with 2 KB SRAM and

battery back-up• General Purpose DMA controller • High-speed Serial: I2S (digital Audio), three I2C,

three SPI/SSP, four UARTs

Benefits c

• Allows fast simultaneous communications operations• Eliminates communication bandwidth bottlenecks• Design flexibility

LPC24xx Block Diagram



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Keil MCB2300 Evaluation Boards The Keil MCB2300 Evaluation Boards introduce you to the NXP LPC23xx series of ARM microcontrollers and allow you to create and test working programs for this advanced architecture; MCB2300two versions of the board are available: the MCB2360 for the 100-pin LPC2368 and the MCB2370 for 144-pin LPC2378

Keil RealView Microcontroller Development Kit The RealView Microcontroller Development Kit (MDK) supports the LPC24xx family of microcontrollers from NXP; this kit is perfect for the developer who requires industry-standard compilation MDK-ARMtools and sophisticated debugging support

Keil ULINK2 The Keil ULINK2 USB-JTAG Adapter connects your PC's USB port to your target hardware (via JTAG, SWD, or OCDS) and allows you to debug embedded programs running on target hardware; ULINK2ULINK2 offers all the features of the original ULINK USB-JTAG Adapter and adds serial wire debug (SWD) support, return clock support, and a real-time agent; ULINK2 works with standard Windows USB drivers


Part Tota l Tota l Temp.°C Package Core Max A/D A/D Timer Timer Serial Interface GPIO Ethernet USB PeripheralsNumber Flash RAM Type Variant ID Frequency Bits Channels Channels Bits Description

LPC2468FET208 512 98 -40 to +85 TFBGA208 ARM7TDMI-S 72 10 8 4 32 2xSSP, I2S, 4xUART, 3xI2C – 10/100 2.0 FS, OTG 2xCAN

LPC2468FBD208 512 98 -40 to +85 LQFP208 ARM7TDMI-S 72 10 8 4 32 2xSSP, I2S, 4xUART, 3xI2C – 10/100 2.0 FS, OTG 2xCAN

LPC2378FBD144 512 58 -40 to +85 LQFP144 ARM7TDMI-S 72 10 8 4 32 SPI, 2xSSP, I2S, 4xUART, 3xI2C – 10/100 2.0 FS, OTG 2xCAN

LPC2368FBD100 512 58 -40 to +85 LQFP100 ARM7TDMI-S 72 10 8 4 32 SPI, 2xSSP, I2S, 4xUART, 3xI2C 70 10/100 2.0 FS, OTG 2xCAN

LPC2366FBD100 256 58 -40 to +85 LQFP100 ARM7TDMI-S 72 10 8 4 32 SPI, 2xSSP, I2S, 4xUART, 3xI2C 70 10/100 2.0 high speed OTG + 2 hosts 2xCAN

LPC2364FBD100 128 34 -40 to +85 LQFP100 ARM7TDMI-S 72 10 8 4 32 SPI, 2xSSP, I2S, 4xUART, 3xI2C 70 10/100 2.0 high speed OTG + 2 hosts 2xCAN


1-866-910-3650

LPC2478 72 MHz, 32-bit ARM-based microcontroller with integrated LCD supportCore: ARM7TDMI-S

LPC247x Block Diagram

These innovative and cost-effective microcontrollers support concurrent operations of high-bandwidth peripherals with significant power savings. The large array ofperipherals supported by these devices in addition to the LCD interface include10/100 Ethernet, USB host/OTG/device, two CAN channels, four UARTs, three I2C buses, two-input and two-output I2S, SPI, SSP, RTC, ADC/DAC, SD/MMC card interface, external interfaces to SRAM, SDRAM and NOR Flash.

The LPC2478 microcontroller is the industry’s only ARM7 Flash-based MCU offering integrated LCD support as well as a Flashless version, the LPC2470.

44 |

Features c

• 72-MHz, 32-bit ARM7 core with dual AHB interfaces• 512 KB of fast 128-bit wide embedded Flash (LPC2478 only)• LCD interface• 10/100 Ethernet MAC interface with DMA• USB 2.0 full-speed OTG/Device/OHCI plus PHY and DMA• Two CAN 2.0B controllers with acceptance filtering• External interfaces to SRAM, SDRAM, and NOR Flash• 10-bit A/D converter and 10-bit D/A converter

Benefits c

• Significant savings in cost, area, and power consumption• Ideal for a wide range of industrial, consumer, retail and

medical systems using LCD panels and requiring network or Internet connectivity

• LCD implementation allows code execution on-chip



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Keil RealView Microcontroller Development Kit The RealView Microcontroller Development Kit (MDK) supports the LPC24xx family of microcontrollers from NXP; this kit is perfect for the developer who requires industry-standard MDK-ARMcompilation tools and sophisticated debugging support

Keil ULINK2 The Keil ULINK2 USB-JTAG Adapter connects your PC's USB port to your target hardware (via JTAG, SWD, or OCDS) and allows you to debug embedded programs running on target ULINK2hardware; ULINK2 offers all the features of the original ULINK USB-JTAG Adapter and adds serial wire debug (SWD) support, return clock support, and a real-time agent; ULINK2 works with standard Windows USB drivers



LPC2470FBD208 0 98 -40 to +85 LQFP208 ARM7TDMI 72 10 8 4 32 4xUART(1xIrDA), 2xCAN, 160 1 1 LCD (1024x768), 10/100 with MII/RMII and DMA, 2.0/OTG SPI, 2xSSP, 3xI2C, I2S USB 2.0/OTG w/PHY and DMA, SD/MMC

LPC2470FET208 0 98 -40 to +85 TFBGA208 ARM7TDMI 72 10 8 4 32 4xUART(1xIrDA), 2xCAN, 160 1 1 LCD (1024x768), 10/100 with MII/RMII and DMA, SPI, 2xSSP, 3xI2C, I2S USB 2.0/OTG w/PHY and DMA, SD/MMC

LPC2478FBD208 512 98 -40 to +85 LQFP208 ARM7TDMI 72 10 8 4 32 4xUART(1xIrDA), 2xCAN, 160 1 1 LCD (1024x768), 10/100 with MII/RMII and DMA, SPI, 2xSSP, 3xI2C, I2S USB 2.0/OTG w/PHY and DMA, SD/MMC

LPC2478FET208 512 98 -40 to +85 TFBGA208 ARM7TDMI 72 10 8 4 32 4xUART(1xIrDA), 2xCAN, 160 1 1 LCD (1024x768), 10/100 with MII/RMII and DMA, SPI, 2xSSP, 3xI2C, I2S USB 2.0/OTG w/PHY and DMA, SD/MMC


1-866-910-3650

STR7 and STR9 FamiliesCore: ARM7TDMI, ARM966E-S

STR7 and STR9 Portfolio Diagram

STMicroelectronics brings the power of 32-bit ARM® processor cores to the worldof microcontrollers, opening endless opportunities to embedded system designersby making control and connectivity applications easy and affordable. With a widerange of embedded memories, peripherals and architectural enhancements, ST'sSTR7 and STR9 families help scale designs to achieve the best fit for an applica-tion. STR7 and STR9 families address needs, from low-end to high-performance,with a common set of tools and software, thus reducing cost and time to market.

46 |

Features c

STR710 ARM7 • Performance up to 45 MIPs @ 50 MHz, 3.0 to 3.6V,

and -40 to +85°C• STR7’s biggest RAM (64 KB)• The most UARTs (4)• External memory interface• Peripherals include CAN, USB, 4xUARTs,

and SC interface (ISO7816)• Consumer and industrial applications

STR730 ARM7 • Performance up to 32 MIPs @ 36 MHz, 4.5 to 5.5V,

and -40 to +85°C, or up to +105°C• The most timers (20)• The most CANs (3), UARTs (4), and the most I/Os (112)• Peripherals include 3xCANs, 4xUARTs, and up to 20 timers, 16 DMA• Industrial and automotive related applications

STR750 ARM7 • Performance up to 54 MIPs @ 60 MHz, 3.0 to 3.6V or 4.5 to 5.5V,

and -40 to +85°C, or up to +105°C• The best integration and balanced control/communication• Safety and low power• Unique motor control peripherals• Suitable for many general-purpose applications• Peripherals include CAN, USB, 3xUARTs, and advanced timers• General-purpose and vector drive applications

STR910 ARM9E • Performance up to 96 MIPs @ 96 MHz, 2.7 to 3.6V I/O,

1.8V core, and -40 to +85°C• Highest performance (96 MHz ARM9E)• Largest Flash/RAM memory size (544 KB/96 KB)• Ethernet connectivity• Designed to complement STR7 for bigger memory, higher

performance and Ethernet connectivity• Binary compatible with ARM7TDMI core code• Peripherals include Ethernet, USB, CAN, and 3xUARTs• Performance and connectivity applications

STR730FCore: ARM7TDMI

STR730F Block Diagram

STR730F Flash microcontrollers combine the industry standard ARM7TDMI® RISC microprocessor with embedded Flash and powerful peripheral functions, including up to 20 timers, 4xUARTs and 3xCANs. The STR730F MCUs are ideal for embeddedapplications requiring a compact yet powerful MCU, as well as versatile, scalablesolutions such as user interfaces, factory automation systems and appliances.Additionally, the STR730F family features a single 5V power supply particularly suited to industrial applications.

Features c

• Largest choice of peripherals and interfaces including 4xUART, up to 20 timers and up to 3xCAN

• Flexible power and clock management• Five low-power modes• Low-power voltage regulator• Extensive software and tools including the complete

STR7 library supporting all standard peripherals and CAN• Dual APB buses architecture• Single 5V power supply• 16-channel DMA

Benefits c

• Reduces system cost with all peripherals in one chip• Full control over your power consumption

and performance/power tradeoffs• Precisely manage low-power vs. performance• Built-in voltage regulator means fewer external components • Software library dramatically reduces development time and

increases ease-of-use • Increased overall performance due to dual buses • Native 5V supply of industrial applications; no 3.3V

conversion needed • DMA lowers CPU load, optimized access to memory



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STR730F Family of Microcontrollers | STMicroelectronics


1-866-910-3650


STR710F Series Block Diagram

The STR710F series is loaded with many communication interfaces including USB,CAN, ISO7816 and four UARTs. It is endowed with the biggest RAM of all STR7MCUs (up to 64 KB) and implements an optional external memory interface. Thismakes it a perfect fit for consumer, point of sales and high-end industrial applications.The STR710F also features high performance, very low power, and very dense code,and ST's latest 0.18µ embedded Flash technology.

48 |

Features c

• Largest choice of peripherals and interfaces, including USB and CAN

• Flexible power and clock management• Superior RAM/FLASH ratio• High-quality embedded Flash with 16 K extra Flash for

EE emulation (20 year retention at 85°C)• Extensive package options including the space efficient

8x8 LFBGA64 and 10x10 LFBGA 144• Extensive software and tool support including the complete

STR7 library for USB

Benefits c

• Reduces system cost with all peripherals on one chip• Allows full control over power consumption and

performance/power tradeoffs• Unlimited possibilities - up to 64 K RAM, and always above

16 K even with smallest Flash option• 16 K extra Flash reduces system cost with no need for

external EEPROM • Software and tools support dramatically reduces development time

and increases ease-of-use



IAR, Raisonance, & Hitex Starter KitsSTR710F Series

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STR710FZ1 144 32 -40 to +85 BGA144, LQFP144 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, CAN, SC 48 — Device 2.0 EMI

STR710FZ2 272 64 -40 to +85 BGA144, LQFP144 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, CAN, SC 48 — Device 2.0 EMI

STR711FR0 80 16 -40 to +85 BGA64, LQFP64 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, SC 30 — Device 2.0 —



STR712FR0 80 16 -40 to +85 BGA64, LQFP64 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, CAN, SC 32 — — —



STR715FR0 80 16 -40 to +85 BGA64, LQFP64 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, SC 32 — — —



REva Starter Kit - Raisonance The REva starter kit from Raisonance is a cost-effective and complete solution for evaluating and starting application development STR71X-SK/RAIS

IAR KickStart Kit™ with STR711 IAR KickStart Kits™ are cost effective and complete evaluation and development systems in a single package; they are designed to help you to a flying start by providing all the necessary hardware STR711-SK/IARand software you need to design, implement and test your STR7 application; includes J-Link: In-circuit debugger/programmer, featuring USB host interface and industry standard JTAG interface forapplication board connection; with STR711 target MCU

IAR KickStart Kit™ with STR712 IAR KickStart Kits™ are cost effective and complete evaluation and development systems in a single package; they are designed to help you to a flying start by providing all the necessary hardware STR712-SK/IARand software you need to design, implement and test your STR7 application; includes J-Link: In-circuit debugger/programmer, featuring USB host interface and industry standard JTAG interface forapplication board connection; with STR712 target MCU

Hitex Starter Kit The Hitex Starter Kit for STR7 is a complete solution for evaluating and starting application development with ST ARM core-based microcontrollers; includes: application board; Tantino, in-circuit STR710-SK/HITdebugger/programmer, featuring USB host interface and industry standard JTAG interface; HiTOP5, 16K code-size limited version of Hitex’s full-featured Integrated Development Environment;plus GNU C/C++ Compiler

Keil STR710 kit The Keil starter kit, available from Keil, is a complete solution for evaluating and starting application development with the STR7; the package includes: application board with user LEDs, push buttons, STR710 kitswitches, potentiometer and interfaces for device specific peripherals; ULink, in-circuit debugger/programmer; uVision3, the full-featured Integrated Development Environment; RealView Compilation Tools,16K code-size limited version of the optimizing C/C++ compiler


1-866-910-3650



The STR750F microcontrollers are the latest series in the STR7 family. These MCUs bring the best integration with a balanced peripheral set, USB, CAN, and key innovations like clock failuredetection and advanced motor control timers. The STR750F supports either 3.3V or 5V systems,and it is also available in an extended temperature range (-40°C to +105°C). This makes it a genuine general purpose microcontroller, suitable for a wide range of applications such as appliance, brushless motor drive, USB peripheral, UPS, alarm systems, programmable logic controller, circuit breakers, inverters, and medical and portable equipment.

50 |

Features c

• Excellent low power performance through flexible clock management and multiple low power modes with consumption down to 10 µA in standby mode

• Innovative backup clock• Fast startup and wakeup• Auto wake-up• Serial memory interface (SMI) and LIN support• Single supply, 3.3V or 5V (3.3V for USB)• Powerful timers and fast ADC• Extensive firmware support and tools; the STR750F

library is freely distributed by ST

Benefits c

• Easy adjustment of performance/power consumption ratio; suitable for battery operated applications

• Additional security due to backup clock• Fast startup and wakeup adds responsiveness• Auto wakeup improve power-savings • Less external hardware needed • 3.3V or 5V supply gives additional flexibility for customers;

no need for external regulator; real 5V drive on the I/Os when 5V is used

• Perfect fit for tri-phase motor control applications • Extensive library dramatically reduces development time

and increases ease of use



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ST750F Family of Microcontrollers | STMicroelectronics


Part Tota l Tota l Temp. °C Package Core Max. A/D A/D Timer Timer Serial Interface GPIO Ethernet USB PeripheralsNumber Flash RAM Type Variant ID Frequency Bits Channels Channels Bits Description

STR755FR0 80 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – – RTC, Motor Control

STR752FR0 80 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C, CAN 38 – – RTC, Motor Control

STR751FR1 144 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – Device 2.0 RTC, Motor Control

STR752FR1 144 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C, CAN 38 – – RTC, Motor Control

STR755FR1 144 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – – RTC, Motor Control

STR751FR2 272 16 -40 to +85 LQFP64, BGA64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – Device 2.0 RTC, Motor Control

STR752FR2 272 16 -40 to +85 LQFP64, BGA64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C, CAN 38 – – RTC, Motor Control

STR751FR0 80 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART 38 – Device 2.0 RTC, Motor Control

STR755FV2 272 16 -40 to +85 LQFP100, BGA100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C 72 – – RTC, Motor Control

STR750FV2 272 16 -40 to +85 LQFP100, BGA100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C, CAN 72 – Device 2.0 RTC, Motor Control

STR750FV1 144 16 -40 to +85 LQFP100, BGA100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C, CAN 72 – Device 2.0 RTC, Motor Control

STR755FV1 144 16 -40 to +85 LQFP100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C 72 – – RTC, Motor Control

STR750FV0 80 16 -40 to +85 TQFP100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C, CAN 72 – Device 2.0 RTC, Motor Control

STR755FV0 80 16 -40 to +85 LQFP100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C 72 – – RTC, Motor Control

STR755FR2 272 16 -40 to +85 LQFP64, BGA64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – – RTC, Motor Control



STR750 Full Evaluation Board STR750F full evaluation board with 2 x 16 LCD, LEDs, UART and CAN interfaces STR750-EVAL

Hitex Starter Kit for STR750 Hitex starter kit with STR750 evaluation board, USB-JTAG in-circuit debugger/programmer and 16 KB code-size limited version of HiTOP software toolchain STR750-SK/HIT

IAR KickStart™ Kit for STR750 IAR KickStart™ starter kit with STR750 evaluation board, USB-JTAG in-circuit debugger/programmer and 32 KB code-size limited version of EWARM software toolchain STR750-SK/IAR

Keil Starter Kit for STR750 Keil starter kit with STR750F evaluation board, USB-JTAG debugger and evaluation version of RealView Microcontroller Development Kit for ARM with uVision3 and ARM RealView Compilation Tools STR750-SK/KEIL

REva Starter Kit - Raisonance Raisonance REva starter kit for STR750F with RLink In circuit debugger/programmer (USB host interface), REva mother board, STR750F daughter, 16 KB code-size limited version of the RIDE software STR750-SK/RAIStool set and GNU C/C++ compiler for ARM

STR750 Motor Control Kit This motor control kit is ready to run within minutes for PMSM and induction 3-phase motors using STR750F for vector control drive. PMSM motor included STR750-MCKIT


1-866-910-3650

STR910FCore: ARM966E-S


The STR910F family of MCUs delivers up to 96 MIPS peak performance while executing code directly from its Flash memory, executes single-cycle DSP instructionswithin its ARM966E-S core, and includes Ethernet, USB, and CAN interfaces. Thesefeatures, combined with Flash memory sizes reaching 544 Kbytes and a vast 96 KbyteSRAM, make the STR910F an ideal single-chip solution to transform embedded controlapplications into low cost nodes on a local network, or on the Internet.

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Features c

• 96 MHz ARM966E-S CPU core with single-cycle DSP instructionsand independent internal 32-bit buses

• 10/100 Ethernet connectivity with optimized DMA data flow• Plentiful SRAM and Flash memories• Dual bank Flash• Flexible power and clock management with multiple low

power modes• Low power (< 1 µA) real-time clock with programmable

wake-up features• Extensive firmware support and tools offering. The STR910F library

is freely distributed from ST• Analog capability with 10-bit ADC and full supervisor functions

Benefits c

• Simultaneous access to both code and data, generating 96 MIPS peak performance executing code from Flash memory, and at the same time capable of up to 384 Mbytes/sec DMA data flow between peripherals and SRAM

• Connect your product to a network and retain ample CPU bandwidth to implement the embedded application

• Meet requirements of complex applications, real-time operating systems (RTOSs), communication stacks and data storage

• Ideal for robust In-Application Programming (IAP) and EEPROM emulation

• Tailor your system on the fly to balance performance and power consumption as needed

• Ideal for battery operated applications • Extensive firmware support dramatically reduces development time

and increases ease of use • With so much inside, less is needed outside saving you space, cost

and logistic headaches



IAR KickStart Kit

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STR911FM44 544 96 -40 to +85 LQFP80 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I2C 40 – Device 2.0 RTC, Motor Control

STR912FW44 544 96 -40 to +85 LQFP128 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I2C 80 MAC 10/100 Device 2.0 RTC, Motor Control, EMI

STR912FW42 288 96 -40 to +85 LQFP128 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I2C 80 MAC 10/100 Device 2.0 RTC, Motor Control, EMI

STR911FM42 288 96 -40 to +85 LQFP80 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I2C 40 – Device 2.0 RTC, Motor Control

STR910FW32 288 64 -40 to +85 LQFP128 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I2C 80 – – RTC, Motor Control

STR910FM32 288 64 -40 to +85 LQFP80 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I2C 40 – – RTC, Motor Control



STR9 Full Evaluation Board An open-design evaluation platform for STR910F, which includes reference code and a range of hardware features for evaluation of device peripherals including USB, Ethernet, CAN, ADC and much more; STR910-EVALin addition to a JTAG standard interface for in-circuit debugging and programming, it includes an ETM interface for connection of a trace tool

IAR KickStart™ Kit for STR9 IAR KickStart starter kit with STR9 evaluation board, USB-JTAG in-circuit debugger/programmer and 32 KB code-size limited version of EWARM software toolchain STR91X-SK/IAR

Keil STR9 Starter Kit Keil starter kit with STR9 evaluation board, USB-JTAG debugger and evaluation version of RealView Microcontroller Development Kit for ARM with uVision3 and ARM RealView Compilation Tools STR91X-SK/KEI

REva Starter Kit - Raisonance Raisonance REva starter kit for STR9 with RLink In circuit debugger/programmer (USB host interface), REva mother board, STR9 daughter board, 16 KB code-size limited version of the RIDE software STR91X-SK/RAItool set and GNU C/C++ compiler for ARM

Hitex Starter Kit for STR9 Hitex starter kit with STR9 evaluation board, USB-JTAG in-circuit debugger/programmer and 16 KB code-size limited version of HiTOP software toolchain STR91X-SK/HIT


1-866-910-3650

DaVinci™ TMS320DM644x Digital Signal Processing SoCsCore: ARM9 + TMS320C64x+

TMS320DM6446 DSP Block Diagram

DaVinci™ technology makes break-through innovation possible in digital media devices for the hand, home, and car. DaVinci is the first integrated portfolio of Digital SignalProcessing SoCs, software, tools, and support optimized for digital video systems. These integrated components are the industry’s first complete offering of an open platform.

Sampling today, the portfolio of DaVinci processors include the TMS320DM644x digital media processors which are highly integrated SoCs based on an ARM926 processor and the TMS320C64x+DSP core. The TMS320DM644x processors are ideal for applications such as videophones, automotive infotainment, digital still cameras, streaming media, and IP set-top boxes.

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Features c

• Integrated portfolio of Digital Signal Processing SoCs, software, development tools, and support

• Optimized for digital video systems, DaVinci technology accelerates innovation

• A complete portfolio of TI-developed digital media software is now widely available to further simplify design; the software portfolio includes multimedia codecs such as H.264, MPEG-4, WMA9 and many more; for a free evaluation, visit www.ti.com/digitalmediasoftware

• Supports several Operating Systems, appropriate for different applications, including open source Linux, MontaVista™ Linux, Green Hills INTEGRITY™, Green Hills VelOSity, QNX Neutrino and Microsoft Windows® CE

Benefits c

• Save months of development time by leveraging integrated, production-tested software and hardware components

• An open development platform enables OEM product differentiation with a flexible, complete solution

• Lower system cost significantly and leverage IP across multiple products

• Standard operating systems will allow developers with expertise on these systems to work in an environment that is familiar

• Valued members of TI’s Third Party Network provide integral components and tools that complement DaVinci™ technology; they offer various levels of video system integration, optimization and system expertise on DaVinci products worldwide



Digital Video Evaluation ModuleDigital Video Software Development Kit

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DaVinci™ Family of Microcontrollers | Texas Instruments, Inc.


Part Tota l Tota l Temp. °C Package Max. A/D A/D Timer Serial Interface GPIO Ethernet USB PeripheralsNumber Flash RAM Type Frequency Bits Channels Channels Description

TMS320DM6441ZWT 16 176 (DSP), 0 to +85 361 Pb-free BGA 513/405 DSP, N/A 16 (ARM) 1 x 64-bit WD, ASP, I2C, SPI, 71 10/100 Mbps EMAC USB 2.0 Video port front end, video port back end, VICP, VLYNQ, (ARM) 40 (ARM) 257/202 RISC 2 x 64-bit GP 3xUARTs NAND Flash, SmartMedia/xD, ATA/CF, MMC/SD. This device

is similar to the TMS320DM6446BZWT

TMS320DM6443BZWT 16 176 (DSP), 0 to +85 361 Pb-free BGA 594 DSP, N/A 16 (ARM) 1 x 64-bit WD, ASP, I2C, SPI, 71 10/100 Mbps EMAC USB 2.0 Video port back end, VICP, VLYNQ, NAND Flash, (ARM) 40 (ARM) 297 RISC 2 x 64-bit GP 3xUARTs SmartMedia/xD, ATA/CF, MMC/SD

TMS320DM6446BZWT 16 176 (DSP), 0 to +85 361 Pb-free BGA 594 DSP, N/A 16 (ARM) 1 x 64-bit WD, ASP, I2C, SPI, 71 10/100 Mbps EMAC USB 2.0 Video port front end, video port back end, VICP,VLYNQ, (ARM) 40 (ARM) 297 RISC 2 x 64-bit GP 3xUARTs NAND Flash, SmartMedia/xD, ATA/CF, MMC/SD



Digital Video Evaluation Module The Digital Video Evaluation Module (DVEVM) allows developers to write production-ready application code for the ARM and provides access to the DSP core using DaVinci APIs to begin immediate TMDXEVM6446application development for the TMS320DM6441, TMS320DM6443 and TMS320DM6446 digital media processors

Digital Video Software Development Kit The Digital Video Software Development Kit (DVSDK) is a software development kit designed to tune complex DaVinci-based digital video systems quickly and efficiently; the DVSDK significantly TMDSSDK6446-Limproves software integration and system visibility by incorporating tools such as the eXpressDSP™ Configuration Kit, TMS320DM644x SoC Visual Analyzer and MontaVistas Linux

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1-866-910-3650

C/C++ Compiler and Debugger Tools for ARM

IAR Embedded Workbench® is a set of highly sophisticated and easy-to-use development tools for programming ARM® embedded applications. It integrates the IAR C/C++ compiler, assembler, linker, librarian, text editor, project manager, and C-SPY® debugger in one Integrated DevelopmentEnvironment (IDE). With its built-in chip-specific code optimizer, IAR Embedded Workbench generates very efficient and reliable FLASH/PROMable code for ARM devices. In addition to this solid technology, IAR Systems provides professional, worldwide technical support.

The ARM Cortex-M3 processor offers significant benefits to system and software developers.

• ARM7 (ARM7TDMI, ARM7TDMI-S, and ARM720T)• ARM9 (ARM9TDMI, ARM920T, ARM922T, and ARM940T) • ARM9E (ARM926EJ-S, ARM946E-S, and ARM966E-S)• ARM11• Cortex-M3• Intel® XScale™ core

Key Components c

• IDE with project management tools and editor• Highly-optimizing ARM compiler supporting C and C++• Configuration files for ARM chips from Analog Devices,

Atmel, Freescale, Intel, Luminary Micro, NXP, STMicroelectronics, and Texas Instruments

• Extensive JTAG and RDI debugger support• Optional IAR J-Link and IAR J-Trace hardware debug

probes• Run-time libraries including source code• Relocating ARM assembler• Linker and librarian tools• C-SPY debugger with ARM simulator, JTAG support,

and support for RTOS-aware debugging on hardware • Evaluation edition of IAR PowerPac RTOS and file

system bundle• RTOS plug-ins available from IAR Systems and

RTOS vendors• Code templates for commonly used code constructs• Sample projects for evaluation boards from many

different manufacturers• User and reference guides, both printed and in

PDF format• Context-sensitive online help

IAR Embedded Workbench Version 4.41 for ARM®

Highlights in the Current Version c

• IAR PowerPac bundled evaluation edition of RTOS and file system for ARM

• Live watch on target hardware• Code coverage using IAR J-Trace• Comprehensive Flash loader support• I/O register definition files• More than 400 sample projects for different evaluation boards

Supported ARM Cores and Devices c

IAR Embedded Workbench supports ARM7, ARM9, ARM9E,ARM11, Cortex-M3, and Intel® XScale™ devices from these manufacturers:

• Analog Devices • Atmel • Freescale Semiconductor • Intel• Luminary Micro • NXP• STMicroelectronics • Texas Instruments

For more information on Arrow's Development Tools, pricing and availability, visit www.arrowdevtools.com or call 1-866-910-3650.

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Chip-Specific Support c

• Ready-made C/C++ and assembler peripheral register definition files

• Multiple code and data models (where applicable)• Extensive set of language features for PROMable

embedded code, including memory keywords, intrinsic functions, interrupt functions, memory-mapped I/O ports, etc.

• Sample projects for evaluation boards from IAR Systems, Analog Devices, ARM, Atmel, Freescale, Keil, LogicPD, Luminary Micro, Nohau, NXP, Phytec, STMicroelectronics,and Texas Instruments

• Support for 4 Gbyte applications in ARM and Thumb® mode

• Each function can be compiled in ARM or Thumb mode • Vector Floating Point (VFP) coprocessor code generation• Flash loaders included for devices from Analog Devices,

Atmel, Freescale, Luminary Micro, NXP, STMicroelectronics, and Texas Instruments

• ARM Angel debug monitor support

Embedded Focus c

• Advanced generic and processor-specific optimizations for speed and memory footprint

• Lightweight runtime library: user-configurable to match the needs of the application; full source included

• Flexible memory handling allows detailed control of code and data placement

• Unnecessary functions and variables are removed• Application-wide type checking of C/C++ variables

and functions at link time• Optional flexible checksum generation for image

runtime verification• Automatic placement of code and data in non-contiguous

memory regions• Powerful relocating macro assembler with a versatile set

of directives and operators

Embedded Debugging c

• Fully integrated debugger for source and disassembly level debugging

• Very fine granularity execution control (function call-level stepping)

• Complex code and data breakpoints• Versatile monitoring of data: locals, watch, auto,

live watch, and quick watch windows; register and memory windows

• STL container awareness• C/C++ call stack window that also shows the function

to be entered; double-click on any function in call chain updates the editor, locals, register, watch, and disassembly windows to display the state of that particular function at the time of call

• Trace utility to examine execution history: moving around in the trace window updates the editor and disassembly windows to show the appropriate location

• Terminal I/O emulation• Interrupt and I/O simulation• C-like macro system to extend debugger functionality• Application program system calls emulated by the host• Code coverage and profiling performance analysis tools• Support for the ARM Debug Communication Channel (DCC)• Generic Flash loader with API guide• Multiple Flash loaders supported• Debugger software development kit for third-party

extensions such as real-time operating systems and emulator drivers

• Command line debugger utility

Graphical IDE c

• Hierarchical project presentation• Multiple projects within the same workspace• Dockable windows and multiple views• Source browser• Library tools included for creating and

maintaining libraries• Integration with source code control systems• Text editor with multi-byte character support:

context-sensitive help system; syntax coloring; unlimited undo/redo; find; search; replace; incremental search; bookmarks; error tags; previous/next navigation; matching brackets; smart indentation; code breakpoint set/clear/enable/disable; and multiple panes

• Command line build utility

Language and Standards c

• The C programming language, as standardized by ISO/ANSI C94, with selected features from C99

• Embedded C++ extended with templates, multiple and virtual inheritance, namespaces, and other C++ features that do not cause an overhead in size or speed; full Embedded C++ library containing string, streams, etc., as well as the Standard Template Library (STL)

• IEEE-754 floating-point arithmetic• MISRA C checker• Supports a wide range of industry-standard debug and

image formats: compatible with most popular debuggers and emulators, including ELF/DWARF where applicable

User Assistance c

• Ready-made sample projects and project templates• Context-sensitive online help with library function lookup• Printed user guides with extensive step-by-step tutorials• User friendly, detailed, and precise error messages

and warnings

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1-866-910-3650

Create Applications for ARM7, ARM9, or Cortex-M3 Based Microcontrollers

The RealView® Microcontroller Development Kit (MDK) shortens development cycles byreducing the time spent configuring, testing, and debugging embedded applications.

The RealView MDK combines ARM RealView compilation tools with the Keil µVision®

Integrated Development Environment (IDE), providing developers with a feature-rich envi-ronment optimized for ARM-Powered® microcontrollers.

The Keil µVision IDE includes c

• Project management and device and tool configuration• A source code editor optimized for embedded systems • Target debugging and Flash programming• Accurate device simulation (CPU and peripheral)

ARM technology-based projects created under µVision are automatically compiled and linked using the RealView compilation tools.

The built-in microcontroller simulator models more than 50 ARM-Powered® devices, including the ARM instruction set, on-chip peripherals, and the external signals used to manipulate them.

ARM RealView compilation tools are recognized by the industryfor providing the best performance of all available ARM technology-targeted compilers. Developed and tuned to deliverthe tightest code density, the compiler produces the smallestcode size, which leads to significant product cost savings. The compiler generates optimized code for both the 32-bit ARM and 16-bit Thumb® instruction sets while supporting full ISO standard C and C++.

Project Configuration c

The µVision IDE incorporates a device database of supportedARM-Powered microcontrollers. In µVision projects, requiredoptions are set automatically when you select the device fromthe device database.

µVision displays only those options that are relevant to theselected device and prevents the selection of incompatible directives. Only a few dialogs are required to completely configure all the tools (assembler, compiler, linker, debugger, and Flash download utilities) and memory map for your application.

The Keil RealView Microcontroller Development Kit

Project Management c

File groups allow associated files to be grouped together. Theymay be used to separate files into functional blocks or to identifyengineers in your software team.

Project targets allow you to create several programs from a single project. You may require one target for testing and another target for a release version of your application. Each target allows individual tool settings within the same project file.

Editor c

The µVision Editor includes all the standard features you expect in a professional editor. Color syntax highlighting and text indentation are optimized for editing C source files, whiledocument outlining allows you to collapse function blocks in your source code. Most Editor functions are quickly accessedfrom the toolbars.

While debugging, the Editor is available so you can easily makechanges to your source code.

RealView Microcontroller Development KitRealView

Real-Time Library

µVision Project Manager

C/C++ Compiler Macro Assembler

RTX RTOS Libraries

Linker / Locator

µVision Debugger

Device Simulation Target Hardware CAN Interface

USB Device Interface

Flash File System

RTX Source Code

TCP/IP Suite

TCP, UDP, PPP, SLIP,ARP, DNS Resolver,

Ethernet, DHCP Client,HTTP Server with CGL

TFTP Server, SMTP Client

For more information on Arrow's Development Tools, pricing and availability, visit www.arrowdevtools.com or call 1-866-910-3650.

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Debugger c

The µVision Editor enables you to set simple breakpoints using the context menu (or Editor toolbar) while creating your C or assembler source. Breakpoints you set while editing areactivated when you start the µVision Debugger.

In addition to simple breakpoints, the µVision Debugger supports complex breakpoints (with conditional or logical expressions) and memory access breakpoints (with read/writeaccess from an address or range). The Debugger also displays code coverage and execution profiling information in the Editor windows.

RealView Real-Time Library c

The RealView Real-Time Library (RL-ARM) enables networking,communication, and real-time software. The RL-ARM is based ona real-time kernel that simplifies the design and implementationof complex, time-critical applications. A Flash file system, TCP/IP networking suite, and other communication protocols are included.

Today, microcontroller applications require simultaneous execution of multiple jobs or tasks. For such applications, the RL-ARM allows task management and flexible scheduling of system resources (CPU, memory, etc.).

The RL-ARM is a full-featured real-time kernel with task priorities, round-robin, preemptive context switching, and support for multiple instances of the same task function. It is royalty-free and is fully integrated into µVision.

Third-Party Utilities c

Third-party utilities extend the functions and capabilities ofµVision and are available from a wide variety of vendors.

Accurate Device Simulation c

The µVision Debugger simulates a complete ARM-Poweredmicrocontroller including the instruction set and on-chip peripherals. These powerful simulation capabilities provide serious benefits and promote rapid, reliable embedded software development.

• Simulation allows software testing on your desktop with no hardware environment

• Early software debugging on a functional basis improves overall software reliability

• Simulation allows breakpoints that are not possible with hardware debuggers

• Simulation allows for optimal input signals (hardware debuggers add extra noise)

• Signal functions are easily programmed to reproduce complex, real-world input signals

• Single-stepping through signal processing algorithms is possible; external signals stop when the CPU halts

• It is easy to test failure scenarios that would destroy real hardware peripherals

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1-866-910-3650

Tools that Span the Complete Development Process

RealView® tools by ARM® are unique in their ability to provide solutions that span the complete development process from concept to final product deployment. Eachmember of the RealView portfolio has been developed closely alongside IP, ensuringthat it maximizes the IP’s performance.

RealView Development Suite c

RealView Development Suite is the only complete, end-to-endsolution for software development that supports all ARM®

processors and ARM debug technology. These tools offer thehighest-performance ARM C/C++ compilers and support themost advanced debug technology available today for bringing up the latest SoC and ASIC designs.

Proven to deliver the highest return for the lowest risk on theirARM-based ASICs, SoC, and FPGA designs, the RealViewDeveloper Suite is a trusted source for ARM development solutions. Today, the majority of the four billion ARM-Powered™devices worldwide have software created with RealView tools.Investing in the RealView solution is the clear choice for a safe,reliable, and high-performance design.

New Features of RealView Development Suite3.0 and SP1 c

Key features of the RealView Development Suite 3.0 solutioninclude support for the full line of ARM processors, including the Cortex™-A8 processor, the Cortex-M3 processor, and future Cortex family processors; support for CoreSight™advanced debug and trace technology; an intrinsics compiler for the NEON™ SIMD technology; an enhanced compiler optimization engine that provides a 10 percent performanceimprovement; and interoperability with GNU tools, enabling optimal compilation of Embedded Linux applications and optional integration with Eclipse.

RealView Development Suite 3.0 Service Pack 1 provides a consolidation of enhancements since the original RealViewDevelopment Suite 3.0 release, including preliminary support for Cortex-R4, improved compilation times and DWARF3 debug data sizes, an expanded SIMD NEON assembler with Programmer’s notation, an improved user interface thatdebugs a multi-processor MPCore target, and expanded Cortex-M3 examples.

The following components and abilities are offered by theRealView Development Suite:

• Integrated Development Environment (IDE)• A choice of IDEs• RealView Development Suite can be integrated

with the Industry-standard Eclipse IDE through a plug-in or CodeWarrior v5.7 IDE

RealView Tools by ARM

Eclipse Plug-ins for RealView DevelopmentSuite c

RealView Development Suite integrates with the open-sourceEclipse IDE. This integration combines Eclipse’s outstandingsource code development tools and plug-in framework with thebest-in-class compilation and debug technology in the RealViewDEVELOP family of tools. The RealView Eclipse Plug-in enablesdevelopers to use Eclipse as a project manager to create, build,debug, and manage C and C++ projects for ARM targets. Theplug-in provides project stationery to simplify the creation ofARM, Thumb®, and ARM/Thumb architecture-based projects,and provides comprehensive configuration panels to specifyoptions for the RealView Development Suite.

Compilation Tools c

The compilation tools in RealView Development Suite are recognized by the industry for providing the best performance of all available ARM-processor targeted compilers. Developedand tuned to deliver the tightest code density, the compilers produce significantly smaller executables than other leading tool suites. The compilers generate optimized code for the 32-bit ARM and 16-bit Thumb and Thumb-2 instruction sets and support full ISO standard C and C++.

Debug Tools c

Designed from the ground up to support complex single- andmulti-core SoC software development with Embedded OS, thedebugger in RealView Development Suite sets the standard forcreating and debugging deeply embedded applications. Noother debug environment provides interconnectivity with both the RealView CREATE world of system-level modeling and theRealView DEVELOP world of software development.

Add-om Options c

The following are available as add-on options to the RealViewDevelopment Suite:

• RealView SoC Designer • RealView ICE and RealView Trace • Real-Time System Model (RTSM) for ARM1176JZ(F)-S • Eclipse IDE plug-in • Plug-ins for popular DSP support

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Supported Platforms: c

• Windows 2000, XP Professional • Red Hat Enterprise Linux 3 and 4 • SPARC Solaris 9 and 10

RealView ICE c

RealView ICE is ARM’s leading-edge JTAG run control hardware unit, delivering the high performance required bytoday’s developers working with sophisticated System-on-Chip(SoC) devices and large software images.

RealView ICE provides a universal-ARM solution, i.e., one unit supports all ARM CPUs in single, multi-core, homogenous,and heterogeneous architectures, offering an unparalleled depthand breadth of support for ARM processor-based devices.

RealView ICE is an essential tool in an ARM system debug environment for connection and access to devices that containthe EmbeddedICE® logic, Embedded Trace Macrocell™ (ETM™),and Embedded Trace Buffer(ETB™) components for on-chiptrace data storage. The unit has the ability to be expanded with additional modules for extended functionality, such asRealView Trace for trace data capture.

The recently released RealView ICE version 3.0 now enablescustomers to connect to the new ARM Cortex family of processors and devices containing the new CoreSight™advanced debug and trace technology. RealView ICE and Trace fully complement the RealView Development Suite in providing best-in-class integrated tools for hardware/software co-development of optimized ASIC, SoC, and FPGA-based systems.

Other New Features c

• JTAG run control for the new Cortex™-A8 and Cortex-M3 processors

• CoreSight DK11 run control support for the ARM1136, ARM1156, and ARM1176 processors

• TrustZone® secure and non-secure code views for the Cortex-A8 and ARM1176 processors

RealView ICE can be connected to most types of host platformsby Ethernet for extended and remote connection, or locally byUSB, to provide the optimum debug coupling and performancewith the RealView Debugger.

Main Features c

• High-performance debug control • Code download up to 1300 KBytes/sec with

the RealView Debugger • High-speed single-stepping; up to 100 steps/sec • JTAG Debug Communications Channel (DCC) support

• Support for variable JTAG clock frequencies, 2 kHz to 20 MHz (standard cable) or 50 MHz (LVDS cable)

• Very low JTAG clock frequencies (sub-1 kHz) support ASIC-emulation environments

• Wide target-voltage support, from 1.0V to 5.0V • Tightly coupled, synchronized multi-core control • ETM trace data capture with plug-in RealView

Trace module • ETB trace data access via the JTAG port • Debug using GDB and KGDB capability • USB 1.1 and 2.0 compatible connection

(Windows platform only) • Ethernet 10/100baseT remote and local host connection

Supported ARM Processors: c

RVI-Supported cores include the following ARM processor-based families: ARM7™, ARM9™, ARM9E™, ARM10™,ARM11™, and Cortex™

RealView Trace c

RealView Trace interfaces with ARM on-chip trace data storageEmbedded Trace Macrocell (ETM™) components for theARM7™, ARM9™, ARM9E™, ARM10™, and ARM11™ core families, and in conjunction with RealView Debugger. RealViewTrace provides non-intrusive real-time tracing of instructions, data and profiling for performance analysis. It’s an optional add-on expansion module for RealView ICE.

Main Features c

• Non-intrusive real-time tracing of instructions and data upto 250 MHz trace clock

• Up to eight million frames deep trace buffer (up to four million frame deep buffer with time stamps)

• 4-/8-/16-bit data width trace port• Trigger synchronization with external events• Fully variable trigger position• Fast on-the-fly trace data upload • Shares RealView ICE connection to the host computer • ETM trace ports modes supported

– ETM protocols v1.x, v2.x, v3.x for ETM7TM, ETM9TM, ETM10TM, and ETM11TM

– Single and doubled-edged clocking– Normal and multiplexed ports

• Time stamp (48-bit) 10 ns resolution with 32-day duration

Platforms supported are Windows 2000 and XP

Note: Cannot be used standalone. This product is designed tobe used in conjunction with a RealView ICE

Embedded Developer lets you compare more than and ...

elect and compare ARM7 core-based devices like the LPC2000from NXP, the STR7 from

STMicroelectronics and Atmel’s AT91 toeach other, or compare them to PowerPC,ColdFire, or any other device you select.

Compare any device by features and performance in seconds--then download adatasheet or go to Arrow’s shopping cartand buy the chips. Need tools to supportyour device? Every device page lists thetools that support them, and they’re linkedto Arrow’s tools shopping cart!

The only One Stop. Shop. www.EmbeddedDeveloper.com

Embedded Developer is the ultimate resource for the designer with a job to do. It is the only site in the world whereyou’re only clicks away from comparing and evaluating devices, and buying toolsand chips from the electronics industry’sbroadest line card.

You can find the complete design chain atembedded developer: Add analog solutions,or customize your design for hundreds ofapplications. Try it today--we guarantee thissite will be the one you’ll bookmark for allyour embedded designs!

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33arm Selector Guide

Documents

Transcript of 33arm Selector Guide