300 MHz to 2500 MHz Rx Mixer with Integrated Fractional-N ... · PDF file300 MHz to 2500 MHz...

300 MHz to 2500 MHz Rx Mixer with Integrated Fractional-N PLL and VCO

Data Sheet ADRF6601

Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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FEATURES Rx mixer with integrated fractional-N PLL RF input frequency range: 300 MHz to 2500 MHz Internal LO frequency range: 750 MHz to 1160 MHz Input P1dB: 14.5 dBm Input IP3: 31 dBm IIP3 optimization via external pin SSB noise figure

IP3SET pin open: 13.5 dB IP3SET pin at 3.3 V: 14.6 dB

Voltage conversion gain: 6.7 dB Matched 200 Ω IF output impedance IF 3 dB bandwidth: 500 MHz Programmable via 3-wire SPI interface 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS Cellular base stations

GENERAL DESCRIPTION The ADRF6601 is a high dynamic range active mixer with an integrated phase-locked loop (PLL) and a voltage controlled oscillator (VCO). The PLL/synthesizer uses a fractional-N PLL to generate a fLO input to the mixer. The reference input can be divided or multiplied and then applied to the PLL phase frequency detector (PFD).

The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter.

The loop filter output is then applied to an integrated VCO. The VCO output at 2 × fLO is applied to an LO divider, as well as to a programmable PLL divider. The programmable PLL divider is controlled by a sigma-delta (Σ-Δ) modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047.

The active mixer converts the single-ended 50 Ω RF input to a 200 Ω differential IF output. The IF output can operate up to 500 MHz.

The ADRF6601 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range.

Table 1.

Part No. Internal LO Range

±3 dB RFIN Balun Range

±1 dB RFIN Balun Range

ADRF6601 750 MHz 300 MHz 450 MHz 1160 MHz 2500 MHz 1600 MHz ADRF6602 1550 MHz 1000 MHz 1350 MHz 2150 MHz 3100 MHz 2750 MHz ADRF6603 2100 MHz 1100 MHz 1450 MHz 2600 MHz 3200 MHz 2850 MHz ADRF6604 2500 MHz 1200 MHz 1600 MHz 2900 MHz 3600 MHz 3200 MHz

FUNCTIONAL BLOCK DIAGRAM

MUX

RSET CP VTUNE

LODRV_EN

LON

LOP

IP3SET

VCC1

2:1MUX

VCOCORE

RFIN

TEMPSENSOR

DECLVCO

DECL2P5

DECL3P3

IFP

BUFFER

BUFFER

IFN

VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO NC

–+

CHARGE PUMP250µA,500µA (DEFAULT),750µA,1000µA

PRESCALER÷2

LECLK SPI

INTERFACE

DATA

MUXOUT

NC

3.3VLDO

2.5VLDO

VCOLDO

DIVBY

4, 2, 1

PLL_EN

REF_IN

GND

ADRF6601INTERNAL LO RANGE750MHz TO 1160MHz

34

191839354

8

6

14

13

12

16

38

37

36

7 11 15 20 21 23 24 25 28 30 31 35

32 33

2

9

40

26

29

2717101 22

PHASEFREQUENCYDETECTOR

THIRD-ORDERFRACTIONAL

INTERPOLATOR

FRACTIONREG MODULUS INTEGER

REG

N COUNTER21 TO 123

×2

÷2

÷4

0854

6-00

1

Figure 1.

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ADRF6601 Data Sheet

Rev. B | of 32

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3

RF Specifications .......................................................................... 3 Synthesizer/PLL Specifications ................................................... 4 Logic Input and Power Specifications ....................................... 4 Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9

RF Frequency Sweep .................................................................... 9 IF Frequency Sweep ................................................................... 10 Spurious Performance................................................................ 15

Register Structure ........................................................................... 16 Register 0—Integer Divide Control (Default: 0x0001C0) .... 16 Register 1—Modulus Divide Control (Default: 0x003001) ........ 16 Register 2—Fractional Divide Control (Default: 0x001802) ...... 17

Register 3—Σ-Δ Modulator Dither Control (Default: 0x10000B) .................................................................................... 17 Register 4—PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4) ................................................... 18 Register 5—PLL Enable and LO Path Control (Default: 0x0000E5) .................................................................................... 19 Register 6—VCO Control and VCO Enable (Default: 0x1E2106) .................................................................................... 19 Register 7—Mixer Bias Enable and External VCO Enable (Default: 0x000007) .................................................................... 19

Theory of Operation ...................................................................... 20 Programming the ADRF6601 ................................................... 20 Initialization Sequence .............................................................. 20 LO Selection Logic ..................................................................... 21

Applications Information .............................................................. 22 Basic Connections for Operation ............................................. 22

AC Test Fixture ............................................................................... 23 Evaluation Board ............................................................................ 24

Evaluation Board Control Software ......................................... 24 Schematic and Artwork ............................................................. 26 Evaluation Board Configuration Options ............................... 28

Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29

REVISION HISTORY 1/14—Rev. A to Rev. B

Replaced LO Range with RF Range in Data Sheet Title .............. 1 Updated Outline Dimensions ....................................................... 29

3/11—Rev. 0 to Rev. A

Changes to Features Section, General Description Section, and Table 1 ............................................................................................ 1

Changes to Table 2 ............................................................................ 3 Changes to Conditions Statement and the Figure of Merit,

Reference Spurs, and Phase Noise Parameters, Table 3; Changes to Conditions Statement and the Supply Current Parameter, Table 4 ........................................................................ 4

Changes to Table 6 ............................................................................ 6 Changes to Table 7 ............................................................................ 7 Replaced Typical Performance Characteristics Section .............. 9 Added Spurious Performance Section ......................................... 15 Changes to Figure 44 and Figure 45 ............................................. 19 Changes to Theory of Operation Section .................................... 20 Added AC Test Fixture Section and Figure 47;

Renumbered Sequentially ......................................................... 23 Changes to Evaluation Board Control Software Section........... 24 Changes to Table 10 ........................................................................ 28

1/10—Revision 0: Initial Version

Data Sheet ADRF6601

Rev. B | of 32

SPECIFICATIONS RF SPECIFICATIONS VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fPFD = 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized using CDAC = 0x0 and IP3SET = 3.3 V, unless otherwise noted.

Table 2. Parameter Test Conditions/Comments Min Typ Max Unit INTERNAL LO FREQUENCY RANGE 750 1160 MHz RF INPUT FREQUENCY RANGE ±3 dB RF input range 300 2500 MHz RF INPUT AT 610 MHz

Input Return Loss Relative to 50 Ω (can be improved with external match) −11.1 dB Input P1dB 14.8 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 67.4 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 33.4 dBm Single-Side Band Noise Figure IP3SET = 3.3 V 13.3 dB

IP3SET = open 12.5 dB LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −55.5 dBm

RF INPUT AT 910 MHz Input Return Loss Relative to 50 Ω (can be improved with external match) −16.7 dB Input P1dB 14.5 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 55.3 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 30.9 dBm Single-Side Band Noise Figure IP3SET = 3.3 V 14.6 dB

IP3SET = open 13.5 dB LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −48 dBm

RF INPUT AT 1020 MHz Input Return Loss Relative to 50 Ω (can be improved with external match) −16.8 dB Input P1dB 14.8 dBm Second-Order Intercept (IIP2) −5 dBm each tone (10 MHz spacing between tones) 60.9 dBm Third-Order Intercept (IIP3) −5 dBm each tone (10 MHz spacing between tones) 32.2 dBm Single-Side Band Noise Figure IP3SET = 3.3 V 14.8 dB

IP3SET = open 13.5 dB LO-to-IF Leakage At 1× LO frequency, 50 Ω termination at the RF port −49 dBm

IF OUTPUT Voltage Conversion Gain Differential 200 Ω load 6.7 dB IF Bandwidth Small signal 3 dB bandwidth 500 MHz Output Common-Mode Voltage External pull-up balun or inductors required 5 V Gain Flatness Over frequency range, any 5 MHz/50 MHz 0.2/0.5 dB Gain Variation Over full temperature range 1.2 dB Output Swing Differential 200 Ω load 2 V p-p Differential Output Return Loss Measured through 4:1 balun −15.5 dB

LO INPUT/OUTPUT (LOP, LON) Externally applied 1× LO input, internal PLL disabled Frequency Range 250 6000 MHz Output Level (LO as Output) 1× LO into a 50 Ω load, LO output buffer enabled −6 dBm Input Level (LO as Input) −6 0 +6 dBm Input Impedance 50 Ω

ADRF6601 Data Sheet

Rev. B | of 32

SYNTHESIZER/PLL SPECIFICATIONS VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized using CDAC = 0x0 and IP3SET = 3.3 V, unless otherwise noted.

Table 3. Parameter Test Conditions/Comments Min Typ Max Unit SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1× LO

Frequency Range Internally generated LO 750 1160 MHz Figure of Merit1 PREF_IN = 0 dBm −222 dBc/Hz/Hz Reference Spurs fPFD = 38.4 MHz

fPFD/4 −107 dBc fPFD −83 dBc >fPFD −88 dBc PHASE NOISE fLO = 750 MHz to 1160 MHz, fPFD = 38.4 MHz

1 kHz to 10 kHz offset −99 dBc/Hz 100 kHz offset −108 dBc/Hz 500 kHz offset −127 dBc/Hz 1 MHz offset −135 dBc/Hz 5 MHz offset −147 dBc/Hz 10 MHz offset −151 dBc/Hz 20 MHz offset −153 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.14 °rms PFD Frequency 20 40 MHz

REFERENCE CHARACTERISTICS REF_IN, MUXOUT pins REF_IN Input Frequency 12 160 MHz REF_IN Input Capacitance 4 pF MUXOUT Output Level VOL (lock detect output selected) 0.25 V VOH (lock detect output selected) 2.7 V MUXOUT Duty Cycle 50 %

CHARGE PUMP Pump Current Programmable to 250 µA, 500 µA, 750 µA, 1 mA 500 µA Output Compliance Range 1 2.8 V

1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10 log 10(fPFD) – 20 log 10(fLO/fPFD). The FOM was measured across the full LO range with fREF = 80 MHz,

and fREF power = 10 dBm (500 V/µs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.

LOGIC INPUT AND POWER SPECIFICATIONS VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fPFD = 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized using CDAC = 0x0 and IP3SET = 3.3 V, unless otherwise noted.

Table 4. Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS CLK, DATA, LE

Input High Voltage, VINH 1.4 3.3 V Input Low Voltage, VINL 0 0.7 V Input Current, IINH/IINL 0.1 µA Input Capacitance, CIN 5 pF

POWER SUPPLIES VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins Voltage Range 4.75 5 5.25 V Supply Current PLL only 97 mA

External LO mode (internal PLL disabled, IP3SET pin = 3.3 V, LO output buffer off ) 184 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on) 294 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off) 281 mA Power-down mode 30 mA

Data Sheet ADRF6601

Rev. B | of 32

TIMING CHARACTERISTICS VS = 5 V ± 5%.

Table 5. Parameter Limit Unit Description t1 20 ns min LE setup time t2 10 ns min DATA-to-CLK setup time t3 10 ns min DATA-to-CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK-to-LE setup time t7 20 ns min LE pulse width

Timing Diagram

CLK

DATA

LE

DB23 (MSB) DB22 DB2 DB1(CONTROL BIT C2)(CONTROL BIT C3)

DB0 (LSB)(CONTROL BIT C1)

t1

t2 t3

t7t6

t4 t5

0854

6-00

2

Figure 2. Timing Diagram

ADRF6601 Data Sheet

Rev. B | of 32

ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Supply Voltage, VCC1, VCC2, VCC_LO,

VCC_MIX, VCC_V2I −0.5 V to +5.5 V

Digital I/O, CLK, DATA, LE, LODRV_EN, PLL_EN

−0.3 V to +3.6 V

VTUNE 0 V to 3.3 V IFP, IFN −0.3 V to VCC_V2I + 0.3 V RFIN 16 dBm LOP, LON, REF_IN 13 dBm θJA (Exposed Paddle Soldered Down) 35°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Data Sheet ADRF6601

Rev. B | of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1INDICATOR

NOTES1. NC = NO CONNECT. DO NOT CONNECT THIS PIN.2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE.

1VCC12DECL3P33CP4GND5RSET6REF_IN7GND8MUXOUT9DECL2P5

10VCC2

23 GND24 GND25 GND26 RFIN27 VCC_V2I28 GND29 IP3SET30 GND

22 VCC_MIX21 GND

11G

ND

12D

ATA

13C

LK

15G

ND

17VC

C_L

O16

PLL_

EN

18IF

P19

IFN

20G

ND

14LE

33N

C34

VCC

_LO

35G

ND

36LO

DRV_

EN37

LON

38LO

P39

VTU

NE

40D

ECLV

CO

32N

C31

GN

D

TOP VIEW(Not to Scale)

ADRF6601

0854

6-00

3

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 VCC1 Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin. 2 DECL3P3 Decoupling Node for the 3.3 V LDO. Connect a 0.1 µF capacitor between this pin and ground. 3 CP Charge Pump Output Pin. Connect to VTUNE through the loop filter. 4, 7, 11, 15, 20, 21, 23, 24, 25, 28, 30, 31, 35

GND Ground. Connect these pins to a low impedance ground plane.

5 RSET Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In this mode, no external RSET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally adjusted according to the following equation:

Ω37.84.217

−

×=

NOMINAL

CPSET I

IR

6 REF_IN Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dc-biased and should be ac-coupled.

8 MUXOUT Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register.

9 DECL2P5 Decoupling Node for the 2.5 V LDO. Connect a 0.1 µF capacitor between this pin and ground. 10 VCC2 Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin. 12 DATA Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. 13 CLK Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. 14 LE Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the

eight registers. The relevant latch is selected by the three control bits of the 24-bit word. 16 PLL_EN PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is

automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be used to switch modes.

17, 34 VCC_LO Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.

18, 19 IFP, IFN Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes.

ADRF6601 Data Sheet

Rev. B | of 32

Pin No. Mnemonic Description 22 VCC_MIX Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled

with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin. 26 RFIN RF Input (single-ended, 50 Ω). 27 VCC_V2I Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled

with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin. 29 IP3SET Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open. 32, 33 NC No Connection. 36 LODRV_EN LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON

pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high if the PLEN bit (DB6 in Register 5) is set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. The external LO drive frequency must be 1× LO. This pin has an internal 100 kΩ pull-down resistor.

37, 38 LON, LOP Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO generation is disabled, an external 1× LO can be applied to these pins.

39 VTUNE VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.5 V to 2.5 V.

40 DECLVCO Decoupling Node for the VCO LDO. Connect a 100 pF capacitor and a 10 µF capacitor between this pin and ground.

EPAD Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.

Data Sheet ADRF6601

Rev. B | of 32

TYPICAL PERFORMANCE CHARACTERISTICS RF FREQUENCY SWEEP CDAC = 0x0, internally generated high-side LO, RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted.

5

–5

–4

–3

–2

–1

0

1

2

3

4

610 660 710 760 810 860 910 960 1010

GA

IN (d

B)

RF FREQUENCY (MHz)

IP3SET = OPENIP3SET = 3.3V

TA = –40°CTA = +25°CTA = +85°C

0854

6-00

4

Figure 4. Gain vs. RF Frequency

90

80

70

60

50

40

30610 660 710 760 810 860 910 960 1010

INPU

T IP

2 (d

Bm

)

RF FREQUENCY (MHz) 0854

6-00

5


TA = –40°CTA = +25°CTA = +85°C

Figure 5. Input IP2 vs. RF Frequency

20

18

16

14

12

10

8

6

4

2

0610 660 710 760 810 860 910 960 1010

NO

ISE

FIG

UR

E (d

B)

RF FREQUENCY (MHz)


TA = –40°CTA = +25°CTA = +85°C

0854

6-00

6

Figure 6. Noise Figure vs. RF Frequency

40

45

35

30

20

25

10

15

5610 660 710 760 810 860 910 960 1010

INPU

T IP

3 (d

Bm

)

RF FREQUENCY (MHz)


TA = –40°CTA = +25°CTA = +85°C

0854

6-00

7

Figure 7. Input IP3 vs. RF Frequency

20

18

16

14

12

10

8

6

4

2

0610 660 710 760 810 860 910 960 1010

INPU

T P1

dB (d

Bm

)

RF FREQUENCY (MHz)


TA = –40°CTA = +25°CTA = +85°C

0854

6-00

8

Figure 8. Input P1dB vs. RF Frequency

ADRF6601 Data Sheet

Rev. B | of 32

IF FREQUENCY SWEEP CDAC = 0x0, internally generated swept low-side LO, fRF = 1960 MHz, RFIN = −5 dBm, unless otherwise noted.

5

–5

–4

–3

–2

–1

0

1

2

3

4

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

GA

IN (

dB

)


TA = –40°CTA = +25°CTA = +85°C

IF FREQUENCY (MHz) 0854

6-00

9

Figure 9. Gain vs. IF Frequency

90

80

70

60

50

40

3025 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

INP

UT

IP

2 (d

Bm

)


TA = –40°CTA = +25°CTA = +85°C

IF FREQUENCY (MHz) 0854

6-01

0

Figure 10. Input IP2 vs. IF Frequency, RFIN = −5 dBm

20

18

16

14

12

10

8

6

4

2

025 4003753503253002752502252001751501257550 100

NO

ISE

FIG

UR

E (

dB

)

IF FREQUENCY (MHz)

TA = –40°CTA = +25°CTA = +85°C


0854

6-01

1

Figure 11. Noise Figure vs. IF Frequency

45

40

35

30

25

20

15

10

525 4003753503253002752502252001751501257550 100

INP

UT

IP

3 (d

Bm

)

IF FREQUENCY (MHz)

TA = –40°CTA = +25°CTA = +85°C

0854

6-01

2


Figure 12. Input IP3 vs. IF Frequency, RFIN = −5 dBm

25 4003753503253002752502252001751501257550 100

20

18

16

14

12

10

8

6

4

2

0

INP

UT

P1d

B (

dB

m)

IF FREQUENCY (MHz)


TA = –40°CTA = +25°CTA = +85°C

0854

6-01

3

Figure 13. Input P1dB vs. IF Frequency

Data Sheet ADRF6601

Rev. B | of 32

0

–60

–65

–70

–55

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

750 800 850 900 950 1000 1050 1100 1150

LO

-TO

-IF

FE

ED

TH

RO

UG

H (

dB

m)

LO FREQUENCY (MHz)


TA = –40°CTA = +25°CTA = +85°C

0854

6-01

4

Figure 14. LO-to-IF Feedthrough vs. LO Frequency, LO Output Turned Off, CDAC = 0x0

–90

–80

–70

–60

–50

–40

–30

750 1000 1050 1100 1150950900850800

LO

-RF

LE

AK

AG

E (

dB

m)

LO FREQUENCY (MHz)


TA = –40°CTA = +25°CTA = +85°C

0854

6-01

5

Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off

0

–35

–40

–30

–25

–20

–15

–10

–5

500 1300120011001000900800700600

RE

TU

RN

LO

SS

(d

B)

RF FREQUENCY (MHz) 0854

6-01

6

Figure 16. RF Input Return Loss vs. RF Frequency

0

–40

–35

–30

–25

–20

–15

–10

–5

500 1300120011001000900800700600

RE

TU

RN

LO

SS

(d

B)

LO FREQUENCY (MHz) 0854

6-01

7

Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun)

350

0

50

100

150

200

250

300

3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

50 500450400350300250200150100

RE

SIS

TA

NC

E (Ω

)

CA

PA

CIT

AN

CE

(p

F)

IF FREQUENCY (MHz)

CAPACITANCE

RESISTANCE

0854

6-01

8

Figure 18. IF Differential Output Impedance (R Parallel C Equivalent)

35

10

15

20

25

30

–60 –50 –40 –30 –20 –10 0

NO

ISE

FIG

UR

E (

dB

)

CW BLOCKER LEVEL (dBm)


0854

6-01

9

Figure 19. SSB Noise Figure vs. 5 MHz Offset Blocker Level, LO Frequency = 1055 MHz, RF Frequency = 915 MHz

ADRF6601 Data Sheet

Rev. B | of 32

0

–60

–65

–70

–55

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

550 1350125011501050950850750650

RF

-TO

-IF

IS

OL

AT

ION

(d

Bc)

RF FREQUENCY (MHz)


TA = –40°CTA = +25°CTA = +85°C

0854

6-02

0Figure 20. RF-to-IF Isolation vs. RF Frequency, High-Side LO, IF = 140 MHz,

LO Output Turned Off

0

–10

–1

–2

–3

–4

–5

–6

–7

–9

–8

750 800 850 900 950 1000 1050 1100 1150

LO

OU

TP

UT

AM

PL

ITU

DE

(d

Bm

)

LO FREQUENCY (MHz)


TA = –40°CTA = +25°CTA = +85°C

0854

6-02

1

Figure 21. LO Output Amplitude vs. LO Frequency

20

15

10

5

0

–5

–10

–15

–200 50 100 150 200 250

FR

EQ

UE

NC

Y D

EV

IAT

ION

FR

OM

920

MH

z (M

Hz)

TIME (µs) 0854

6-02

2

Figure 22. Frequency Deviation from 910 MHz vs. Time (Demonstrates LO Frequency Settling Time from 920 MHz to 910 MHz)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0750 800 850 900 950 1000 1050 1100 1150

VT

UN

E V

OL

TA

GE

(V

)

LO FREQUENCY (MHz)

TA = –40°CTA = +25°CTA = +85°C

0854

6-02

3

Figure 23. VTUNE vs. LO Frequency

350

100

150

200

250

300

750 1150110010501000950900850800

SU

PP

LY

CU

RR

EN

T (

mA

)

LO FREQUENCY (MHz)


TA = –40°CTA = +25°CTA = +85°C

0854

6-02

4

Figure 24. Supply Current vs. LO Frequency

2.0

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

–55 –35 –15 5 25 45 65 85 105

VP

TA

T V

OL

TA

GE

(V

)

TEMPERATURE (°C)


0854

6-02

5

Figure 25. VPTAT Voltage vs. Temperature (IP3SET = Optimized, Open)

Data Sheet ADRF6601

Rev. B | of 32

Complementary cumulative distribution function (CCDF), fRF = 2140 MHz, fIF = 140 MHz.

100

0

10

20

30

40

50

60

70

80

90

–1.0–1.5–2.0 –0.5 0 0.5 1.0 1.5 2.0 3.02.5

DIS

TR

IBU

TIO

N P

ER

CE

NT

AG

E (

%)

GAIN (dB) 0854

6-02

6


TA = –40°CTA = +25°CTA = +85°C

Figure 26. Gain

100

0

10

20

30

40

50

60

70

80

90

50 55 60 65 70 75 80

DIS

TR

IBU

TIO

N P

ER

CE

NT

AG

E (

%)

INPUT IP2 (dBm)


TA = –40°CTA = +25°CTA = +85°C

0854

6-02

7

Figure 27. Input IP2

100

0

10

20

30

40

50

60

70

80

90

11 12 13 14 15 16 17109

DIS

TR

IBU

TIO

N P

ER

CE

NT

AG

E (

%)

NOISE FIGURE (dB)

IP3SET = OPEN

TA = –40°CTA = +25°CTA = +85°C

0854

6-02

8

Figure 28. Noise Figure

100

0

10

20

30

40

50

60

70

80

90

24 26 28 30 32 34 36 38 40

DIS

TR

IBU

TIO

N P

ER

CE

NT

AG

E (

%)

INPUT IP3 (dBm)


TA = –40°CTA = +25°CTA = +85°C

0854

6-02

9

Figure 29. Input IP3

100

0

10

20

30

40

50

60

70

80

90

10 11 12 13 14 15 16 1817

DIS

TR

IBU

TIO

N P

ER

CE

NT

AG

E (

%)

INPUT P1dB (dBm)


TA = –40°CTA = +25°CTA = +85°C

0854

6-03

0

Figure 30. Input P1dB

100

0

10

20

30

40

50

60

70

80

90

–90 –80 –70 –60 –50 –40 –30

DIS

TR

IBU

TIO

N P

ER

CE

NT

AG

E (

%)

LO FEEDTHROUGH (dBm)


TA = –40°CTA = +25°CTA = +85°C

0854

6-03

1

Figure 31. LO Feedthrough to IF, LO Output Turned Off

ADRF6601 Data Sheet

Rev. B | of 32

Measured at IF output, CDAC = 0x0, IP3SET = open, internally generated high-side LO, fREF = 153.6 MHz, fPFD = 38.4 MHz, RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted.

–80

–160

–150

–140

–130

–120

–110

–100

–90

1k 10k 100k 1M 10M 100M

PH

AS

E N

OIS

E (

dB

c/H

z)

OFFSET FREQUENCY (Hz)

LO FREQUENCY = 1155.2MHz

LO FREQUENCY = 752MHz

TA = –40°CTA = +25°CTA = +85°C

0854

6-03

2

Figure 32. Phase Noise vs. Offset Frequency

–75

–110

–105

–100

–95

–90

–85

–80

750 850 950 1050 1150800 900 1000 1100

SP

UR

S L

EV

EL

(d

Bc)

LO FREQUENCY (MHz)

OFFSET AT 2× PFD FREQUENCYOFFSET AT 4× PFD FREQUENCY

TA = –40°CTA = +25°CTA = +85°C

0854

6-03

3

Figure 33. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD)

–75

–110

–105

–100

–95

–90

–85

–80

750 850 950 1050 1150800 900 1000 1100

SP

UR

S L

EV

EL

(d

Bc)

LO FREQUENCY (MHz)

TA = –40°CTA = +25°CTA = +85°C

0.25× PFDFREQUENCY

0854

6-03

4

OFFSET AT 3× PFD FREQUENCYOFFSET AT 1× PFD FREQUENCY

Figure 34. PLL Reference Spurs vs. LO Frequency (0.25× PFD, 1× PFD, and 3× PFD)

0.50

0

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.05

0.10

750 800 850 900 950 1000 1050 1100 1150

INT

EG

RA

TE

D P

HA

SE

NO

ISE

(°r

ms)

LO FREQUENCY (MHz)

TA = –40°CTA = +25°CTA = +85°C

0854

6-03

5

Figure 35. Integrated Phase Noise vs. LO Frequency

–90

–100

–110

–120

–130

–140

–150

–160

PH

AS

E N

OIS

E (

dB

c/H

z)

LO FREQUENCY (MHz)

TA = –40°CTA = +25°CTA = +85°C

750 1150110010501000950900850800

0854

6-03

6

OFFSET = 5MHz

OFFSET = 100kHz

OFFSET = 1kHz

Figure 36. Phase Noise vs. LO Frequency (1 kHz, 100 kHz, and 5 MHz Steps)

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

PH

AS

E N

OIS

E (

dB

c/H

z)

LO FREQUENCY (MHz)

OFFSET = 1MHz

TA = –40°CTA = +25°CTA = +85°C

750 800 850 900 950 1000 1050 1100 1150

OFFSET = 10kHz

0854

6-03

7

Figure 37. Phase Noise vs. LO Frequency (10 kHz, 1 MHz Steps)

Data Sheet ADRF6601

Rev. B | of 32

SPURIOUS PERFORMANCE (N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spurious products were measured in dB relative to the carrier (dBc) from the IF output power level. All spurious components greater than −125 dBc are shown.

LO = 750 MHz, RF = 610 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm.

M

N

0 1 2 3 4 0 −115.74 −63.28 −31.83 −54.52 −33.54

1 −49.49 0.0 −64.58 −24.09 −71.52

2 −48.77 −42.49 −75.23 −60.35 −67.88

3 −81.30 −71.27 −103.32 −73.13 −110.05

4 −83.02 −91.24 −105.20 −88.27 −113.66

5 −103.16 −111.19 −114.25 −108.4 −115.31

6 −110.88 −112.83 −112.85 −113.85 −113.55

7 −110.87 −108.26 −112.91 −111.93 −113.64

LO = 1050 MHz, RF = 910 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm.

M

N

0 1 2 3 4 0 −113.23 −57.96 −27.78 −58.01 −40.34

1 −34.12 0.0 −58.72 −27.14 −84.94

2 −49.76 −47.19 −57.30 −68.48 −65.03

3 −73.54 −74.12 −102.24 −72.99 −108.62 4 −102.66 −110.29 −100.07 −99.75 −112.69 5 −108.79 −107.57 −110.94 −110.16 −115.35

6 −110.79 −108.34 −107.38 −112.44 −113.78

7 −109.87 −109.71 −108.58 −110.01

ADRF6601 Data Sheet

Rev. B | of 32

REGISTER STRUCTURE This section provides the register maps for the ADRF6601. The three LSBs determine the register that is programmed.

REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)

DIVIDEMODE

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 0 0 0 0 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0)

DM

0

1

ID6 ID5 ID4 ID3 ID2 ID1 ID0

0 0 1 0 1 0 1

0 0 1 0 1 1 0

0 0 1 0 1 1 1

0 0 1 1 0 0 0

... ... ... ... ... ... ...

... ... ... ... ... ... ...

0 1 1 1 0 0 0

... ... ... ... ... ... ...

... ... ... ... ... ... ...

1 1 1 0 1 1 1

1 1 1 1 0 0 0

1 1 1 1 0 0 1

1 1 1 1 0 1 0

1 1 1 1 0 1 1

...

...

119

120 (INTEGER MODE ONLY)

INTEGER DIVIDE RATIO




24

...

...

56 (DEFAULT)

INTEGER

INTEGER DIVIDE RATIO CONTROL BITS

DIVIDE MODE

FRACTIONAL (DEFAULT)




RESERVED

0854

6-03

8

Figure 38. Register 0—Integer Divide Control Register Map

REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001) MODULUS VALUE

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB00 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)

MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD00 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 1 0... ... ... ... ... ... ... ... ... ... ...... ... ... ... ... ... ... ... ... ... ...1 1 0 0 0 0 0 0 0 0 0... ... ... ... ... ... ... ... ... ... ...... ... ... ... ... ... ... ... ... ... ...1 1 1 1 1 1 1 1 1 1 1

MODULUS VALUE

...

...2047

CONTROL BITS

1

1536 (DEFAULT)

2......

RESERVED

0854

6-03

9

Figure 39. Register 1—Modulus Divide Control Register Map


Data Sheet ADRF6601

Rev. B | of 32

REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)

FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 1

... ... ... ... ... ... ... ... ... ... ...

... ... ... ... ... ... ... ... ... ... ...

0 1 1 0 0 0 0 0 0 0 0

... ... ... ... ... ... ... ... ... ... ...

... ... ... ... ... ... ... ... ... ... ...

FRACTIONAL VALUE MUST BE LESS THAN MODULUS

FRACTIONAL VALUE

0

1

...

...

768 (DEFAULT)

...

...

<MDR

FRACTIONAL VALUERESERVEDDB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CONTROL BITS

0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0)

0854

6-04

0

Figure 40. Register 2—Fractional Divide Control Register Map

REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B) DITHER

ENABLEDB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 DITH1 DITH0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)

DITH1 DITH00 00 11 01 1

DEN01

DITHERMAGNITUDE DITHER RESTART VALUE CONTROL BITS

DITHER MAGNITUDE15 (DEFAULT)731 (RECOMMENDED)

DITHER ENABLEDISABLEENABLE (DEFAULT, RECOMMENDED)

DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0x00001 (DEFAULT)......0x1FFFF

DITHER RESTARTVALUE

0854

6-04

1

Figure 41. Register 3—Σ-Δ Modulator Dither Control Register Map

ADRF6601 Data Sheet

Rev. B | of 32

REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4) CP

CURRENTREF

SOURCE

PFDPOL

CPSRC

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)

CPC1 CPC0

0 00 11 01 1

CPS

01

CPP1 CPP0

0 00 11 01 1

CPB4 CPB3 CPB2 CPB1 CPB0

0 0 0 0 00 0 0 0 10 0 1 1 00 1 0 1 01 0 0 0 01 1 1 1 1

CPBD01

CPM

01

RS0 RS1

0 00 11 01 1

RMS2 RMS1 RMS0

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

10 × 22.5°/ICPMULT (DEFAULT)16 × 22.5°/ICPMULT31 × 22.5°/ICPMULT

PFD PHASE OFFSET MULTIPLIER

0 × 22.5°/ICPMULT1 × 22.5°/ICPMULT6 × 22.5°/ICPMULT (RECOMMENDED)

BOTH ONPUMP DOWNPUMP UPTRISTATE (DEFAULT)

REF OUPUTMUX SELECT

INPUT REFPATH

PFD PHASE OFFSETMULTIPLIER

CPCURRENT

CPCONTROL PFD EDGE CONTROL BITS

PFD ANTIBACKLASH

DELAY

PE0

01

REFERENCE PATH EDGESENSITIVITYFALLING EDGERISING EDGE (DEFAULT)

PAB0 PAB1

0 00 11 01 1

PFD ANTI BACKLASHDELAY0ns (DEFAULT)0.5ns0.75ns0.9ns

CHARGE PUMP CONTROL

0.5× REF_IN (BUFFERED)

CHARGE PUMP CONTROL SOURCE

CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)CONTROL FROM PFD (DEFAULT)

REF OUTPUT MUX SELECT

LOCK DETECT (DEFAULT)VPTATREF_IN (BUFFERED)

PFD PHASE OFFSET POLARITYNEGATIVEPOSITIVE (DEFAULT)

CHARGE PUMP CURRENTREFERENCE SOURCEINTERNAL (DEFAULT)EXTERNAL

0.25× REF_IN

CHARGE PUMP CURRENT

250µA500µA (DEFAULT)750µA1000µA

INPUT REFERENCEPATH SOURCE2× REF_INREF_IN (DEFAULT)0.5× REF_IN

2× REF_IN (BUFFERED)TRISTATERESERVEDRESERVED

PE1

01

DIVIDER PATH EDGESENSITIVITYFALLING EDGERISING EDGE (DEFAULT)

0854

6-04

2

Figure 42. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map

Data Sheet ADRF6601

Rev. B | of 32

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

0854

6-04

3

RESERVED RES PLLEN

LODIV1

LOEXT

LODRV

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7LDV2

DB6 DB5 DB4 DB3 DB2 DB1 DB0CD3 CD2 CD1 CD0 PLEN LDV1 LXL LDRV C3(1) C2(0) C1(1)

LDRV

01

LXL

01

LDV1

01

DIVIDE BY 1DIVIDE BY 2 (DEFAULT)

LO OUTPUT DRIVERENABLE

DRIVER OFF (DEFAULT)DRIVER ON

PLEN

01

DISABLEENABLE (DEFAULT)

PLL ENABLE

EXTERNAL LO DRIVEENABLE (PIN 37, PIN 38)

INTERNAL LO OUTPUT (DEFAULT)EXTERNAL LO INPUT

DIVIDE-BY-2 IN LO CHAIN ENABLE

CAP DAC CONTROL BITS

CD3 CD2 CD1 CD0

0 0 0 0... ... ... ...

MIN...

CAPACITOR DACCONTROL FOR IIP3OPTIMIZATION

1 1 1 1 MAX

0 0 0 0 00 0 00 0 0 0

Figure 43. Register 5—PLL Enable and LO Path Control Register Map

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106) CHARGE

PUMPENABLE

3.3VLDO

ENABLEVCO

ENABLEVCO

SWITCHVCO

BW SWCTRL

VBSRC

01

VCO EN

VCO LDOENABLE VCO AMPLITUDERESERVED VCO BAND SELECT FROM SPI

VBS[5:0] VCO BAND SELECT FROM SPI0x00

DEFAULT

CHARGE PUMP ENABLE

0x01….

0x00 0…. ….0x18 24 (DEFAULT)…. ….0x2B 43…. ….0x3F 63 (RECOMMENDED)

0x20….0x3F

VCO BW CAL AND SW SOURCE CONTROL

BAND CAL (DEFAULT)VCO SW

01

VCO SWITCH CONTROL FROM SPI

REGULAR (DEFAULT)BAND CAL

SPI

VCO ENABLE


DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CONTROL BITS

DB23CPEN L3EN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)LVEN

VC[5:0] VCO AMPLITUDE

01

LVEN VCO LDO ENABLE


01

L3EN 3.3V LDO ENABLE


01

CPEN


01

0 0 0

0854

6-04

4

Figure 44. Register 6—VCO Control and VCO Enable Register Map

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB00 XVCO

XVCORES

MBE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(1) C1(1)

MIXERB_EN RESERVED CONTROL BITS

MBE01

XVCO01

INTERNAL VCO (DEFAULT)EXTERNAL VCO

MIXER BIAS ENABLEENABLE (DEFAULT)DISABLE

EXTERNAL VCO

0854

6-04

5

Figure 45. Register 7—Mixer Bias Enable and External VCO Enable Register Map

ADRF6601 Data Sheet

Rev. B | of 32

THEORY OF OPERATION The ADRF6601 integrates a high performance downconverting mixer with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions and the mixer optimization functions, as well as allowing for an externally applied LO or VCO.

The mixer core within the ADRF6601 is the next generation of an industry-leading family of mixers from Analog Devices, Inc. The RF input is converted to a current and then mixed down to IF using high performance NPN transistors. The mixer output currents are transformed to a differential output voltage by external bias inductors. The mixer bias current is also sourced through these external inductors. The high performance active mixer core results in an exceptional IIP3 and IP1dB with a very low output noise floor for excellent dynamic range. Over the specified frequency range, the ADRF6601 typically provides an IF input P1dB of 14.5 dBm and an IIP3 of 31 dBm.

Improved performance at specific frequencies can be achieved with the use of the internal capacitor DAC (CDAC), which is programmable via the SPI port and by using a resistor to a 5 V supply from the IP3SET pin (Pin 29). Adjustment of the capacitor DAC allows increments in phase shift at internal nodes in the ADRF6601, thus allowing cancellation of third-order distortion with no change in supply current. Connecting a resistor to a 5 V supply from the IP3SET pin increases the internal mixer core current, thereby improving overall IIP2 and IIP3, as well as IP1dB. Using the IP3SET pin for this purpose increases the overall supply current.

The fractional divide function of the PLL allows the frequency multiplication value from REF_IN to LO output to be a fractional value rather than to be restricted to an integer value as in traditional PLLs. In operation, this multiplication value is

INT + (FRAC/MOD)

where: INT is the integer value. FRAC is the fractional value. MOD is the modulus value.

The INT, FRAC, and MOD values are all programmable via the SPI port. In other fractional-N PLL designs, fractional multiplication is achieved by periodically changing the fractional value in a deterministic way. The disadvantage of this approach is often spurious components close to the fundamental signal. In the ADRF6601, a Σ-Δ modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function.

PROGRAMMING THE ADRF6601 The ADRF6601 is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Figure 2. Eight pro-grammable registers, each with 24 bits, control the operation of the device. The register functions are listed in Table 8.

Table 8. ADRF6601 Register Functions Register Function Register 0 Integer divide control for the PLL Register 1 Modulus divide control for the PLL Register 2 Fractional divide control for the PLL Register 3 Σ-Δ modulator dither control Register 4 PLL charge pump, PFD, reference path control Register 5 PLL enable and LO path control Register 6 VCO control and VCO enable Register 7 Mixer bias enable and external VCO enable

Note that internal calibration for the PLL must be run when the ADRF6601 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 should always be programmed in the order specified in the Initialization Sequence section.

To program the frequency of the ADRF6601, the user typically programs only Register 0, Register 1, and Register 2. However, if registers other than these are programmed first, a short delay should be inserted before programming Register 0. This delay ensures that the VCO band calibration has sufficient time to complete before the final band calibration for Register 0 is initiated.

Software is available on the ADRF6601 product page under the Evaluation Boards & Kits section that allows easy programming from a PC running Windows XP or Vista.

INITIALIZATION SEQUENCE To ensure proper power-up of the ADRF6601, it is important to reset the PLL circuitry after the VCC supply rail settles to 5 V ± 0.25 V. Resetting the PLL ensures that the internal bias cells are properly configured, even under poor supply start-up conditions.

To ensure that the PLL is reset after power-up, follow this procedure:

1. Disable the PLL by setting the PLEN bit to 0 (Register 5, Bit DB6).

2. After a delay of >100 ms, set the PLEN bit to 1 (Register 5, Bit DB6).

After this procedure is complete, the other registers should be programmed in the following order: Register 7, Register 6, Register 4, Register 3, Register 2, Register 1. Then, after a delay of >100 ms, Register 0 should be programmed.













Data Sheet ADRF6601

Rev. B | of 32

LO SELECTION LOGIC The downconverting mixer in the ADRF6601 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer.

The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3 (LDRV) and Bit DB6 (PLEN) in Register 5. The combination of externally applied logic and internal bits required for particular LO functions is given in Table 9.

Table 9. LO Selection Logic Pins1 Register 5 Bits1 Outputs

Pin 16 (PLL_EN) Pin 36 (LODRV_EN) Bit DB6 (PLEN) Bit DB3 (LDRV) Output Buffer LO 0 X 0 X Disabled External 0 X 1 X Disabled External 1 X 0 X Disabled External 1 0 1 0 Disabled Internal 1 X 1 1 Enabled Internal 1 1 1 X Enabled Internal 1 X = don’t care.


ADRF6601 Data Sheet

Rev. B | of 32

APPLICATIONS INFORMATION BASIC CONNECTIONS FOR OPERATION Figure 46 shows the schematic for the ADRF6601 evaluation board. The six power supply pins should be individually decoupled using 100 pF and 0.1 µF capacitors located as close as possible to the device. In addition, the internal decoupling nodes (DECL3P3, DECL2P5, and DECLVCO) should be decoupled with the capacitor values shown in Figure 46.

The RF input is internally ac-coupled and needs no external bias. The IF outputs are open collector, and a bias inductor is required from these outputs to VCC.

A peak-to-peak differential swing on RFIN of 1 V (0.353 V rms for a sine wave input) results in an IF output power of 4.7 dBm.

The reference frequency for the PLL should be from 12 MHz to 160 MHz and should be applied to the REF_IN pin, which should

be ac-coupled and terminated with a 50 Ω resistor as shown in Figure 46. The reference signal, or a divided-down version of the reference signal, can be brought back off chip at the multiplexer output pin (MUXOUT). A lock detect signal and a voltage proportional to the ambient temperature can also be selected on the multiplexer output pin.

The loop filter is connected between the CP and VTUNE pins. When connected in this way, the internal VCO is operational. For information about the loop filter components, see the Evaluation Board Configuration Options section.

Operation with an external VCO is also possible. In this case, the loop filter components should be referred to ground. The output of the loop filter is connected to the input voltage pin of the external VCO. The output of the VCO is brought back into the device on the LOP and LON pins, using a balun if necessary.

R280Ω

(0402)

RFIN

MUX

RSET CP VTUNE

LODRV_EN

LON

LOP

2:1MUX

VCOCORE

TEMPSENSOR

DECL2P5

DECL3P3

DECLVCO

BUFFER

BUFFER

IFNIFP

2

1 4

53

IP3SET

RFIN

–+

CHARGE PUMP250µA,500µA (DEFAULT),750µA,1000µA

PRESCALER÷2

MUXOUT

REF_IN

ADRF6601

195

8

36

1174 2015 2321 2524 3038 3531

26

PHASEFREQUENCYDETECTOR

THIRD-ORDERFRACTIONAL

INTERPOLATOR

FRACTIONREG MODULUS INTEGER

REG

N COUNTER21 TO 123

×2

÷2

÷4

DIVIDER÷2

SPIINTERFACE

C4310µF

(0603)

C1422pF

(0603)

CPTEST

POINT(ORANGE)

C136.8pF(0603)

C4022pF(0603)

C70.1µF(0402)

VCCRED+5V

VCC

VTUNE

C152.7nF(1206)

C2OPEN(0402)

C1100pF(0402)

R10Ω

(0402)

R380Ω

(0402)

R370Ω

(0402)

R2OPEN(0402)

C4210µF(0603)

C170.1µF(0402)

R63OPEN(0402)

R65 10kΩ(0402)

R9 10kΩ(0402)

R120Ω(0402)

R103.0kΩ(0603)

R620Ω(0402)

R11OPEN(0402)

RFOUT

C16100pF(0402)

R180Ω

(0402)

C41OPEN(0603)

C110.1µF(0402)

C270.1µF(0402)

C290.1µF(0402)

C12100pF(0402)

R80Ω

(0402)

R160Ω

(0402)

C311nF

(0402)

C61nF

(0402)

R55OPEN(0402)

VCC1RED

S1OPEN

R560Ω

(0402)

C51nF

(0402)

R7049.9Ω(0402)

4LO IN/OUT

REF_IN

REFOUT

3

5 1T8

TC1-1-13+

R200Ω

(0402)

R5410kΩ(0402)

R190Ω

(0402)

S2R53

10kΩ(0402)

R350Ω(0402)

R300Ω(0402)

R50OPEN(0402)

R570Ω(0402)

R360Ω(0402)

P19-PINDSUB

VCC_LO VCC2 VCC1 PLL_

EN

CLK

DA

TALE

27 13 12

C8100pF(0402)

R60Ω(0402)

C250.1µF(0402)

C24100pF(0402)

R260Ω(0402)

C230.1µF(0402)

C22100pF(0402)

R250Ω(0402)

C200.1µF(0402)

C21100pF(0402)

R240Ω(0402)

C190.1µF(0402)

C18100pF(0402)

R170Ω(0402)

C90.1µF(0402)

C10100pF(0402)

R70Ω(0402)

2 4 61 3 5 7

C32OPEN(0402)

R51OPEN(0402)

C33OPEN(0402)

R52OPEN(0402)

C34OPEN(0402)

14

DIVBY

4, 2, 1

VCC_MIXVCC_V2IVCC_LO

R270Ω

(0402)

R430Ω

(0402)VCC+5V R59

0Ω(0402)

0854

6-04

6

16

2

9

29

1840393

6

38

37

34 22 17 10 1

8 9

Figure 46. Basic Connections for Operation of the ADRF6601



Data Sheet ADRF6601

Rev. B | of 32

AC TEST FIXTURE Characterization data for the ADRF6601 was taken under very strict test conditions. All possible techniques were used to achieve optimum accuracy and to remove degrading effects of

the signal generation and measurement equipment. Figure 47 shows the typical ac test setup used in the characterization of the ADRF6601.

ROHDE & SCHWARTZFSEA30

IF_OUT

AGILENT 34401A SET TO IDC(SET FOR SUPPLY CURRENT)

RF1 AGILENT N5181A

RF2 AGILENT N5181A

REF_IN AGILENT N5181A

HP 11636APOWER DIVIDER

AGILENT 34980A WITH THREE 34921 MODULESAND ONE 34950 MODULE

ADRF6601 CHARACTERIZATION RACK DIAGRAM.ALL INSTRUMENTS ARE CONTROLLED BY A LABCOMPUTER VIA A USB TO GPIB CONTROLLER, DAISYCHAINED TO EACH INDIVIDUAL INSTRUMENT.

REF_IN

RFIN

5V dc VIA10-PIN DC HEADER

5V dc MEASURED FOR SUPPLY CURRENTAGILENT E3631A 25V SET TO

3.3V, 6V SET TO 5V.RETURNS ARE

JUMPERED TOGETHER

ADRF6601EVALUATION BOARD

GND VIA10-PIN DC HEADER

3.3V dc VIA10-PIN DC HEADER

9-PI

N C

ON

TRO

LLER

DSU

B A

ND

10-P

IN D

C H

EAD

ER

0854

6-04

7

Figure 47. ADRF6601 AC Test Setup




ADRF6601 Data Sheet

Rev. B | of 32

EVALUATION BOARD Figure 50 shows the schematic of the RoHS-compliant evaluation board for the ADRF6601. This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses. FR4 material is also adequate if the design can accept the slightly higher trace loss of this material.

The evaluation board is designed to operate using the internal VCO of the device (the default configuration) or with an external VCO. To use an external VCO, R62 and R12 should be removed. Place 0 Ω resistors in R63 and R11. The input of the external VCO should be connected to the VTUNE SMA connector, and the external VCO output should be connected to the LO IN/OUT SMA connector. In addition to these hardware changes, internal register settings must also be changed to enable operation with an external VCO (see the Register 6—VCO Control and VCO Enable (Default: 0x1E2106) section).

Additional configuration options for the evaluation board are described in Table 10.

EVALUATION BOARD CONTROL SOFTWARE Software to program the ADRF6601 is available for download from the ADRF6601 product page under the Evaluation Boards & Kits section. To install the software 1. Download and extract the zip file:

ADRF6x0x_3p0p0_XP_install.exe file. 2. Follow the instructions in the read me file.

The evaluation board can be connected to the PC using a PC USB port.

To connect the evaluation board to a USB port, a USB adapter board (EVAL-ADF4XXXZ-USB) must be purchased from Analog Devices.

This board connects to the PC using a standard USB cable with a USB mini-connector at one end. An additional 25-pin male to 9-pin female adapter is required to mate the EVAL-ADF4XXXZ-USB board to the 9-pin D-Sub connector on the ADRF6601 evaluation board.

0854

6-05

3

Figure 48. Control Software Opening Menu

Figure 49 shows the main window of the control software with the default settings displayed.





http://www.analog.com/eval-adf4xxx?doc=ADRF6601.pdf

http://www.analog.com/eval-adf4xxx


Data Sheet ADRF6601

Rev. B | of 32

0854

6-04

9

Figure 49. Main Window of the ADRF6601 Evaluation Board Software


ADRF6601 Data Sheet

Rev. B | of 32

SCHEMATIC AND ARTWORK

08546-050

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

NC

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

E-P

AD

VC

C

CP

OU

T

GN

DC

P

RS

ET

RE

FGN

D

VC

C

GNDDIG

DATA

CLK

LE

GNDDIG

OUTPUTEN

GNDBB

GN

DR

F

VC

CB

B

RFR

TN NC

GN

DR

F

VC

CR

F

GN

DR

F

GN

DR

F

INBB

IPBB

GNDBB

GND

LOEXTEN

LON

RE

F_IN

VCC_LOVCC_LO

VCO_LDO

3P3_

LDO

2P5_

LDO

LOP

VCO_IN

RFI

N

IP3S

ET

IFP

IFN

RE

FOU

T/LO

CK

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

1V

CC

1VC

C2

1V

CC

5

1V

CC

_LO

1

1V

CC

_BB

1

1V

CC

_RF

1VC

C1

1V

CC

_LO

1VC

C4

1VC

O_L

DO

1C

P

1

DA

TA

1IP

3SE

T

1 LE

1

CLK

12P5V

1O

SC

_3P

3V13P3V

1

R10

3K

R63

100K

R37

0

DNI

R11

R12

0

0

R62

10K

R65

R9

10K

22P

FC

40C

1422

PF

C13

6.8P

FC

152.

7NF

L2 TBDL1 TBD

C36

DN

I

C35

DN

I

0

R66

R67 0R68

0 D

NI

C41

10U

F

0.1U

FC

9

10U

FC

42

10U

F

C43

P1-

6

P1-

11 2 3 4 5 6 7 8 9P

1

AM

P74

5781

-4

TBD

R27

IP3S

ET

C34

100P

F D

NI

100P

F D

NI

C33

C32

100P

F D

NI

1K D

NI

R52

R51

1K D

NI

1K D

NI

R50

C28

10UF

R47 0 0R48

VC

C

VC

C

1 2 3 4 5 6 7 8 9 10

1112

1516

1820

222324252627282930

3132

3334

3536

3738

3940

21

1314

1719

PA

D

Z1

VC

C_B

B

R60

TBD

R44

DN

I

VC

C

4

6

1

3

2

T3

TC4-1W

R59

0

0

R43

0.1U

FC

29

C25

0.1U

F

DN

IR

58

1D

IG_G

ND

R36

00R

57

123

S2

R53

10K

10K

R54R

5610

K

VC

C

C31

1000

PF

R49

DN

I

1NF

C6

C5

1NF

LO_E

XTE

RN

0

R33

10K

R55

VC

C

32

1S1

OU

TPU

T_E

N

0R

30

R19 0

100P

FC

10

R18 0

DN

I

R2

C12

100P

F

0R25

R26 0

0R38

R8 0

0

R35

1G

ND

0

R29

VC

C

1J1

Y1

R1 0

VC

C_S

EN

SE

SN

S1

SN

S

VC

O_L

DO

LO_E

XTE

RN

2P5V

_LD

O

3P3V

_LD

O

AG

ND

VC

C_S

EN

SE

AG

ND

VC

C

10J1

8J1

R20

0

VCC_BB

VCC_LO

VCC_RF

VC

C_B

B

VC

C_L

O

VC

C_L

O

0R28

R14

DNI

R15 0 C3 10

PF

C4

2200

0PF

0.1U

FC

70R6

C2

0.1U

FC

110

0PF

100P

FC

8

0R7

C11

0.1U

F

RE

FIN

RE

FOU

TR

16 0

0.1U

FC

1910

0PF

C18

C17

0.1U

FC

1610

0PF

0R17

OU

T

C21

100P

F

R24 0

C20

0.1U

F

0.1U

FC

2310

0PF

C22

C24

100P

F0.1U

FC

27

RFI

N

VC

C

0

R31

R32

0

0

R34

2J1

3J1

4J1

5J1

6J1

7J1

9J1

1G

ND

11

GN

D2

VC

C_R

F

IFNIFP

OS

C_3

P3V

VC

C

P4-

T7P

4-T7

P3-

T7P

3-T7

P1-

T7P

1-T7

P1-

T7LO

0R69

1 1A 2 2A 3 3A4 4A5 5A6 6A

T7

15

34 2

T8

P3-

T7

P4-

T7

OU

TPU

T_E

N

IP3S

ET

R70

49.9

3P3V

_LD

O

VC

O_L

DO

2P5V

_LD

O

VTU

NE

P1-

6

R72

0

P1-

1

R71

TBD

Figure 50. Evaluation Board Schematic

Data Sheet ADRF6601

Rev. B | of 32

0854

6-05

1

Figure 51. Evaluation Board Layout (Bottom)

0854

6-05

2

Figure 52. Evaluation Board Layout (Top)

ADRF6601 Data Sheet

Rev. B | of 32

EVALUATION BOARD CONFIGURATION OPTIONS

Table 10.

Component Description Default Condition/ Option Settings

S1, R55, R56, R33 LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in combination with internal register settings, determines whether the LOP and LON pins function as inputs or outputs (see the LO Selection Logic section for more information).

S1 = R55 = open (not installed), R56 = R33 = 0 Ω, LODRV_EN = 0 V

LO IN/OUT SMA Connector

LO input/output. An external 1× LO or 2× LO signal can be applied to this single-ended input connector.

LO input

REFIN SMA Connector

Reference input. The input reference frequency for the PLL is applied to this connector. Input impedance is 50 Ω.

REFOUT SMA Connector

Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The on-board multiplexer can be programmed to bring out the following signals: REF_IN, 2× REF_IN, REF_IN/2, and REF_IN/4; temperature sensor output voltage; and lock detect indicator.

Lock detect

CP Test Point Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that the CP pin should not be probed during critical measurements such as phase noise.

R37, C14, R9, R10, C15, C13, R65, C40

Loop filter. Loop filter components.

R11, R12 Loop filter return. When the internal VCO is used, the loop filter components should be returned to Pin 40 (DECLVCO) by installing a 0 Ω resistor in R12. When an external VCO is used, the loop filter components can be returned to ground by installing a 0 Ω resistor in R11.

R12 = 0 Ω (0402), R11 = open (0402)

R62, R63, VTUNE SMA Connector

Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector.

R62 = 0 Ω (0402), R63 = open (0402)

R2 RSET pin. This pin is unused and should be left open. R2 = open (0402) RFIN SMA Connector RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of

the ADRF6601 is ac-coupled; therefore, no bias is necessary. R3 = R23 = open (0402)

T3 IF output. The differential IF output signals from the ADRF6601 (IFP and IFN) are converted to a single-ended signal by T3.



Data Sheet ADRF6601

Rev. B | of 32

OUTLINE DIMENSIONS

140

1011

3130

2120

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 06-0

1-20

12-D

0.50BSC

PIN 1INDICATOR

4.50 REF0.20 MIN0.50

0.400.30

TOP VIEW

12° MAX 0.80 MAX0.65 TYP

SEATINGPLANE

COPLANARITY0.08

1.000.850.80

0.300.230.18

0.05 MAX0.02 NOM

0.20 REF

4.254.10 SQ3.95

0.60 MAX

0.60 MAX

PIN 1INDICATOR

6.106.00 SQ5.90

5.855.75 SQ5.65

FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

EXPOSEDPAD

(BOTTOM VIEW)

Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad (CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADRF6601ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1 ADRF6601-EVALZ Evaluation Board 1 Z = RoHS Compliant Part.

ADRF6601 Data Sheet

Rev. B | of 32

NOTES

Data Sheet ADRF6601

Rev. B | of 32

NOTES

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