3 Voter Counter

7/25/2019 3 Voter Counter

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3 Voter Counter

Objective

The circuit accepts 3 inputs, and shows the number of Yes

votes on a human-readable seven-segment display. Yes

is

represented by a 1! input value. "or e#ample, if the votes are

yes!, yes! and no!, the display must show the decimal number 2

$since there are two yes! votes%.

Design&e are using ' ways to design ( implement this circuit.

). Brute Force'. Modular

Methodology&henever a voter says yes!, the logic state will be 1.

The *-segment display will display the number of 1!s. +et!s say

when there is only ) yes! voter, the *-segment

should display ).

n order to do so, we need to turn on the +s b!and c!. n other words, b! and c! are 1 and the rest

of the +s are 0. /o, in order to display '! and 3!,

depending upon, how many voters are yes!, we

shall ma0e a circuit. This circuit displays the

number, how many voters say yes!.

Brute Force ApproachThis approach uses '-level /12 circuit structure. t is treated

as one-multiple-input, multiple-output circuit, and implemented

each output using appropriate '-level /12.

Figure P1.1


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Fig P1.2

ruth ableThe truth table clearly shows which segment will glow

depending upon the input. &e can ma0e then, e#pressions for

every segment by using '-level /12.

!1 !2 !" A B # D $ F % ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )) ) ) ) ) ) ) ) ) )) ) ) ) ) ) )) ) ) ) ) ) ) )

able P1.1

$&pressionsn the right side of e#pressions, 4 V), 5 4 V'( C 4 V3for

convenience

).A ' 5C 6 $5 7 C% 6AB C


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'.B 'A C 6 C $ 7 5% 6 $56C% 6

AB C

3.# ' C 7 7 5 6AB C

8.D ' 5C 6 $5 7 C% 6A B C

9.$ 'A 5C 6 $5 7 C% 6

AB C

:.F 'A B C

*.% ' 5C 6 $5 7 C%

Proteus Diagra(

Figure P1." )nside the * " !O$+ * ,ub-circuit


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The ; 3 V1T< ; sub-circuit is simply a combinational logic

circuit designed on the e#pressions for the *-segment display

$Common Cathode%. t ta0es 3 inputs $Votes% and displays the

number of yes! on the *-segment display.

Figure P1.a

Figure P1.b


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Figure P1.c

Figure P1.d


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Modular ApproachThis approach uses two smaller sub-circuits interconnected

together. &e divide the overall design into two sub-circuits, and

implement each sub-circuit using '-level /12 structure. The )st

circuit accepts the 3 e#ternal inputs $V), V', V3% and produces a '-

bit output $/)and /% representing the number of yes! votes. t is

a full adder circuit. The 'ndsub-circuit accepts the /)and /

signals, and drives the * outputs to illuminate the *-segment

display.

Figure P1./

ruth able F ADD$+3/ince, there are two sub-circuits therefore there are two

truth tables. "irst for the ; "=++ < ; and second for the ; *

/>?@T ;.

!1 !2 !" ,0 ,1 ) ) ) ) ) ) ) ) )) ) ) ) ) )


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) ) ) ) )able P1.2 Full Adder ruth able

The "ull dder circuit accepts 3 inputs and adds the total

yes!. @ote when only one input is 1, /)is 1$Aust li0e /um! in a

"ull dder% and when only two inputs are 1, /is 1but /)is 0$Austli0e Carry 1ut! in a "ull dder%. That!s why it is called a ; "=++

< ; Circuit. &hen all inputs are 1, both outputs are 1. n this

way we get total number of yes! or 1! at the output. @ow this

output needs to be processed to ma0e it readable on a *-segment

display.

$&pressions

). ,0' V)V'6 V)V36 V'V3'. ,1' V)7 V'7 V3

Proteus Diagra(

Figure P1.4 Full Adder


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ruth able 5 ,$%M$63

,0'A

0

,1'A

1

A B # D $ F %

) ) ) ) ) ) ) ) ) ) ) ) ) ) )) ) ) ) ) ) )

able P1." ,even ,eg(ent ,ub-circuit ruth able

The *-/>?@T /ub-circuit in "ig 2).9 accepts the two

outputs of the "=++ < /ub-circuit$/( /)% as inputs$( )%,

and produces seven outputs, each for a single segment. The Brst

row of the truth table will display the number ! on * segmentdisplay because both inputs are 0. The second row displays )!

because only )is 1. The third row displays '! because only 'is

1. The last row displays 3! on *-segment display. @ote that the )

is a /um! $"=++


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Proteus Diagra(

Figure P1.5 ,even ,eg(ent ,ub-circuit


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Figure P1.7

#onclusion

5oth approaches can be used to acuire the reuired results.5ut there are some diDerences between them.

6o. Brute Force Approach Modular Approach1. =ses a lot of gates =ses a few gates2. Eard to ebug asy to ebug". =ses /12 rule only =ses /12 with sub-circuits. Convenient for 5eginners ntermediate +evel /0ill

&e can see clearly that ?odular pproach is better than5rute "orce pproach as it uses less gates $less volume too%. t is

divided into parts$sub-circuits% and therefore easy to debug. The

5rute "orce pproach on the other hand, is very helpful for

beginners because only /12 rule is applied to whole truth table,

e#pression is obtained and simpliBed and that simpliBed


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e#pression is implemented while The ?odular pproach uses sub-

circuits, so one should spend time to thin0 the appropriate logic to

acuire the reuired results and ta0es more time but when

everything is clear, designing a circuit should not be a big deal.

3 Voter Counter

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