3 rd Nov. 2008 CSV881: Low Power Design1 Power Estimation and Modeling M. Balakrishnan.
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Transcript of 3 rd Nov. 2008 CSV881: Low Power Design1 Power Estimation and Modeling M. Balakrishnan.
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3rd Nov. 2008 CSV881: Low Power Design 1
Power Estimation and Modeling
M. Balakrishnan
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Outline
• Estimation problem• Estimation at different levels• System level• Algorithmic level• Processor level• RT level• Gate level• Circuit level
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Power Estimation Problem
The objective in Power estimation is similar to other estimation problems; one tries to minimize time for estimation to achieve a certain accuracy or maximize accuracy for a given effort.
Hi-fidelity is another objective
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Abstraction Levels
• Higher the level of abstraction, it is likely to take less time but also produce lower accuracy
• Suitable models to speedup estimation at higher levels
• Primitive operations or structures keep on changing as we move up the abstraction levels
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System Level
• Energy estimation in terms of very coarse granularity events e.g. specific tasks initiated by specific triggers or interrupts
• Estimates for components like memory, buses etc. handled separately
• Support for system level power management decisions
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System Level Approaches
• Early approaches [3] were based on Monte-Carlo simulation.
• Random input vectors were generated and power data for them generated using simulation
• Approaches varied in terms of efficiency and accuracy. Some approaches provided for confidence level to be controlled
• Quality of results depend on the “statistical” properties of the input vectors and their impact on power
• Difficult to handle various power modes of operation• A recent approach for IP power estimation [4] works with
hierarchical models
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Park et al [4]
• Estimation at different hierarchical levels– Direct tradeoff between accuracy and time for
estimation
• Creation of power models at different levels
• TLM (Transaction level modeling)
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Park et al[4] contd
H.264 Prediction IP
Active IDLE
Inter Intra
Luma Chroma Luma(16X16)
ChromaLuma(4X4)
Loc 0 Loc m Mod 0 Mod n
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Algorithmic/Behavioral Level
• Models of RT level components expressed in terms of input characteristics that can be extracted from the behavior– e.g. adder operation energy in terms of word-length
and hamming distance of inputs– e.g. memory energy per read or write access
• Energy estimation based on weighted sum of such basic operations
• Behavioral transformations to be supported in terms of energy change
• Prediction of interconnect power consumption to support data transfer is an issue
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Algorithmic Energy Components
Total energy consumed =
energy consumed in computation
+ energy consumed in storage access
+ energy consumed in data transfer
+ energy consumed in control
(function of allocation as well as binding)
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Adder Module Characteristics
Hamming distance
Energy
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Processor Level
• First proposed by Tiwari et. al [5,6] for software power estimation
• The methodology is based on measuring power consumption for each instruction and
• Overall energy consumption is computed by taking a weighted sum of number of instructions of each type. The weighting factor is the power consumption of the individual instructions
• This approach based on measurements is valid only for a processor which has been fabricated. Sama et.al [7] have modified it to create an instruction level power model with a gate level simulator
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Vivel Tiwari’s Model[5]
Energy cost of an instruction =base cost (measuring current on a repetitive set of identical instructions)
+ circuit state overhead cost (measuring current on pairs of instruction)
+ resource constraint cost (to account for stall cycles due to resource contention)
+ cache energy costs (to account for cache misses)
Tiwari observed that at least for CISC processors, operand and data value variations affect less than 3% of the total energy consumption.
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Lee et al [6]
• Approach similar to the one proposed in [5]. Processor used is Fujitsu DSP processor instead of DX486 (Intel processor)
• Base cost of the instructions varies significantly unlike CISC processor
• Instructions classified into 6 different classes to reduce the size of measurements. (individual as well as pair wise measurements)
• Power minimization strategies suggested include– “Intelligent” register bank assignment– Instruction packing to reduce cycles– Instruction scheduling to reduce circuit state switching energy– Operand swapping to reduce computation in Booth’s algorithm
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Sama et al[7]
• Instruction set model similar to the models proposed by Tiwari[5]
• Energy numbers obtained through a power simulator rather than actual measurement; thus models possible at design time and can be part of micro-architecture and/or instruction set architecture exploration
• Considerable speedup over gate-level or circuit-level simulation of the processor model
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Issues in Instruction Set Power Models
• Instructions are not executed one at a time– All current processors are deeply pipelined and as
many instructions are active concurrently in the pipeline, their interactions should also be accounted for
– Tiwari[5] also measured interactions between consecutive instructions from different classes
• The effect of varying data (as well as address) is ignored in the model– Though can be accounted by an additive factor
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RT Level Estimation
• Models of RTL components like adders, comparators, decoders, multiplexers etc.
• Models based on effective capacitance
• Switching activity estimated from the RTL code
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Gate Level Estimation
• Effective capacitance models at the gate level in the library
• Switching activity is estimated for a given application (specified as a set of Boolean equations)
• Switching activity could be based on probabilistic input vector characteristics or actual input vector characteristics
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Circuit Level
• Comparison is always with SPICE – How much faster and how close in terms of
prediction?
• Compact set of vectors– How representative are these vectors in terms of
actual use?
• Powermill [3] a popular tool achieves 2 to 3 order speedup while being within 10% accuracy. This is based on event driven timing simulation and uses a simplified table –driven device models.
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References
• M. Pedram, “Power Minimization in IC Design”, ACM TODAES, Vol. 1., No. 1, Jan. 1996, pp. 3-56
• Macii et al, “High-level Power Modeling, Estimation and Optimization”, DAC 1997
• Burch et al, “ A Monte-carlo Approach for Power Estimation”, IEEE TVLSI, Vol. 1, No. 1, Mar. 1993. pp. 63-71
• Park et al, “System Level Power Estimation Methodology with H.264 Decoder Prediction IP Case Study”, pp. 601-608
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References (contd)
• Tiwari et al, “Power Analysis of Embedded Software: A First Step towards Software Power Minimization”, IEEE TVLSI, Vol. 2, No. 4, Dec. 1994, pp. 437-444
• Lee et al, “Power Analysis and Minimization Techniques for Embedded DSP Software ”, IEEE TVLSI, Vol. 5, No. 1, Mar 1997, pp. 123-135
• Sama et al, “Speeding up Power Estimation of Embedded Software”, ISLPED 2000, pp. 191-196