3-phase half-wave converter

1.The mean output voltage is zero for 2.Negative average output voltage occurs when

3.Power inversion is possible , if a load with an e.m.f. to assist the current flow.

In general, for an m-phase half-wave converter, the mean output voltage is given by If m = 3 (3-phase),

• With an RL load, at Vdc = 0, the load current falls to zero. Thus, continuous load current does not flow for an RL load for

α ≥∏/2.

Half-wave controlled rectifier with free-wheeling diode

The diode prevents the load voltage from going negative, thus inversion is not possible

• For α≤∏/6 , without voltage zeros occurring, the mean output voltage is given by

• For α ≥∏/6, voltage zeros occur and the negative portions in the waveforms do not occur. The mean output voltage is given by

cos2

33mdc VV

60

))6

cos(1(32

sin32

6

m

mdc

V

tdtVV6

56

A delay angle of greater than would imply a negative output voltage, clearly not possible with a free-wheeling load diode.

3-phase full converter

For , the output voltage is non-zero at all instances, hence the load current is continuous for any passive load. Beyond , the load current may be discontinuous. For , the current is always discontinuous for passive loads. Power inversion is possible with an e.m.f. source. If inversion is not required, a free-wheeling diode is normally used

Overlap• Overlap is the phenomenon due to the effect

of source inductance on the a.c. side. The current commutation is delayed due to the source inductance which is normally the leakage reactance of a transformer (as X >> R for a transformer, the source resistance is usually neglected).

• The waveforms with commutation period, denoted by during which both the outgoing diode and incoming diode are conducting.

• This period is also known as “overlap” period. During the overlap period, the load current is the addition of the two diode currents, the assumption being made that the load is inductive enough to give a constant load current.

• The load voltage is the mean of the two conducting phases during overlap period. The effect of overlap is to reduce the mean output voltage.

A circulating current i can be considered to flow in the closed path formed by the 2 conducting diodes D1 and D2. Ignoring the diode voltage drop

dtdiL

dtdiLVV 12

The voltage V2 - V1 = the difference between the two phases = 0 at time zero. (t = 0)

For t > 0, the voltage

tV

tVVV

L

m

sin2

sin312

Vm : peak value of the phase voltage VL : r.m.s. line voltage

Therefore,

CtLV

dttLVi

dtdiLtV

m

m

m

cos23

sin23

2sin3

At t = 0, i = 0

LVC m

23

Hence,

)cos1(2

3 tLVi m

Proof of v2 - v1,

sin3)150'sin(3

'cos21'sin

233

}'cos23'sin

23{

}240sin'cos240cos'sin'{sin

)}240'sin('{sin

)240150sin(

)150sin(

0

00

012

002

01

mm

m

m

m

m

m

m

VV

V

V

V

Vvv

Vv

Vv

221

21

vvv

dtdiLv

dtdiLvv

If the datum is shifted by 1500,

cos6

sin

)150'cos(21

}'cos23'sin

21{

21

}240sin'cos240cos'sin'{sin21

)}240'sin('{sin21

2

)240150sin(

)150sin(

0

00

021

002

01

m

m

m

m

m

m

m

V

V

V

V

VvvVv

Vv

The overlap is complete when i = IL , at t

m

L

mL

VXI

LXXVI

321cos

;)cos1(23

The mean output voltage is given by

)cos1(4

33

]cos6

sinsin[32

10

65

6

m

mmdc

V

dVdVV

orVdc = Vdc without overlap - reduction of Vdc due to overlap.

(i)Vdc without overlap =

65

6233sin

321 m

mVtdtV

(ii) Reduction of Vdc due to overlap

Lmdc

LL

I

IXVV

IXILdiL

dtdtdiLdtvv

L

23

233

23

23

23

23

2321

0

00

12

)cos1(23 XVISince m

L

)cos1(4

33

mdc VV

Overlap in controlled 3-phase converter

It can be seen that with a firing delay angle , a finite voltage is present,

where t = time from the start of commutation, when i = 0.)sin(312 tVVV m

dtdiLt 2)(sin3

which gives

)}(cos{cos23

tLVi m

Overlap being complete when i = IL and t = . )](cos[cos23

LVI m

L

Compared to the uncontrolled case = 00, the overlap angle is shorter and the current change during commutation will be towards a linear variation. The mean voltage of the load is given by : -

)](cos[cos4

33

]cos6

sinsin[

321

65

6

m

mmdc

V

dVdVV

Remark :

1. The location of the waveform during overlap is at a position midway between the outgoing and incoming voltages . 2. For the 2-phase waveform , the load voltage = 0 during overlap period.

Overlap for inversion

A d.c. machine as the load element, acting as a motor which the converter rectifying . However, if the load voltage VL reverses and 090

the d.c. machine will act as a generator. If the machine runs in the same direction of rotation, it can only generate by having its armature or field connections reversed

It is only possible to commutate current from thyristor T1 to thyristor T2 while the instantaneous voltage of phase 2 is higher than phase 1 (i.e. while V2 is less negative than V1). At = 1800, V1 and V2 and the relative voltage between the two phase after this reverses , making commutation impossible, hence 0180

is the limit of operation.

.1800

When in the inverting mode, it is more usual to designate the firing position as firing advance angle

The effect of the overlap period

is to delay the commutation. The waveform during overlap has a voltage midway between the incoming and outgoing voltages. If the commutation is not complete before the two commutating phase reach equal voltage values, then transfer of current is impossible as the load current will revert to the outgoing

thyristor.The overlap angle must be less than the firing advance angle . In practice

can never be reduced to zero.