3 How to Create the Parts

How to Create the Parts?(Layout, Design Rules, and Stick Diagram)

Lecturer 3

Taufiq Alif Kurniawan, ST, MT, M.Sc.EngDepartemen Teknik Elektro, Universitas [email protected]

Introduction Reading

◦ W&H 3 3 Layout Design Rules W&H 3.3 – Layout Design Rules◦ W&H 6.1-6.2.2 – Layout parasitics◦ +W&H 3.6 – Advanced layout rules

IntroductionIn this lecture we look at the effect that fabrication constraints have on the layout we need to produce For this class we will use a very simple the set of design rules, since it is hard enough with these rules, but in real life, the rules are much more complex. Just the book describing the rules for modern technologies can be many hundreds of pages. Since even dealing with the simple rules can be complex, we will also introduce the notion of a stick diagram, and the basic rule of 8 for sizing. We finally look at some of the parasitic effect of the layout at the end of the lecture.

Geometric Design Rules

Layer Fabrication uses a set of layers that are not natural for

a designer:◦ Some of these layers are really the combination of layers a

designer would like to think about. For example “active” is really all the diffusion layers merged together.

◦ Many of these layers can be derived from other layers. For example the selects and the threshold adjust implants could be derived from the diffusion type and where poly crosses the diffusion

◦ So rather than working at the actual mask layers, most designers create a set of more intuitive layers for the them to work with.

Requires a CAD tool to generate the real mask layers for fabrication

◦ Generating the manufacturing data is called ‘tapeout’◦ Can have funny design rules in design layers to make sure

this process is possible

Layer Choice The layers a designer uses is set by the

technology files◦ These tell the tools what to do◦ Allow the tools to handle many different

technologiesDominant layout editor is ‘Virtuoso’

◦ Dominant layout tool used in the industry◦ Can handle very complex layout rules can handle

very complex layout rules But we can’t

The other is SCMOS design technology◦ Created 20 years ago to make layout rules simpler◦ They were scalable, and still kind of work today

SCMOS Design Rules Highlights

Stick Diagram We represent the different wiring layers with

different colors

Wires on the same layer that touch ALWAYS connect. There is no way to jumper a wire without changing layers.

Wires on different layers can cross without connections. To form connections between different layers you need to explicitly draw a contact.

Basic Layout Planning

Here are a few simple guidelines to CMOS layouts◦ You need to route power and ground (in metal)

No one will auto connect it for you.

◦ Try to keep nMOS devices near nMOS devices and pMOS devices near pMOS devices near pMOS devices. So nMOS usually are placed near Gnd, and pMOS near Vdd

Run poly vertically and diffusion horizontally, with metal1 horizontal (or the reverse, just keep them orthogonal)◦ Good default layout plan

Keep diffusion wires as short as possible (just connect to transistor)

All long wires (wire that go outside a cell, for example) should be in either m1 or m2.

Try to design/layout as little stuff as possible (use repetition/tools)◦ Critical issue

Transistor RulesCMOS transistors are generally defined

by at least four physical masks◦Active (diffusion, diff or thinox) all areas where either n- or p-type diffusion is to

be placed, or where the gates of transistors are to be placed.

◦n-select (n-implant, nimp or n+)◦p-select (p-implant, pimp or n+) What type of diffusion required. n-select

surrounds active regions where n-type diffusion is required, etc.

◦Polysilicon (poly or polyg)

Transistor Rules (cont’d)

Contact and Metal RulesThere are several generally

available contacts:◦ Metal to p-active (p-diffusion)◦ Metal to n-active (n-diffusion)◦ Metal to polysilicon◦ Metal to well or subsrate

Metal rules may be complicated by varying spacing dependent on width : as the width increases, the spacing increases. Metal overlap over contact might be zero or nonzero.

Via RulesVias are normally of uniform size

within layer. They may increase in size toward the top of a metal stack. For instance, large vias required on power busses are constructed from an array uniformly sizes vias.Other RulesDiffering nMOS and pMOS gate

lengthsetc.

MOSIS design rule options

• SUBM rules are somewhat more conservative than SCMOS rules, DEEP rules are even more conservative.

MOSIS design rule

MOSIS design rule (cont’d)

An Example

• Choose global directions for routing layers• Position power lines in top/bottom layer of metal

An Example – Step 2

• Cluster together NMOS with NMOS and PMOS with PMOS

• Generally keep gate orientation the same


• Arrange transistors so that common gates line up


• Connect everything up

Convert to real layout

Fabrication is more complex than thatAs technology has scaled, design rules

have become complex◦Problem is we are running into physics

limitationsWe are creating features smaller than the

wavelength of lightProcessing steps have their own

constraintsThe following slides talk about some of

these issues The following slides talk about some of these issues◦Optional material

Metal Density• Old rule: minimum metal density• For Al, metals were etched away

Antenna Rules• Reactive ion etch charges up metal lines

• Charge can accumulate and zap a gate oxide• If a gate sees a long metal before a

diffusion does

CMOS Process EnhancementsSilicon on Insulator

◦ Process where the transistors are fabricated on an insulator.

◦ Two main insulators are used, SiO2 and sapphire.

◦ Advantage : elimination of the capacitance between the source/drain regions and body, leading to higher-speed devices.

CMOS Process EnhancementsHigh-k Gate Dielectrics

◦ MOS transistors need high gate capacitance to attract charge to the channel very thin SiO2 gate dielectrics. C = €.A/d

◦ Gate leakage will be unacceptably large in such thin gates.

◦ Gates could use thicker dielectrics and hence leak less if a material with higher dielectric constant were available.

◦ HfO2 (k = 20), ZrO2 (k = 23), silicon nitride (k = 6.5 – 7.5) called high-k dielectrics in contrast to SiO2 with k = 3.9.

CMOS Process EnhancementHigher Mobility◦ Increasing the mobility of the semiconductor

improves drive current and transistor speed, this has been achieved by using silicon germanium (SiGe) for bipolar transistors.

◦ SiGe can be constructed on conventional CMOS processing by adding a few extra implantation steps.

◦ The resulting bipolar transistors have extremely good radio frequency (RF) performance.

◦ Combination of excellent RF performance and high-density digital CMOS, SiGe-based CMOS processes find the wide application in communications circuits involving RF and high-speed switching.

Circuits ElementsCapacitors

◦ The most common capacitor used in CMOS processes today is the MIM (metal-insulator-metal) that is normally placed between metal layers n and n-1 (n is normally the top level metal layer) to minimize the stray capacitance of the bottom plate.

◦ Another type of capacitor that is possible in scaled processes is the fringe (or fractal) capacitor, which is composed of interdigitated metal fingers.

Circuits Elements (cont’d)Capacitor

1-4 fF/um2

• High-Q• Very linier• High-

valued capacitor with low parasitic capacitance to gnd

Circuits Elements (cont’d)Resistors

◦Resistor can be built from any layer, with final resistance depending on the resistivity of the layer.

◦Building large resistances in a small area requires layers with high resistivity, particularly polysilicon and diffusion.

◦Another material used for high-quality resistors is nichrome need a special proc. steps.

Circuits Elements (cont’d)Resistor

Meander structure

Circuits Elements (cont’d) Inductors◦ The most common monolithic inductor is the spiral inductor,

which is a spiral upper-level metal.◦ The parameters of interest to a designer are its inductance,

the Q of the inductor, and self-resonant frequency.◦ High Q low phase-noise osc, narrow filters and low-loss

circuits. Q-values for typical planar inductors on a bulk process are in the range from 5 to 10.

◦ Reduction in Q occurs because The resistive loss in the conductors (Rs) Eddy current loss in the resistive silicon substrate (Rp).

◦ Effort to increase Q Removing the substrate below the inductor using MEMS. Used bond wires for high-Q inductor. Increase the thickness of the top level metal. Using patterned ground shield in polysilicon under the inductor to

decrease substrate losses.

Circuits Elements (cont’d)Inductor

Power and Delay : A Gate’s MetricsWhen we use a gate we care about its logic

function◦ That is the desired output

It also consumes “resources” that care about◦ Delay

The output becomes valid some time after inputs settle

◦ Power The gate also consumes some energy from the power supply

◦ Area This is often less important in today’s chips The wires needed to connect the gates takes the most space

These “charges” are not difficult to estimate◦ But you will need to estimate them to be a good

designer

R and C is All You NeedDelay can be estimated by

simple RC modelsPower can be estimated (mostly)

from C aloneBut to do either, we need to have

a R, C model of gates◦And the wires And the wires

Resistance? Capacitance?Resistance

◦Relates current to voltage (V = IR)◦Measures how easy it is for current to flow◦ (Actually weird – relates a force qV/L to a

velocity)Capacitance

◦Relates charge to voltage (Q = CV)◦Exists between any two conductors◦Causes delay in circuits (t = RC) and data

storage (memory)◦Causes energy consumption

ResistanceResistance of a conductor

◦ Resistivity r * Length/Area◦ Designer does not control r, t◦ Generally deal with r/t◦ Called ohm/square (Rsq)

That’s why LONG wires have higher resistances

Transistor ResistanceFor transistors

◦Designer chooses W and L

Wider transistor◦More current ◦Lower R

R is a surrogate for ◦1/Ids◦R depends on Vdd

R increases as Vdd decreases

Rules of Thumb for Resistance

Capacitance and Delay

Load CapacitanceCload comes from three factors:

◦Gate capacitance of driven transistors.

◦Diffusion capacitance of source/drain connected to the wire.

◦Wire capacitance 3. Wire capacitanceToday, a 1u technology is the

really cheap technology that students use and advanced processes are running at 0 045u.

Real Wires

Rules of Thumb for Capacitance

Since The Tool Has The LayoutLet it estimate the resistance and

capacitance◦Can compute more accurate numbers

But it only can do this when the layout is complete◦Which is why the simple models are still useful

If you know the wires is going to be 10mm◦You can estimate its capacitance◦Which is important

Need to know load to “size” transistor/gates properly

Even BetterLet someone else do the design

◦Use their cells

Homework 11. Consider the design of a CMOS compound OR-OR-AND-INVERT (OA122) gate

computing F=(A+B).(C+D).

a. Sketch a transistor-level schematic

b. Sketch a stick diagram

c. Estimate the area from the stick diagram

d. Layout your gate with a CAD tool using unit-sized transistors (optional)

e. Compare the layout size to the estimated area

2. A carry lookahead adder computes G=G3+P3(G2+P2(G1+P1G0)). Consider designing a compound gate to compute G.

a. Sketch a transistor-level schematic

b. Sketch a stick diagram

c. Estimate the area from the stick diagram

d. Layout your gate with a CAD tool using unit-sized transistors (optional)

e. Compare the layout size to the estimated area

Please using TSMC 0.18u deep submicron standard, deadline : 12/10/2011

3 How to Create the Parts

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