3-Dimensional Monolithic Nonvolatile Memories and the Future of Solid-State Data Storage

Dr. Michael A. VyvodaDirector, Technology Transfer and Operations

3D Technology GroupSanDisk Corporation

February 8th, 2008

22

Outline

Flash memory market dynamics: what drives technology advances?

The floating-gate technology roadmap

Scaling challenges: what will replace the floating gate?

Monolithic 3D memory: technical overview and future potential

33

Flash Memory Market Dynamics

44

Strong Demand Drivers of Flash Market Growth

Source: Gartner Dataquest, November 2006

Imaging Video & PCAudioDataBillions of MB

Lifestyle Storage

-

2,000

4,000

6,000

8,000

10,000

12,000

14,000

16,000

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010

Other Automotive PC Gaming Mobile Phone Camcorder USB Drive Media Player Digital Camera

15.4 Trillion MB

1.4 Billion MB

Media Player

Mobile Phone

PC

USB

Bits shipped routinely doubles-to-triples year-over-year, fueled by rapid average-selling-price (ASP) reduction (next page)

This is enabling exciting new markets such as flash-based MP3 players and video recording

55

Continual $/MB Reductions Driving New Markets

SanDisk Retail Selling Price per MB ($/MB) - Log Scale

1999Q1Q2 Q3 Q4 2000Q1Q2 Q3 Q4 2001Q1Q2 Q3 Q4 2002Q1Q2 Q3 Q4 2003Q1Q2 Q3 Q4 2004Q1Q2 Q3 Q4 2005Q1Q2 Q3 Q4 2006Q1Q2 Q3 Q4

3-4 Quarter Cyclicality

43% Annual ASP/MB Decline Trendline

Source: SanDisk

2001 DownCycle

2007 Down Cycle

Persistent, unrelenting price reductions, enabled by aggressive technology innovation, driving new markets shown on previous page

Superimposed boom/bust cycles of more benign/more rapid ASP decline

ASP

/MB

66

Projected Flash Trends: 2008 - 201140%-50% annual price reductions sustainable only by top tier players

Smooth transitions to 5Xnm (2007), 43nm (2008/2009)Transition points to date have been limited by photolithographicconstraints (more on this later)

Increasingly more complex NAND (Floating-Gate to Charge-Trap-Flash) transitions at 32nm, 22nm (2009-2011)

3- and 4-bit-per-cell critical for competitiveness in 2009-2011

200mm Fabs no longer competitive; 300mm wafers are now the norm in cutting-edge Fabs

In next 1-2 years capacities should grow dramatically: 512MB-2GB 4GB-32GB

In next 3-5 years cumulative price reductions (~10X from 2007 to 2011) should become disruptive to DVD, HDD (hard disk drive), stimulate huge demand and create new Flash markets

77

Sub-segment Market Growth

88

USB (“Thumb Drive”) Market Size

0

50

100

150

200

250

2005 2006 2007 2008 2009

Source: Gartner Nov '06

M Units

2,200

2,300

2,400

2,500

2,600

2,700

2,800

2,900

M $

UFD Units

UFD $

18% compound-annual-growth-rate (CAGR) in units shipped from 2006 2009, much higher than the semiconductor industry in aggregate

Dollar growth less strong due to ASP declines

99

Flash MP3 Player Market Size

0

50

100

150

200

250

300

2003 2004 2005 2006 2007 2008 2009

Source: Gartner Nov ‘06 M Units

Very strong growth in the 2003 2006 timeframe as MP3 player manufacturers adopted flash memory

16% CAGR 2006 2009, as with USB showing continued strong growth

1010

Source: DSC Forecast IDC Sep‘06, Installed Base: SanDisk Estimates

DSC Shipments and Installed Base

-20406080

100120140160180200220240260280300

2005 2006 2007 2008 2009

Installed Base 4 Years shipments

Digital Still Camara (DSC) Market Size

Roughly 120M DSC units ship per year, with a 260M DSC installed base (!)

~240M Flash cards sold per year with market size

1111

Video Consuming More Memory

Video Capture becoming a large driver of bit growth

IDC predicts that 4800 PBs will be consumed by Video in 20091

Today 20% of all PBs used in Video is used for archival storage and will grow to >40% through 20091

Camera phones are a large component of this

0

500,000,000

1,000,000,000

1,500,000,000

2,000,000,000

2,500,000,000

3,000,000,000

3,500,000,000

4,000,000,000

4,500,000,000

5,000,000,000

Cap

ture

d G

igaB

ytes

2006 2007 2008 2009

Consumer DVC

DSC

CamPhone

DVCCAGR 34.6%

DSCCAGR 25.8%

CamPhoneCAGR 42%

Source1: IDC Dec. 06

1212

Projected SSD Penetration in Notebooks by 2010

Solid-state-drive (SSD) adoption driven by price elasticity and MLC adoption (must reasonably compete with rotating-media)SSD penetration in ~20% of the notebook market = 32M units1300 PB of NAND flash to be used in SSDs or 11% of NAND outputTAM >$3B in 2010 $100/system ASP

0

5

10

15

20

25

30

35

2006 2007 2008 2009 2010

Uni

ts (M

illio

ns)

0

200

400

600

800

1000

1200

1400

Meg

abyt

es (B

illio

ns)

Units MB

Source: Gartner, December, 2006 Notebook market in 2010 is estimated at 153M units

1313

Finally: Mobile Phones as the Market Leader

0

1400

1200

1000

800

600

400

200

2005 20102009200820072006

Worldwide Handset Sales (MU)

Source: Strategy Analytics, December 2006

Shipments of Slotted Phones (MU)

500M phones with Flash-card slots shipped in 2007, projected to almost double by 2010

1414

Conclusions – Market Dynamics

The solid-state data storage market, dominated by Flash memory, has grown and will continue to grow very rapidly in the foreseeable future

This growth has been driven entirely by the effects of price elasticity: lower prices lead to nonlinear growth in bits shipped, due to the appearance of new markets for memory

The markets for Flash memory are now very diverse, ranging from music to video to still images to hard-disk replacements

1515

NAND Technology Roadmap

1616

NAND Memory Product Roadmap

1G

16G

4G

2G

8G

20072005 2006 20092008 2010

32G

Source: SanDisk

64G

96G

128G

32nm

32nm

43nm

43nm

56nm70nm

Released 56nm

Prod

uct M

emor

y C

apac

ity

Near-yearly technology-node transitions are responsible for the price declines and bit-growth described in the previous slides

50% year-over-year price declines matched by YOY cost declines

1717

New Process Node Transition Every Year

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

2004 2005 2006 2007 2008

43nm

56nm

70nm

90nm

130nm

Technology Transition for Total Captive Wafer Production – % of GB

Source: SanDisk

1818

Going Beyond 2 Bits/Cell (“MLC”)

4 bits/cell16 levels 1

111

0000

0010

1 bit/cell2 levels(“SLC”)

0 1

2 bits/cell4 levels(“MLC”)

00 01 10 11

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1110

1101

0001

3 bits/cell8 levels(“x3”)

000

001

010

011

100

101

110

111

Syst

em E

xper

tise

Incr

easi

ngly

Im

port

ant

Very advanced controller chips required to move above 2-bit/cell

Signal processing and other algorithm innovations to maintain high write speeds and data retentionWear-leveling algorithms to increase endurance

1919

Multi-bit-per-cell Implementation

0.010.01

0.00010.0001

Effe

ctiv

e C

ell S

ize

0.10.1

0.0010.001

JanJan--‘‘0404

JanJan--‘‘0505

JanJan--‘‘0606

JanJan--‘‘0707

JanJan--‘‘0808

JanJan--‘‘0909

JanJan--‘‘1010

JanJan--‘‘1111

JanJan--‘‘1212

90 nm90 nm 70 nm70 nm 56 nm56 nm 43 nm43 nm 32 nm32 nm 2x nm2x nm

Binary

MLC (2b/cell)

MLC (3b/cell)

MLC (4b/cell)

Immersion Litho ~56-nmSuper SA-STI New Structure

New Materials

2G4G

8G8G

16G

4G8G

16G16G

32G64G

32G64G

64G

Source: SanDisk

2-bit-per-cell (MLC) has been mainstream for several years now, among the top-tier suppliers3-bit-per-cell (x3) on SanDisk’s 56nm technology will ramp in mid-’08

2020

Photolithography as a Technology Enabler

70nm

56nm

43nm

32nm

2xnm

2005 2006 2007 2008 2009 2010

Further Aggressive shrink with immersion & hyper NA

Dry ArF λ=193nmNA < 1.0

EUV

Immersion ArF λ=193nmHyper NA >> 1.0

Immersion ArF λ=193nmNA >> 1.0

Wet ArF l=193nmNA > 1.0

Source: SanDisk

For the past several years, brute-force physical scaling as lead the way to technology-node transitionsImmersion lithography as a key enabler for 56nm and onwards

2121

Scaling Challenges and Alternate Devices

2222

Scaling Challenges

Physical limitationsHow do we print, etch and fill lines/spaces below 3xnm?To continue on the Moore’s Law trajectory of cost reduction, innovation is needed

Cell-to-cell couplingVt shift due to coupling fromadjacent cells exacerbated attighter geometries

Electron-loss tolerance(from floating gate)

Reduced allowance for electron loss to avoidlarge Vt shift Source: Kim and Jeong, 2007 IEDM

2323

SeagateNanochipIBM(?)

Not sure

Good.Tip size and

scan precision

only dependent

Not Known. Potentially very high

Not known. Storage media

dependent

Not compatible.

Very small (nm) Tip size and

scan precision

dependent

Probe Probe StorageStorage

In development cell level(many companies)

Has potential.

Not proved.

Good

No data

Potential small. Scales

poorly

Potential good. But

no sufficient data

Small~4F²

RRAMRRAM

SanDiskToshiba

Samsung MacronixToshiba

Freescale4MbSamsungIBM 16Mb

FujitsuRamtron1Mb

In Development Intel, IBM,Samsung 512MbQuimonda

Spansion1Gb (ORNAND)

In Development Samsung SanDisk / Toshiba, Macronix

SanDisk Toshiba SamsungHynix, Micron

Company

No DataHas potential.

NoNoHas potential. Not proved on

products.

2 bits proved.4 bits ??

Possible with

improved material

Yes. In producti

on.

MLC Capability

GoodGoodPoor. Write

current increases

with scaling

PoorQuestionable. Endurance is

affected by the volume of the PCM material

Down to 5x nm

Good down to 2xnm. Possible 1xnm(?)

Good down to 2x nm

Scalability

No DataComparable w/ NAND (?)

Theoretically infinite

108 -1012

~105104104104-105Endurance

No DataVery SmallVery High5-10 maScales poorly

Small ~1µa

High~mA

Medium10 –

100µa

Very SmallVery Small

W/E Current per cell

GoodGoodPoorPoorEtching difficult

Good Compatible with back

end process

GoodGoodGoodCMOS Integration

Very small 4F2 /n

Small~4F²Large ~ 30F²

Large ~20F²

Small ~6F²Medium ~10F²

Small ~ 4F²Small ~ 4F²

Cell Size

3D Diode3D Diode3D NAND3D NANDMRAMMRAMFeRAMFeRAMPCMPCMMirror BitMirror BitSONOSSONOSFG FG NANDNAND

NONVOLATILE MEMORY TECHNOLOGIES COMPARISONNONVOLATILE MEMORY TECHNOLOGIES COMPARISON

SeagateNanochipIBM(?)

Not sure

Good.Tip size and

scan precision

only dependent

Not Known. Potentially very high

Not known. Storage media

dependent

Not compatible.

Very small (nm) Tip size and

scan precision

dependent

Probe Probe StorageStorage

In development cell level(many companies)

Has potential.

Not proved.

Good

No data

Potential small. Scales

poorly

Potential good. But

no sufficient data

Small~4F²

RRAMRRAM

SanDiskToshiba

Samsung MacronixToshiba

Freescale4MbSamsungIBM 16Mb

FujitsuRamtron1Mb

In Development Intel, IBM,Samsung 512MbQuimonda

Spansion1Gb (ORNAND)

In Development Samsung SanDisk / Toshiba, Macronix

SanDisk Toshiba SamsungHynix, Micron

Company

No DataHas potential.

NoNoHas potential. Not proved on

products.

2 bits proved.4 bits ??

Possible with

improved material

Yes. In producti

on.

MLC Capability

GoodGoodPoor. Write

current increases

with scaling

PoorQuestionable. Endurance is

affected by the volume of the PCM material

Down to 5x nm

Good down to 2xnm. Possible 1xnm(?)

Good down to 2x nm

Scalability

No DataComparable w/ NAND (?)

Theoretically infinite

108 -1012

~105104104104-105Endurance

No DataVery SmallVery High5-10 maScales poorly

Small ~1µa

High~mA

Medium10 –

100µa

Very SmallVery Small

W/E Current per cell

GoodGoodPoorPoorEtching difficult

Good Compatible with back

end process

GoodGoodGoodCMOS Integration

Very small 4F2 /n

Small~4F²Large ~ 30F²

Large ~20F²

Small ~6F²Medium ~10F²

Small ~ 4F²Small ~ 4F²

Cell Size

3D Diode3D Diode3D NAND3D NANDMRAMMRAMFeRAMFeRAMPCMPCMMirror BitMirror BitSONOSSONOSFG FG NANDNAND

NONVOLATILE MEMORY TECHNOLOGIES COMPARISONNONVOLATILE MEMORY TECHNOLOGIES COMPARISON

(CTF)

2424

NVM Technology – Next Five Years

Floating Gate (FG) NAND Likely scalable to ~20nmx3 will likely become mainstream by 2009x4: SanDisk plans to lead through system/controller solutions, initially targeting A/V markets (starting 2008, growing impact in later years)

Charge Trapping (CTF) NAND Advocated by Samsung and Hynix for below 40nm (~2009)Planar structure has scaling advantages, unknown difficulties/risks x3, x4 implementation may be more challenging for CTF

NROM (Quadbit) Competitive with NOR, probably not a serious threat to high-density NAND

PCM, MRAM, Nanotubes, MilipedeNot a serious threat to high-density NAND in the next five years

2525

NVM Technology – Next Five Years (Cont’d)

3D Read/WriteLong-term potential to disrupt/displace NAND, HDDR/W switching actively researched: expected productization in the next several years (more on this later…)

2626

SanDisk 3D Technology Overview

2727

SanDisk 3D has brought to high volume an NVM where arrays of memory cells are stacked above control logic circuitry in the 3rddimension

Stacking 3D memory directly over CMOS allows for high array efficiency and very small die size

The technology uses no new materials, processes or Fabequipment

Control logic circuitry composed of typical CMOSMemory construction using typical backend processing toolsEach memory layer is a repeat of layers belowCMOS node can lag memory node (“hybrid scaling”)

Example: 0.13um-generation CMOS with 80nm-generation memory

The technology is inherently scalableMultiple technology generations proven using the same cell architectureLithography-driven scaling allows for rapid cost reduction

SanDisk 3D Technology Summary

2828

The 3D cell consists of a vertical diode in series with a memoryelement

State-change element is…Irreversibly altered in the case of OTP memoryReversibly altered in the case of re-writeable (R/W) memory

SanDisk 3D Memory Cell

State change element (e.g., antifuse)

Steering element (e.g., diode)

InputTerminal

OutputTerminal

S teeringE lem ent

S tateC hangeE lem ent

O utput2O utpu t1

O nw iring1layer

Input2

Input1

O n w iring1 layer

Input2

O n w iring2 layerO n w iring2 layer

Cell

Array

2929

SanDisk 3D OTP Memory Cell

n+ Si

metal

p+ Si

metal

n- Si

Anti-fuse

Programmed Cell Unprogrammed Cell

3030

OTP Memory Cell I-V Curve

1.E-14

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-8 -6 -4 -2 0 2 4 6 8 10

V

I [A

]

Vread Vprog

Memory Cell Window

> 4 orders cell window at 2V read voltage

Unprogrammedcell

Programmed cell

3131

OTP Memory Cell Read Window

Programmed

Unprogrammed

-4-5-6-7-8-9-10

99

95908070605040302010 5

1

Log(IF2)

Per

cent

Current at 2V for programmed and unprogrammed cells

Programmed cell

Unprogrammed cell

Wide [> 4 orders] read margin when considering distributions of millions of cells

3232

SanDisk 3D Physical Cross SectionMemory array is composed of repeating layers of poly-Si memory cells built directly above CMOS

LV + HV CMOS logic

2 levels of tungsten routing

4 layers of memory cells + tungsten interconnect

Al top metal

3333

SanDisk 3D Array ArchitectureSIDE VIEW

3D VIEW

TOP VIEW

WL

WL

WL

BL BL BL BL

3434

SanDisk 3D R/W Cell Development Update

OTP and R/W cell developments are tightly coupled and share most of the process module and design architecture ideas

Recall that the identity and behavior of the switching element defines OTP or R/W capabilities

Several parallel research activities are being pursued, exploring several types of switching behavior

We have produced several distinctly different cells, each capable of being integrated into the existing 3D architecture

We have developed a test vehicle to test out some of the ideas being generated that allows us to rapidly collect statistics on large number of cells

We are seeing very encouraging results from our development efforts – please stay tuned for results in the near future…

3535

Overall Concluding Remarks

The flash memory marketplace is one of the most vibrant and exciting in the semiconductor industry, not to mention one of the most competitive

The dominant flash cell architecture, the conventional floating gate, will see significant, if not unsurpassable, scaling challenges below the 2x nm technology node

In order to continue the pace of price reductions that consumersdemand, significant innovation is needed, both at the device andsystem level

Many candidate device architectures are in development; we are strong believers that 3D is a viable candidate