ECE2411: Logic Circuits II

Abstract—Lab 1 was to design and build a 3-bit counter, using 3 LED lights for the counting in binary and a fourth for overflow. The team designed and created this circuit using a total of 5 chips: two J-K flip flops, one 2-input OR, one 3-input AND, and one 4-input AND. Successfully accomplishing the goal set forth, the teams design and building techniques were a success.

I. INTRODUCTION AND DISCUSSION

HE counter is very commonly used for many different kinds of devices. Counters are the building blocks for

more complicated circuitry, including digital speedometers, the counters at DMV, timing for systems, clock or data delay, and plenty of other devices used in this day and age.

T

The teams’ circuit was designed to count in binary using three LED lights that count from 000 up to 111 and by flipping a switch will force the circuit to count down from 111 to 000. When the circuit reached 111 and flipped back over to 000 the overflow light would illuminate for 1 clock pulse to signify that an overflow had occurred, this would also happen if the circuit counted down reaching 000 the light would then illuminate at 111 for 1 clock pulse. (For a visual of this process see FIG. 1)

Using the 7400 series logic and the teams’ knowledge of combinational and sequential logic, the team was successful in completing and demonstrating the circuit. The circuit performed up to standards and executed the job the team had designed it to accomplish.

A. Design of the CounterTo design the counter, the team had to first construct a

state diagram, which included the binary representation of the decimal numbers zero through seven. Designed to count up to seven and if the counter past seven resetting itself to (000) or technically the decimal number 8 (binary number 1000) an extra light would turn on for one pulse to indicate that there had been a carry bit. Likewise, the counter could count down and if it passed the value of zero resetting itself to (111), the carry bit would be activate again for one clock pulse.

Next the team translated the state diagram into a state table, which identified present state and inputs, next state and outputs (the carry bit), and the required JK flip flop values.

Once the JK flip flop values were obtained, the team transferred these values to Karnaugh maps to find the simplest form of the combinational logic to feed into the flip flops. This process was also executed for the carry-bit output.

The last step in the design phase was to draw the schematic. Images of each step can be seen in Results.

B. Building the CounterAfter design was complete the team was able to

construct the counter using 7400 series logic gates and a logic box. It was determined that the team’s design required a two input OR chip, a two input AND chip, a three input AND chip, a four input AND chip, and two JK-FF chips. The chips chosen were 7432, 7408N, 7411, 7421, and 7473 respectively.

II.RESULTS

Result task A: Design went pretty fast for the team, sitting down

brainstorming the state diagram, to converting the state diagram into a state table, then utilizing the excitation table to create the inputs on the JK-FF, then using Karnaugh maps to come up with state equations, and last but not least the team transferred the state equations into a schematic to build the circuit from. The team did a wonderful job with no problems or issues producing a flawless schematic.

The state diagram was created with the conditions that the x input of zero caused the counter to count up and the x input of one caused the counter to count up. An output of one indicates a carry bit occurred.

Figure 1 State Diagram

Following is the completed state table.

Present State

Input

Next State Output

JK Flip Flops

A B C X A B C Y JA KA JB KB JC KC

0 0 0 0 0 0 1 0 0 X 0 X 1 X0 0 0 1 1 1 1 1 1 X 1 X 1 X0 0 1 0 0 1 0 0 0 X 1 X X 10 0 1 1 0 0 0 0 0 X 0 X X 1

3-bit CounterBryan Castine and Melissa Spencer

1

ECE2411: Logic Circuits II

0 1 0 0 0 1 1 0 0 X X 0 1 X0 1 0 1 0 0 1 0 0 X X 1 1 X0 1 1 0 1 0 0 0 1 X X 1 X 10 1 1 1 0 1 0 0 0 X X 0 X 11 0 0 0 1 0 1 0 X 0 0 X 1 X1 0 0 1 0 1 1 0 X 1 1 X 1 X1 0 1 0 1 1 0 0 X 0 1 X X 11 0 1 1 1 0 0 0 X 0 0 X X 11 1 0 0 1 1 1 0 X 0 X 0 1 X1 1 0 1 1 0 1 0 X 0 X 1 1 X1 1 1 0 0 0 0 1 X 1 X 1 X 11 1 1 1 1 1 0 0 X 0 X 0 X 1

Figure 2 - State Table

The state table produced the following Karnaugh maps and input equations. It was found that all K input equations were the same as their paired J input equations.

JA

CXAB 00 01 11 00

00 0 1 0 001 0 0 0 110 X X X X11 X X X X

Karnaugh Map 1 - JK Flip Flop A

Equation 1 - JK Flip Flop AJA = B’C’X+BCX’KA = JA

JB

CXAB 00 01 11 00

00 0 1 0 101 X X X X10 X X X X11 0 1 0 1

Karnaugh Map 2 - JK Flip Flop B

Equation 2 - JK Flip Flop BJB = C’X+CX’KB = JB

JC

CXAB 00 01 11 00

00 1 1 X X01 1 1 X X10 1 1 X X11 1 1 X X

Karnaugh Map 3 - JK Flip Flop C

Equation 3 - JK Flip Flop CJC = 1

KC = JC

Using these equations the schematic was developed:

Schematic 1

Result task B:The final results were a superb success; the team used

the X-switch from the James Bond suitcase, to control whether or not the circuit would count up or down. However the first attempt was not so successful, in the first building of the circuit one of the team members, made the mistake of thinking a 74109 would suffice for a JK-FF, however the team learned very quickly that this was not the case. Despite the chip being called a JK-FF, this particular brand of JK did not act in the way the team understood the chip to behave. After rigorous amounts of work to wire this chip up and get everything in place the results were disappointing. Failing to achieve what the circuit was suppose to do the team moved into troubleshooting. The issue in this case was that the lights would come on from right to left and once all three counter lights were illuminated the overflow would illuminate and all the lights would stay on. If the switch was flipped, the circuit would simply de-illuminate from left to right, the far left light would go out along with the overflow, and it would count down until the far right light was on, which would stay illuminated. After an hour or so

2

ECE2411: Logic Circuits II

of looking over the circuit the team came to the conclusion that the JK-FF chips weren’t behaving normally. Once the team swapped out the 74109’s for the 7473’s, the circuit behaved correctly, making the design a complete success. For a picture of the final build, see Appendix, Picture 1.

III. CONCLUSION

In the end lab was a complete success, however, the team should make an adjustment to their approach in choosing the correct type of chips. If the behavior of the chip does not seem familiar to the team’s understanding of that type of chip, they should investigate the issue further. Once the team has found a chip that meets specifications, and appears to behave appropriatly the team should then advance to the next stage. This will save time and confusion, and undesired troubleshooting time in future projects. After completion of this lab the team has gained a better understanding of counters and how to design them.

REFERENCES

K r e s s i n , R o b e r t . " L a b 1 . "   F A L L 2 0 1 1 E C E 2 4 1 1S E C 0 0 1 - L o g i c C i r c u i t s I I L a b s . B l a c k b o a r d , n . d .

W e b . 1 7 O c t 2 0 1 1 . < h t t p s : / / b b . u c c s . e d u / b b c s w e b d a v / p i d - 5 8 1 1 4 9 - d t -

c o n t e n t - r i d - 1 8 2 8 0 2 9 _ 2 / c o u r s e s /2 1 1 7 _ C U S P G _ E C E _ 2 4 1 1 _ S E C 0 0 1 / E C E 2 4 1 1 L a b

1 . p d f > .

" T I H a n d b o o k o n F l i p F l o p s . p d f . " F A L L 2 0 1 1 E C E2 4 1 1 S E C 0 0 1 - L o g i c C i r c u i t s I I . T e x a s

I n s t r u m e n t s , n . d . W e b . 1 7 O c t 2 0 1 1 . < h t t p s : / / b b . u c c s . e d u / w e b a p p s / b l a c k b o a r d / e x e c u t e / c

o n t e n t / f i l e ?c m d = v i e w & c o n t e n t _ i d = _ 5 8 1 1 4 7 _ 1 & c o u r s e _ i d = _ 9 6

2 4 2 _ 1 > .

Biography

Bryan Castine is a sophomore at UCCS pursuing bachelors in Electrical Engineering. Born and raised in Colorado Springs, he graduated from pine creek high school in 2002, which was followed by giving 7 years of his

life to the US Army carrying a Top Secret security clearance while working on UAV’s, Guardrail and a multitude of other intelligence systems.

Melissa Spencer is a senior pursuing her undergraduate degree in Business Innovation and Electrical Engineering at University of Colorado at Colorado Springs.  She is working under Dr. Terrance Boult on the ALIIVE (Advance Live-fire Integrated Intelligent Virtual Environment) project team developing a virtual combat training system.  Her interests include poetry, music composition and performance, baking and pastry arts, team psychology of collaboration and innovation, teaching, and the exploration of technological advancements and their social impact.

APPENDIX A

3

ECE2411: Logic Circuits II

Picture 1

4