ARM Introduction

Data source: S3C4510B Datasheet

張大緯CSIE, NCKU

ARM Introduction

ARM ArchitectureARM Data TypesARM Operating ModesARM Operating StatesARM RegistersARM Exceptions

ARM Architecture

Reduced Instruction Set Computer (RISC) architecture

A large set of registersA load-store architecture

Process values in registers and place the results into a register

3-address instruction formatsTwo source operand registers and the result register are all independently specified

ARM Architecture (Cont.)

Conditional execution of every instruction

Powerful load/store multiple register instructions

Open instruction set extension through the coprocessor instruction set

ARM VersionsVersion 1

The first ARM processorDeveloped at Arcon Computers Limited between 1983~1985Supported only 26-bit addressing and had no multiply or coprocessor support

Version 2Still 26-bit address machineBut included the 32-bit result multiply instruction and coprocessor support

Version 2aThe ARM3 chip was the first ARM with an on-chip cacheAdded the atomic load and store (SWP) instructionIntroduced the use of coprocessor 15 as the system control coprocessor to manage the cache

ARM Versions (Cont.)

Version 3The first ARM processor designed by ARM Limited following their establishment as a separate company in 1990 was the ARM6Had 32-bit addressingSeparate CPSR and SPSRsAdded the undefined and abort modes to allow coprocessor emulation and virtual memory support in supervisor modeBackward compatible with version 2a

Version 3GVersion 3 without backwards compatibility to version 2a

Version 3MIntroduced the signed and unsigned multiply and multiply-accumulateinstructions that generate the full 64-bit result

ARM Versions (Cont.)

Version 4Add the signed and unsigned half-word and signed byte load and store instructionsReserve some of the SWI space for architecturally defined operationsIntroduced the system mode

A system mode that uses the user registersVersion 4T

Introduced the 16-bit Thumb compressed form of the instruction set

Version 5TA superset of architecture version 4T, adding the BLX, CLZ and BPK instructions

Version 5TEAdd the signal processing instruction set extensions

Summary

v5TEARM10TDMI, ARM1020E, Xscalev5TEARM9E-Sv4TARM9TDMI, ARM920T, ARM940Tv4StrongARM, ARM8, ARM810v4TARM7TDMI, ARM710T, ARM720T, ARM 740Tv3ARM7, ARM700, ARM710v3ARM6, ARM600, ARM610v2aARM2aS, ARM3v2ARM2v1ARM1ArchitectureCore

ARM Data Type

The standard ARM word is 32 bits longWord may be divided into four 8-bit bytes

ARM allow addresses to be 32 bits longAn address refer to a byte, not a wordWord 0 is at location 0Word 1 is at location 4PC is incremented by 4 in sequential access

Can be configured at power-up to address the bytes in a word in either little-endian or big-endian mode

Big-endian v.s. Little-endian

Big-endianthe most significant byte of a word is stored at the lowest numbered byte

Little-endianThe least significant byte of a word is stored at the lowest numbered byte

ARM supports both little-endian and big endian

ARM Operating ModesUser mode:

a normal program execution stateFIQ (Fast Interrupt Request) mode:

for supporting a specific data transfer or channel processingIRQ (Interrupt ReQuest) mode:

for general purpose interrupt handlingSupervisor mode:

a protected mode for the operating systemAbort mode:

entered when a data or instruction pre-fetch is abortedSystem mode:

a privileged user mode for the operating systemUndefined mode:

entered when an undefined instruction is executed

ARM Operating Modes (Cont.)

Operating mode changes Can be controlled by software.Can also be caused by external interrupts or exception processing

Most application programs execute in user mode.

Privileged modes (that is, all modes other than User mode) Are entered to service interrupts or exceptions, or to access protected resources.

Thumb

Code size matters!An extension of the basic ARM architecture16-bit instructions

More compactFrom a programmers point of view, the ARM core is always in one of two operating states

ARM or THUMB

ARM Operating States

ARM state Executing 32-bit, word-aligned, ARM instructions

THUMB state Executing 16-bit, half-word aligned THUMB instructions

These states can be switched by software or by exception processing

ARM Registers

ARM has a total of 37 registers31: general-purpose, 32-bit registers

r0~r15, r8_fiq~r13_fiq, r14_fiq, r13_irq, r14_irq, r13_svc, r14_svc, r13_abt, r14_abt, r13_und, r14_und

6: status registersCPSRSPSR_fiq, SPSR_irq, SPSR_svc, SPSR_abt, SPSR_und

Not all of these registers are always availableProcessor state: ARM or ThumbOperating mode

Unbanked registers: r0~r7Banked registers: r8~r14

ARM RegistersIn privileged (non-User) modes, mode-specific banked registers are switched in.

FIQ handler usually needs not save registers since it has many banked registers

Register Organization in ARM States

r0~r12, r13_und, r14_und, PC, CPSR, SPSR_undUndefined Mode

r0~r12, r13_abt, r14_abt, PC, CPSR, SPSR_abtAbort Mode

r0~r12, r13_svc, r14_svc, PC, CPSR, SPSR_svcSupervisor Mode

r0~r12, r13_irq, r14_irq, PC, CPSR, SPSR_irqIRQ Mode

r0~r7, r8_fiq~r13_fiq, r14_fiq, PC, CPSR, SPSR_fiqFIQ Mode

r0~r13, LR(r14), PC (r15), CPSRUser Mode & System Mode

RegistersMode

Register Organization in ARM States

ARM RegistersBy convention

r13: SP (stack pointer)r14: LR (link register)

In User mode: r14 is used as a link register to store the return address when a call to a subroutine is madeIn the exception handling modes, r14 holds the return address for the exception

r15: PC (program counter)Incremented by one word for each instructionTo return from a subroutine

MOV pc, lr

PSR Registers

The format of CPSR and SPSR are the sameCalled PSR in general

One CPSR (Current Program Status Register)Copies of the Arithmetic Logic Unit (ALU) status flagsThe current processor modeInterrupt disable flags

Five SPSR (Saved Program Status Registers)Used to store the CPSR when an exception is takenOne SPSR is accessible in each of the exception-handling modeUser mode and System mode do not have an SPSR because they are not exception handling modes

PSR RegisterFlag field: PSR[31:24], ARM7TDMI only defines four bits

PSR[31]: N, PSR[30]: Z, PSR[29]: C, PSR[28]: VStatus field: PSR[23:16], undefined in ARM7TDMIExtension field: PSR[15:8], undefined in ARM7TDMIControl field

I: PSR[7]: if 1, disable interruptF: PSR[6]: if 1, disable fast interruptT: processor is in ARM state (T=0) or in Thumb state (T = 1)Mode: processor mode

N Z C V undefined I F T mode

31 30 29 28 24 23 8 7 6 5 4 0

Status Bits

Top four bits of the CPSRN: set when the result is negative in two’s-complement arithmeticZ: set when every bit of the result is zeroC: set when there is a carry out of the operationV: set when an arithmetic operation results in an overflow

PSR Registers (Cont.)

MSR and MRS Instructions

To access the CPSR and SPSR registers, you must use the MSR and MRS instructionsMRS: Move PSR to a General-purpose RegisterMSR: Move Register to PSR status/flagsDiscussed later in the instruction set section

ARM ExceptionsAn exception arises when the normal flow of program execution is interruptedThe processor state just prior to handling the exception must be preserved

The program flow can be resumed when the exception routine is completed

To process exceptions, the S3C4510B uses the banked core registers to save the current state

The old PC value are copied into the R14 (LR) registerThe CPSR contents are copied into the SPSR registers.

ARM Exception Types

ResetUndefined instructionSoftware Interrupt (SWI)Prefetch AbortData AbortIRQFIQ

Exception Vectors

Exception Priorities

Note: the ordering is different from that of the previous slide.

References

ARM Developer Suite: Developer Guide, ARM Limited.ARM Developer Suite: Assembler Guide, ARM Limited.Steve B. Furber, “ARM System-on-Chip Architecture,” Addison-Wesley, 2000